KR20030049445A - Apparatus For compensating timing margin of data communication module using same clock by controlling clock - Google Patents

Abstract

PURPOSE: An apparatus for controlling and compensating a timing margin of data communication between modules using same clock is provided to obtain data from a stable block in a data transmission and reception process by controlling quantitatively an operating clock portion. CONSTITUTION: A synchronous clock control portion(200) controls clocks of each module and the transmitting and the receiving directions. A synchronous clock generation portion(210) generates a synchronous clock. An unit clock delay portion(220) delays the synchronous clock generated from the synchronous clock generation portion. A plurality of output clock selection portions(230,240) output selectively output clocks of the unit clock delay portion. A synchronous clock control information storage portion(250) receives and stores a synchronous clock control signal and provides the stored synchronous clock control signal.

Description

Apparatus For compensating timing margin of data communication module using same clock by controlling clock}

The present invention relates to an apparatus for compensating the timing margin of data communication between modules using the same clock by adjusting a clock. An apparatus for securing timing margin by partially adjusting a pulse of a reference clock according to a transmission direction for each module. It is about.

In general, when data communication between two or more modules using the same clock occurs, if the operation clock speed is high, the timing margin often occurs.

Conventionally, the transmitting module itself takes one clock delay of data transmission and uses a clock synchronization buffer having a short output delay time in order to reduce the output delay time compared to the clock.

The configuration of the conventional apparatus assumes that there is a first module 110 and a second module 120 using the same clock source 100 as shown in FIG.

Referring to FIG. 1, when data is transmitted from the second module 120 to the first module 110, the first module for receiving data when the delay of the data transmission path or the interval in which the stable value of the signal is maintained is narrow ( The probability that the reception of 110) receives the correct data is reduced by that much.

Constraints of primary data reception are a clock to output delay of the second module 120 and a setup time of the first module 110. Here, the clock-to-output delay is time information indicating the degree to which the output of the final output stage is delayed and output as compared with the rising portion of the clock in the case of a circuit operating on a synchronous clock. In the case of a circuit operating on a synchronous clock, the setup time is time information indicating the input waiting time at which the input of the input terminal should wait for the input in advance compared to the rising part of the clock. For example, if the clock of the clock source is 100 MHz, the clock-to-output delay of the second module 120 is 6 ns, and the setup time of the first module 110 is 2 ns, the spare time for supplying stable data is 2 ns. do. If a transmission delay of 2 ns or more or an unstable portion of a signal is generated, and the interval for maintaining a stable value is narrowed, the probability that the first module 110 can receive accurate data is reduced.

Conventionally, the method used due to such general constraints uses a clock synchronization buffer 130 with a small clock output delay to secure insufficient transmission time margin. If the clock output delay of the clock synchronizing buffer 130 is 3 ns, a delay of one clock data occurs but a transmission time margin of 10 ns-(3 + 2) ns = 5 ns can be secured.

As described above, the related art has a problem in that unnecessary one clock delay is included in a transmission / reception process, and additional components must be used on a constrained transmission path.

Accordingly, an object of the present invention is to provide an apparatus for compensating for adjusting timing margins in data communication between two or more modules using the same clock.

Another object of the present invention is to provide an apparatus for securing timing margin by partially adjusting a pulse of a clock, which is a reference in data communication between two or more modules using the same clock, according to a transmission direction for each module.

According to an aspect of the present invention, there is provided a synchronization clock controller for controlling a clock and a transmission / reception direction for each module; A synchronous clock generator for generating a synchronous clock; A unit clock delay unit for delaying the synchronous clock inputted from the synchronous clock generator for each state; An output clock selector which receives the clocks output from the unit clock delay unit and selectively outputs the clocks; And a synchronous clock control information storage unit for receiving and storing the synchronous clock control signal and providing the same to the output clock selector. Here, the synchronous clock control signal is information for determining which of the 1-M state outputs represents the clock of the module with respect to the clock output of each module. The unit clock delay unit according to the present invention comprises a plurality of buffers for receiving a synchronous clock generated from the synchronous clock generator and delaying a clock for each state. In addition, the output clock selector according to the present invention exists as many as the number of modules to select and output a suitable synchronous clock for each module.

1 is a structural diagram of a data communication margin compensation circuit between a conventional clock synchronization module;

2 is a block diagram of a synchronous clock control device according to an embodiment of the present invention.

3 is a block diagram of a system to which the present invention is applied.

4 is a diagram showing the margin of each clock for each module using the same clock.

5 is an output diagram of a synchronous clock control device according to an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram of a synchronous clock control apparatus according to the present invention, wherein the first to Mth state buffers 221 to 22M which are the synchronous clock controller 200, the synchronous clock generator 210, and the unit clock delay unit 220. ), An output clock selector 230 and 240, and a synchronous clock control information storage unit 250.

Referring to FIG. 2, the synchronous clock controller 200 receives a clock control path and a transmission / reception direction control path for each module to control the synchronous clock.

The synchronous clock generator 210 generates a synchronous clock and supplies it to the first state buffer 221 which is the unit clock delay unit 220.

The output clock selectors 230 and 240 receive a synchronous clock output from the synchronous clock generator 210 and output signals of an even number of unit clock delay buffers 221 to 22M, and have clock outputs for each module. In addition, the output clock selectors 230 and 240 receive a synchronous clock control signal of a clock used in each module from the synchronous clock control information storage unit 250. That is, the output clock selectors 230 and 240 receive the respective synchronous clocks from the synchronous clock generator 210 and the first to M state buffers 221 to 22M, respectively, and synchronize from the synchronous clock control information storage unit 250. The clock control signal is applied to select and output a synchronous clock for each module.

The synchronous clock control information storage unit 250 receives and stores the synchronous clock control signal, and applies the synchronous clock control signal to the output selection units 230 and 240.

3 illustrates an example of transmitting data from the second module 320 to the first module 310 using the synchronous clock control device according to the present invention.

The synchronous clock control apparatus according to the present invention has a general synchronous data transmission scheme, and the difference from the general scheme is that the phase of the clock input to the module is controlled.

Referring to the operation of the synchronous clock control apparatus, as shown in FIG. 2, the synchronous clock generator 210 is provided as a clock supply source, and the even number M unit clock delay units 220 are provided. The clock output to each module is connected to the output of the unit clock delay unit 220 and is selected and output by the control signal during the 1-M state output.

The reference of the whole module clock is the output of the M / 2-th unit clock delay unit 220, and the phase of the clock is changed as shown in FIG.

Accordingly, when M = 12, the delay of the clock phase occurs as the state increases by 1 with respect to the M / 2 state, and the output is output. As the decrease by 1, the clock phase advances. Also, the change in the M state includes one period of the clock.

If data is transmitted from the second module 320 to the first module 310 as shown in FIG. 2, the data is output after being delayed by the clock-to-output delay of the second module 320. Data should be transmitted as early as the setup time of one module 310.

Accordingly, in order to overcome such timing constraints, the present invention delays the clock of the receiving side by a time t as shown in FIG. 4 to secure timing margin.

On the contrary, when the first module 310 transmits data and the second module 320 receives the data, the clock output characteristic of the module must be changed to control the synchronous clock control signal so that the clock output has the opposite concept. Here, the synchronous clock control signal provides information regarding the clock output of each module to determine which of the 1-M state outputs represents the clock of the module.

As shown in FIG. 2, when each information is stored according to transmission and reception to provide separate transmission / reception information, the control signal may be converted according to a preset clock output of each module.

As described above, according to the present invention, when the synchronous data transmission is performed, the data must exist within a stable region during a clock cycle, and must be solved if there are physical constraints on timing.

Thus, the present invention solves the problem by quantitatively controlling the fixed and difficult-to-control operation clock to enable the acquisition of data in a stable zone during data transmission and reception.

As described above, the present invention increases the number of control signals at the time of transmission and reception, but there is no effect of one clock delay in timing compared to the conventional method, and it is possible to quantitatively control from an external processor.

Claims (4)

An apparatus for adjusting a clock to compensate for a timing margin of data communication between modules using the same clock. A synchronous clock control unit controlling a clock for each module and a transmission / reception direction; A synchronous clock generator for generating a synchronous clock; A unit clock delay unit for delaying the synchronous clock inputted from the synchronous clock generator for each state; An output clock selector which receives the clocks output from the unit clock delay unit and selectively outputs the clocks; And a synchronous clock control information storage unit for receiving and storing the synchronous clock control signal and providing the same to the output clock selector. The display apparatus of claim 1, wherein the unit clock delay unit; And a plurality of buffers configured to receive a synchronous clock generated from the synchronous clock generator and delay a clock for each state. The apparatus of claim 1, wherein the output clock selector comprises: an output clock selector; Apparatus characterized in that the number of modules exist to select and output the appropriate synchronous clock for each module. 2. The synchronization clock control signal of claim 1, further comprising: a synchronous clock control signal; Providing information for determining which of the 1-M status outputs represents the clock of the module with respect to the clock output of each module.