KR100546097B1 - Control and Address Clock Non-Distributed Memory System - Google Patents

Abstract

The present invention relates to a memory system having a plurality of memory devices, and more particularly, to a memory system in which a clock for sampling control and address signals is eliminated. A control device for outputting a plurality of control and address input signals and a second clock signal divided by an integer multiple of the first clock signal and the first clock signal respectively corresponding to the memory device of the memory device, and the control and address input signal from the control device. And a register and a delay circuit unit configured to receive a second clock signal and correct a transfer delay caused by a transmission line from an output buffer to the memory device and a transfer delay occurring in an internal output buffer to output a control and address output signal. The plurality of memory devices may include the register and the delay circuit unit. The control and address output signals are respectively received through a transmission line, and the control and address output signals are sampled using a first clock signal directly input from the control device, thereby simplifying the layout of a semiconductor device design and a clock conflict problem. There is an effect that can be avoided.

Description

Control and Address Clock Non-distributed Memory System

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.

2 is a detailed block diagram of a register and a delay circuit according to an embodiment of the present invention.

3 is a block diagram of a conventional control and address clock distribution memory system.

<Description of Symbols for Major Parts of Drawings>

10: controller 20: PLL circuit

30: register 40: register and delay circuit

42: DLL circuit 44: first replica circuit

43: second replica circuit

The present invention relates to a memory system having a plurality of memory devices, and more particularly, to a memory system in which a clock (Command / Address Clock) (CACLK) for sampling a control and address (Command / Address) signal is removed.

In the case of a dual in line memory module (DIMM), a clock control apparatus of a conventional memory device includes a register chip for buffering a control and address input signal and a phase locked loop (PLL) chip for generating a timing signal. In addition, when a plurality of PLL output clocks are generated, a compensation capacitor (C _comp ) is used to control their edge timings.

3 is a configuration diagram showing an example of a conventional control and address clock signal distribution type memory system. The PLL circuit 20 performs edge control using the compensation capacitor Ccomp in consideration of the signal delay generated in the transmission line and the control and address clock signal CACLK inputted from the controller 10, and then performs edge control again. The control and address signals CACLK and the phases of the control and address signals CACLK inputted from the control device 10 are adjusted to coincide with each other, respectively, to each of the plurality of memory devices 61, 62, 63, and 64. It is applied as a separate clock (CLK0, CLK1, CLK2, CLK3). At this time, the plurality of control and address input signals CAin output from the control device 10 are buffered in the register 30 and then each through a transmission line for distributing the address clock signal CACLK and a separate transmission line. Are output to the plurality of memory devices 61, 62, 63, 64.

The above method has the following problems. First, the semiconductor device design layout is complicated by having control and address clock signal transmission lines corresponding to the number of memory devices for independently transmitting control and address clock signals to each memory device separately from the control and address signals. Become. Second, since the memory device receives a write data capture clock (WCLK) separately from the control and address clock signals, a clock domain collision problem may occur between the control and address clock signals and the write data capture clock. Third, because each memory device must have a separate PLL or DLL circuit, this increases not only the production cost of the entire system but also the jitter. Fourth, since the register and the PLL circuit must be implemented as separate chips, the manufacturing of two chip packages increases the complexity of the semiconductor device process and increases the production cost. Fifth, the variation of multiple compensating capacitors lowers the timing margin of the overall system.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. Since the control and address clock signals are not directly supplied to the memory device, the semiconductor design layout is simplified by eliminating the transmission lines for distributing the control and address clock signals (CACLK). The device prevents clock domain collisions by sampling the control and address signals into a write data capture clock or clock signal divided by an integer multiple, thereby eliminating the need for a separate PLL circuit or DLL circuit, thereby reducing production yield and jitter. The objective is to provide a memory system that improves performance and prevents the timing margin degradation of the system due to variations in multiple compensation capacitors.

It is an object of the present invention to provide a memory system in which the number of production is reduced by unifying a register chip and a PLL or DLL chip.

A control and address clock non-distribution type memory system of the present invention for achieving the above object includes a write data for sampling control and address output signals and data to a plurality of memory devices in a memory system including a plurality of memory devices; A control device for outputting a clock and outputting a plurality of control and address input signals and a control and address clock respectively corresponding to the plurality of memory devices; And a register and a delay circuit unit receiving a plurality of control and address input signals according to the control and address clocks, and outputting control and address output signals corrected for transmission delays due to the transmission lines to the plurality of memory devices through the transmission lines. It is characterized by including.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall configuration diagram of a control and address clock non-distribution type memory system according to an exemplary embodiment of the present invention. As shown in FIG. 1, the control device 10 for controlling the overall operation of the memory system applies a control and address input signal CAin to the register and delay circuit unit 40.

The register and delay circuit unit 40, which receives the control and address input signal CAin, transmits and delays due to a transmission line connected from the register and delay circuit unit 40 to the memory devices 61, 62, 63, and 64. The transmission delay generated in the output buffer is corrected to output the corrected control and address output signal CAout. Preferably, the transmission delay of the transmission line at this time may be a transmission delay from the point A starting at the register and the delay circuit unit 40 to the specific point B in each of the plurality of transmission lines. In addition, the internal propagation delay may include a propagation delay occurring within a register of the control and address signal CAin and a delay circuit. The plurality of memory devices 61, 62, 63, and 64 receive the control and address output signals CAout output from the register and delay circuit unit 40 through a transmission line, and input the control and address output signals CAout. Is sampled using a write data clock (hereinafter, referred to as a first clock signal WCLK) directly input from the control device 10. Therefore, since the memory system according to the present invention does not use a separate control and address clock signal, a separate wiring line for the control and address clock signal is unnecessary unlike a conventional memory system, and multiple clocks are not input to the memory device. Instead, since the control and address signals CAout are sampled using only the write data clock WCLK, there is no collision between clock domains.

2 is a detailed structural diagram of a register and delay circuit unit 40 according to an embodiment of the present invention.

The register unit 30 controls the control and address input signals CAin_i to CAin_j inputted from the control device 10 by using an internal clock (hereinafter referred to as a third clock signal: intCLK). CAout_i ~ CAout_j) are displayed. At this time, the clock control circuit 41 corrects the transfer delay caused by the transmission line of the control and address clock (hereinafter, the second clock signal CACLK) input from the control device 10 and the transfer delay generated from the internal output buffer. Generate a clock signal. Preferably, the transmission line transfer delay at this time may be a transfer delay from a point A starting from the register and delay circuit unit 40 to a specific point B. In addition, the transfer delay from the output buffer input point C to the output point D in the register and delay circuit portion 40 of the control and address signals is mainly occupied by the internal output buffer transfer delay.

Preferably, the clock control circuit 41 includes a DLL circuit 42, a first replica circuit 44 for modeling delay transmission of a transmission line, and a transfer model for modeling a propagation delay of an internal output buffer as shown in FIG. It consists of two replica circuits 43. The DLL circuit 42 receives the second clock signal CACLK from the control device 10 and receives the feedback feedback signal back through the second replica circuit 43 and the first replica circuit 44 ( The delay is corrected with fbCLK_in to generate a third clock signal intclk having the same phase as the feedback output signal. The first replica circuit 44 is a circuit modeling the transmission delay between the register and delay circuit unit 40 and the memory devices 61, 62, 63, and 64 in an actual system, and is mainly connected outside the chip to adjust the transmission delay. It can be manufactured by a combination of general passive / active elements, but preferably manufactured by using control and address transmission lines and termination circuit models to offset the process / supply voltage / temperature deviation of the PCB board. In addition, the second replica circuit is a circuit for modeling the propagation delay of the internal output buffer, and preferably, the output buffer circuit model is used within the chip to cancel the process / power supply voltage / temperature deviation of the output buffer.

As described above, since the memory system according to the present invention does not directly supply control and address clock signals to the memory device, there is no transmission line for distributing control and address clock signals, thereby simplifying layout and controlling and addressing the memory devices. By sampling the signal into a write data capture clock, it avoids clock domain collisions and eliminates the need for a separate PLL or DLL circuit, resulting in lower production, improved jitter performance, and system timing due to variations in multiple compensation capacitors. There is a significant effect of providing a memory system that prevents margin deterioration. In addition, according to a preferred embodiment of the present invention, the number of production can be reduced by unifying the resistor chip and the PLL chip.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (19)

In a memory system including a plurality of memory devices, A control device for outputting a control and address output signal and a write data clock for sampling data to the plurality of memory devices, and outputting a plurality of control and address input signals and a control and address clock respectively corresponding to the plurality of memory devices; ; And A register configured to receive the plurality of control and address input signals according to the control and address clocks, and output the control and address output signals corrected for transmission delays due to transmission lines to the plurality of memory devices through the transmission lines, respectively. And a delay circuit unit. The method of claim 1, The register and delay circuit unit includes a clock control circuit that receives the control and address clock from the control device unit and outputs an internal clock correcting the transmission delay due to the transmission line; And And a register unit for buffering the control and address input signals of the control device and sampling the internal clocks to output the control and address output signals. The method of claim 2, And the clock control circuit and the register unit are implemented as a single chip. The method of claim 2 or 3, wherein the clock control circuit DLL circuit; And A first replica circuit for modeling a propagation delay of the transmission line; Wherein the DLL circuit controls the internal clock fed back through the control and address clock and the first replica circuit to be in the same phase so as to output the internal clock in which the transmission line transfer delay is corrected. system. The method of claim 4, wherein And the first replica circuit is a combination of a PCB line model, an active element, and a passive element, or at least one of them. The method of claim 2, The clock control circuit may receive the control and address clocks from the control unit and correct the transfer delay due to the transmission line and the transfer delay in the register unit to output the internal clock. The method of claim 6, And the clock control circuit and the register unit are implemented as a single chip. 8. The clock control circuit of claim 6 or 7, wherein the clock control circuit DLL circuit; A first replica circuit modeling a propagation delay of the transmission line; And A second replica circuit for modeling propagation delay in the register section; The DLL circuit adjusts the internal clock fed back through the control and address clock, the first replica circuit, and the second replica circuit to be in the same phase, so that the transmission line transfer delay and the register transfer delay are And output the corrected internal clock. The method of claim 8, And the first replica circuit comprises a combination of a PCB line model, a passive element, and an active element, or at least one of them. The method of claim 1, The transmission line comprises a global line from the register and the delay circuit portion to a branch point, branched from the branch point and connected to a plurality of memory units, respectively. delete The method of claim 10, The register and delay circuit unit receives the control and the address clock from the control unit for outputting the internal clock correcting the transmission delay due to the global transmission line; And  And a register unit for buffering the control and address input signals of the control device, sampling the internal clocks, and outputting the control and address output signals. The method of claim 12, And the clock control circuit and the register unit are implemented as a single chip. The method of claim 12 or 13, wherein the clock control circuit DLL circuit; And A first replica circuit for modeling a propagation delay of the global transmission line; Wherein the DLL circuit is configured to adjust the internal clock fed back through the second clock signal and the first replica circuit to be in the same phase so as to output the internal clock in which the transmission delay of the global transmission line is corrected. system. The method of claim 14, And the first replica circuit is a combination of a PCB line model, an active element, and a passive element, or at least one of them. The method of claim 12, The clock control circuit may receive the control and address clocks from the controller and correct the transfer delay due to the global transmission line and the transfer delay in the register unit to output the internal clock. The method of claim 16, And the clock control circuit and the register unit are implemented as a single chip. 18. The apparatus of claim 16 or 17, wherein the clock control circuit DLL circuit; A first replica circuit for modeling a propagation delay of the global transmission line; And A second replica circuit for modeling propagation delay in the register section; The DLL circuit adjusts the internal clocks fed back through the control and address clock, the first replica circuit, and the second replica circuit to be in the same phase, so that the global transmission line transfer delay and the register portion transfer delay are performed. And output the corrected internal clock. The method of claim 18, And the first replica circuit is a combination of a PCB line model, an active element, and a passive element, or at least one of them.

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