KR20010065679A - Clock controller of memory module - Google Patents

Abstract

PURPOSE: A clock controller of a memory module is provided to adjust the capacitance as well as the resistance of a feed back loop path of a PLL(Phase Locked Loop) device in order to synchronize the clock for stable loading. CONSTITUTION: The clock controller includes a capacitor coupler(10), and a loop path changer(20). The capacitor coupler is implemented between a feed back input pin of the PLL device and ground. The loop path changer selects one from plurality of feed back loop paths whose lengths are different from each other and which couples a feed back output pin of the PLL device with the feed back input pin of the PLL device. The loop path changer further includes the first through third loop path(L1,L2,L3). The first loop path includes the first and second selectors which are implemented between the feed back output pin of the PLL device and the feed back input pin. The second loop path includes the third and forth selectors which are implemented between the feed back output pin of the PLL device and the feed back input pin. The third loop path includes the fifth and sixth selectors which are implemented between the feed back output pin of the PLL device and the feed back input pin.

Description

Clock controller of memory module {CLOCK CONTROLLER OF MEMORY MODULE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock controller of a memory module. More particularly, the present invention relates to a clock controller of a memory module, and more specifically, to a memory controller used in a large-capacity system. The present invention relates to a clock controller of a memory module that can adjust skew using a PLL for stable use.

Nowadays, the transmission line lengths are equally arranged in a common clock structure in which the clock is inconsistent by the flight time, which is the time taken for the clock to be transmitted through the transmission line on the PCB as the system bus speed increases to 100 MHz or more. The clock transmission scheme is changing with a source synchronous structure that supplies a clock.

The clock mismatch can be eliminated by the above clock transmission method, but when the external clock and the internal clock are not synchronized with each other due to the time required to pass the clock buffer inside the chip, skew occurs. There is.

This skew is caused by the difference in electrical characteristics or propagation delay time of transmission line. Due to the inconsistency of the clock, when the memory is loaded into a medium-large computer system, the system is down due to loss of data when loading. There is a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to achieve stable loading by synchronizing clocks by adjusting capacitance and resistance of a feedback loop pass of a PLL device for a clock mismatch caused by skew. To provide a clock controller of a memory module.

1 is a circuit diagram showing a PLL element portion of a clock controller of a memory module according to the present invention.

-Explanation of symbols for the main parts of the drawings-

10 capacitor connection part 20 loop path setting part

30: PLL element FC: feedback capacitor

12,14: first to second pad

S1, S2, S3, S4, S5, S6: 1st to 6th selection unit

L1, L2, L3: First to Third Loop Pass

The present invention for achieving the above object is a clock controller of the memory module, the capacitor connection between the feedback input pin and the ground of the PLL device, and between the feedback output pin of the PLL device and the feedback input pin of the PLL device And a loop path changing unit for selecting a plurality of feedback loop paths having different path lengths.

The present invention made as described above finely synchronizes the external clock and the internal clock inputted by the capacitor of the feedback input stage of the PLL element and the resistance of the feedback loop pass due to the skew of the clock, so that the system can be stably operated. Instead, random skew is generated to analyze the margin of the memory device.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.

1 is a circuit diagram showing a PLL element portion of a clock controller of a memory module according to the present invention.

As shown here, a capacitor capacitor 10 is formed between the feedback input pin FBIN and the ground GND of the PLL element, and connects the feedback output pin FBOUT and the feedback input pin FBIN. A loop path changing unit 20 for selecting the first to third loop paths L1, L2, and L3 having different path lengths is formed.

The capacitor connection unit 10 is configured to connect the feedback capacitor FC between the first pad 12 connected to the feedback input pin FBIN and the second pad 14 connected to the ground GND.

In addition, the loop path changing unit 20 may include a first loop path in which the first selector S1 and the second selector S2 are mediated between the feedback output pin FBOUT and the feedback input pin FBIN of the PLL device. A second loop path L2 in which the third selector S3 and the fourth selector S4 are interposed between the L1 and the feedback output pin FBOUT and the feedback input pin FBIN of the PLL element, A third loop path L3 in which a fifth selector S5 and a sixth selector S6 are interposed between the feedback output pin FBOUT and the feedback input pin FBIN of the PLL element.

In this case, the lengths of the first to third loop paths L1, L2, and L3 are different from each other. Therefore, since the load varies depending on the length of the first to third loop paths L1, L2, and L3, the characteristics of the PLL can be finely adjusted.

The external clock is input to the input pin CLK_IN, and the output pin CLK_OUT is connected to the clock terminal of each memory device.

Referring to the operation of the present embodiment made as described above are as follows.

The first pad 12 and the second pad 14 of the capacitor connection part 10 of the PLL when skew occurs when the skew occurs without synchronizing between the external clock inputted through the input pin CLK_IN and the internal clock outputted to the output pin CLK_OUT. A feedback capacitor (FC) of 24 kHz to 27 kHz is installed between the circuits to adjust the delay value of the clock. The loop path change unit 20 is set by calculating an optimum length of the loop path to be fed back.

That is, when the second loop path L2 is to be used, the feedback output pin FBOUT and the feedback input pin FBIN are connected to each other when the third selector S3 and the fourth selector S4 are connected to each other. The two loop paths L2 are connected to each other to correct the characteristics of the PLL by the load value of the second loop path to synchronize the clock.

Therefore, when the PLL does not have ideal characteristics, the clock may be fine tuned by adjusting the capacitance value of the feedback capacitor FC and the length of the loop path connecting the feedback output pin FBOUT and the feedback input pin FBIN.

In addition, when the loop path changing unit 20 connects the first to sixth selection units S1 to S6, 0 연결 connection means is used. However, when the resistance value is added to the loop path, the loop path changing unit 20 may use a resistance of 20 Ω or less.

Meanwhile, the feedback capacitor FC and the loop path changing unit 20 are arbitrarily adjusted to adjust the length and resistance of the loop path to generate skew on the clock to analyze the margin of data access time and hold time of the memory device. It may be.

As described above, according to the present invention, the skew between the external clock and the internal clock is controlled by adjusting the resistance value and the feedback capacitance value according to the length of the feedback loop path of the PLL device, thereby suppressing the skew and thereby performing stable loading. There is an advantage to this.

In addition, by arbitrarily adjusting the skew, there is an advantage that the margin of the clock can be analyzed in the loading operation of the memory device.

Claims (4)

In the clock controller of the memory module, A capacitor connection mediated between the feedback input pin of the PLL element and ground; A loop path changing unit for selecting a plurality of feedback loop paths having different path lengths between the feedback output pin of the PLL device and the feedback input pin of the PLL device; Clock controller of a memory module, characterized in that made. The method of claim 1, wherein the loop path changing unit A first loop path having a first selector and a second selector interposed between the feedback output pin and the feedback input pin of the PLL element, A second loop path having a third selector and a fourth selector interposed between the feedback output pin and the feedback input pin of the PLL element, Third loop path in which the fifth selector and the sixth selector are interposed between the feedback output pin and the feedback input pin of the PLL element. Clock controller of the memory module, characterized in that consisting of. The clock controller of claim 2, wherein the first to third loop paths have different lengths. The clock controller of claim 1, wherein a capacitance value of the feedback capacitor connected to the capacitor connection unit is 24 μs to 27 μs.