TW202321935A - Synchronization correction method, master device and slave device - Google Patents

Abstract

The disclosure provides a synchronization correction method, a master device and a slave device. The method includes: in a first period of an i-th second, sending a synchronization signal frame to the slave device, wherein the synchronization signal frame includes a synchronization header, a pulse per second (1PPS) signal, a first time of date (ToD) information, and a first phase compensation information, wherein the first phase compensation information is used to request the slave device to correct a transmission time point at which a first reference 1PPS signal is transmitted in a second period of the i-th second; during the second period of the i-th second, receiving the first reference 1PPS signal from the slave device; determining a second phase compensation information sent to the slave device in a first period of an (i+1)-th second according to a receiving time point when the first reference 1PPS signal is received.

Description

Synchronization correction method, master control device and slave device

The present invention relates to a synchronization mechanism between devices, and in particular to a synchronization correction method, a master device and a slave device.

Please refer to FIG. 1A , which is a schematic diagram of a conventional synchronization mechanism. In Figure 1A, the master (Master) device can be connected to the slave (slave) device through three signal transmission lines, and the master control device can transmit frequency information (such as 10MHz) and phase information (such as a second pulse) through these signal transmission lines. (a pulse per second, 1PPS) signal) and time of day (Time of date, ToD) information to the slave device, so that the slave device can synchronize accordingly.

However, since the method in FIG. 1A needs to use three signal transmission lines, it is not convenient for wiring.

Please refer to FIG. 1B , which is a schematic diagram of another conventional synchronization mechanism. In FIG. 1B , the master control device can be connected to the slave device through a single signal transmission line, and a synchronization signal (such as an embedded PPS (embedded PPS, ePPS) signal) can be transmitted through pulse width modulation (PWM). Sent to slave devices to implement technologies such as Inter-Range Instrumentation Group B (IRIG-B).

Please refer to FIG. 1C , which is a schematic diagram of a conventional PWM. In this embodiment, the bit "0" can be modulated into a pulse wave with a duty cycle of 25% based on the concept of PWM, and the bit "1" can be modulated into a pulse wave based on the concept of PWM. The duty cycle is 75% of the pulse wave. In FIG. 1C , the signal "1011" can be modulated into the pulse sequence shown, for example, according to the above principles, but it is not limited thereto.

It can be seen from FIG. 1B that although it reduces the difficulty of wiring, since the master control device transmits signals to the slave device in one direction, the slave device cannot know the delay error caused by the line length or other factors.

In view of this, the present invention provides a synchronization correction method, a master control device and a slave device, which can be used to solve the above technical problems.

The present invention provides a synchronous correction method suitable for a master control device, comprising: sending a synchronization signal frame to a slave device during the first period of the i-th second, wherein the synchronization signal frame includes a synchronization header, a first A pulse per second (a pulse per second, 1PPS) signal, first time of day information and first phase compensation information, wherein the first phase compensation information is used to request the slave device to correct during the second period of the ith second Send a sending time point of a first reference 1PPS signal; receive the first reference 1PPS signal from the slave device during the second period of the i second; determine the first reference 1PPS signal according to a receiving time point of receiving the first reference 1PPS signal A second phase compensation message sent to the slave device during the first period of i+1 seconds.

The invention provides a master control device, which includes a processing circuit and a compensation estimation circuit. The processing circuit is configured to: send a synchronization signal frame to a slave device during a first period of the i-th second, wherein the synchronization signal frame includes a synchronization header, a first one-second pulse (a pulse per second, 1PPS ) signal, first day time information and first phase compensation information, wherein the first phase compensation information is used to request the slave device to correct a sending time of sending a first reference 1PPS signal during the second period of the i second point. The compensation estimation circuit is coupled to the processing circuit and is configured to: receive the first reference 1PPS signal from the slave device during the second period of the ith second; A second phase compensation message sent to the slave device during the first period of i+1 seconds.

The present invention provides a synchronization correction method suitable for a slave device, comprising: receiving a synchronization signal frame from a master control device during the first period of the i-th second, wherein the synchronization signal frame includes a synchronization header, a first A pulse per second (a pulse per second, 1PPS) signal, first day time information and first phase compensation information; according to the first phase compensation information, a first reference is sent during the second period of the i-th second A sending time point of the 1PPS signal: sending the first reference 1PPS signal to the main control device at the sending time point of the second period of the i-th second.

The invention provides a slave device, including a receiver and a processing circuit. The receiver is configured to: receive a synchronization signal frame from a master control device during a first period of the i-th second, wherein the synchronization signal frame includes a synchronization header, a first one-second pulse (a pulse per second, 1PPS) signal, first day time information and first phase compensation information. The processing circuit is coupled to the receiver and is configured to: modify a sending time point of sending a first reference 1PPS signal during the second period of the i-th second according to the first phase compensation information; The first reference 1PPS signal is sent to the master control device at the sending time point of the second period of seconds.

Please refer to FIG. 2 , which is a schematic diagram of a synchronization system according to an embodiment of the present invention. In FIG. 2 , the synchronization system 200 includes a master device 210 and a slave device 220 , wherein the master device 210 and the slave device 220 can be connected through a bidirectional transmission interface (such as a synchronous serial bus). That is, in some embodiments, in addition to sending information required for synchronization to the slave device 220, the master device 210 can also receive feedback information from the slave device 220, and the master device 210 and the slave device 220 are Synchronous corrections can be made in this two-way communication mechanism.

In one embodiment, the main control device 210 includes a compensation estimation circuit 211 and a processing circuit 212 , wherein the processing circuit 212 is coupled to the compensation estimation circuit 211 . In some embodiments, the main control device 210 may further include a time of day circuit 213 coupled to the processing circuit 212 , but is not limited thereto. In addition, the slave device 220 includes a receiver 221 and a processing circuit 222 coupled to each other.

In an embodiment of the present invention, the master device 210 and the slave device 220 can cooperate to implement the synchronization correction method of the present invention, and the details are described in detail as follows.

Please refer to FIG. 3 , which is a flowchart of a synchronous calibration method according to an embodiment of the present invention. The method of this embodiment can be executed by the master control device 210 and the slave device 220 in FIG. 2 , and the details of each step in FIG. 3 will be described below with the components shown in FIG. 2 .

In the embodiment of the present invention, the principles of the operations performed by the master device 210 and the slave device 220 in the time interval of each second are substantially the same/similar, so the operations performed in the i-th second are taken as an example below description, but not limited to

First, in step S311 , the processing circuit 212 of the master device 210 sends a synchronization signal frame F1 to the slave device 220 during the first period of the i-th second. Accordingly, in step S321 , the receiver 221 of the slave device 220 receives the synchronization signal frame F1 from the master device 210 during the first period of the i-th second.

In an embodiment of the present invention, the i-th second can be at least divided into a first period and a second period, wherein the first period is, for example, a period during which the master device 210 can send a signal to the slave device 220, and the second period is, for example, is the period during which the master device 210 listens to the signal sent by the slave device 220 , but it is not limited thereto.

Please refer to FIG. 4 , which is a schematic diagram of the first period and the second period of the i-th second according to an embodiment of the present invention. As shown in FIG. 4, the synchronization signal frame F1 sent by the main control device 210 in the first period T1 of the i-th second may include, for example, a synchronization header 411, a first 1PPS signal 412, a first day time information 413 and First phase compensation information 414 . In other embodiments, the designer can also adjust the sequence of the first 1PPS signal 412 , the first time of day information 413 and the first phase compensation information 414 in the synchronization signal frame F1 according to requirements, but it is not limited thereto.

In one embodiment, after the processing circuit 212 obtains the contents of the synchronization header 411, the first 1PPS signal 412, the first time of day information 413, and the first phase compensation information 414, the synchronization header can be converted to the synchronization header according to the previously mentioned PWM mechanism. The header 411 , the first 1PPS signal 412 , the first time of day information 413 and the first phase compensation information 414 are encoded into corresponding PWM signals and sent, but not limited thereto.

In one embodiment, the content of the sync header 411 can be designed as a specific bit combination, so that the slave device 220 can determine that the sync signal frame F1 has been received after detecting the specific bit combination, and then send The subsequent first 1PPS signal 412 , the first time of day information 413 and the first phase compensation information 414 are retrieved and subsequent operations are performed. In different embodiments, the length and content of the synchronization header 411 can be determined according to the designer's requirements. For example, assume that the length of the sync header 411 is 7 bits, and its content is, for example, "1011000". In this case, after the slave device 220 detects the specific bit combination of "1011000", the slave device 220 can individually correspond to the first 1PPS signal 412, the first time of day information 413, and the first phase compensation information 414. The first 1PPS signal 412 , the first time of day information 413 and the first phase compensation information 414 are obtained by defaulting the signal length.

For example, assuming that the preset signal lengths of the first 1PPS signal 412, the first time of day information 413, and the first phase compensation information 414 are 1 bit, 80 bits, and 32 bits respectively, then the slave device 220 detects After the synchronization header 411 whose content is "1011000", the slave device 220 can be configured to: determine the next bit of the synchronization header 411 as the first 1PPS signal 412; determine the 80 bits after the first 1PPS signal 412 The bit is determined as the first day time information 413; and the 32 bits after the first day time information 413 are determined as the first phase compensation information 414, but not limited thereto.

In one embodiment, the main control device 210 can determine the first time of day information 413 in the synchronization signal frame F1 through the time of day circuit 213 . In one embodiment, the time of day circuit 213 can determine the first component 413a of the first time of day information 413 after obtaining the external time of day ET corresponding to the i-th second. In one embodiment, the external time of day ET is, for example, epoch time, which can be obtained by the time of day circuit 213 from the Internet or other similar external sources, and used as the second time of the first time of day information 413 A component 413a. In the embodiment of the present invention, under the assumption that the preset signal length of the first time of day information 413 is 80 bits, the first component 413a may occupy the first 48 bits of the first time of day information 413, for example, but It is not limited to this.

In one embodiment, the time-of-day circuit 213 can estimate the second component 413b of the first time-of-day information 413 based on the system clock signal SC1. In an embodiment, the system clock signal SC1 may include a plurality of pulses, and the periods of these pulses may be determined according to the frequency of the system clock signal SC1, for example. For example, assuming that the frequency of the system clock signal SC1 is 125 MHz, the period of these pulse waves is, for example, 8 ns (ie 1/125M). That is, a pulse wave will appear every 8ns.

In this case, in response to the time-of-day circuit 213 detecting one of the pulses of the system clock signal SC1, the time-of-day circuit 214 can increment the first count value. That is, when the frequency of the system clock signal SC1 is 125 MHz, the time of day circuit 214 increments the first count value every 8 ns. In an embodiment, the time of day circuit 214 may use the first count value as the second component 413 b of the first time of day information 413 . In the embodiment of the present invention, when the preset signal length of the first time of day information 413 is assumed to be 80 bits and the first component 413a occupies the first 48 bits of the first time of day information 413, the second component For example, 413b may occupy the last 32 bits of the first day time information 413, but it is not limited thereto.

In short, the first component 413a of the first time of day information 413 can be determined by the time of day circuit 413 based on the external time of day ET (its precision is only seconds), and the second component 413b of the first time of day information 413 (its precision can be ns) can be obtained by counting by the time-of-day circuit 413 itself, but is not limited thereto.

In one embodiment, the first phase compensation information 414 is used to request the slave device 220 to revise the sending time point of sending the first reference IPPS signal RS in the second period T2 of the i-th second.

Roughly speaking, the slave device 220 is configured to send the first reference IPPS signal RS at a preset time point during the second period of every second. In one embodiment, the first reference IPPS signal RS is, for example, 1, and other bits in the second period are, for example, 0. In other words, if the length of the second period is set to be N bits, only one of the N bits is 1, and the other bits are all 0, but it is not limited thereto.

In one embodiment, if there is perfect synchronization between the master device 210 and the slave device 220, the master device 210 will receive a message from the slave device 220 at a preset time point in the second period of every second. The first reference 1PPS signal RS.

However, since the synchronization between the master device 210 and the slave device 220 is generally not perfect, the master device 210 may not receive the first reference IPPS signal from the slave device 220 at the preset time point of the second period. For example, the main control device 210 may receive the first reference 1PPS signal RS before/after the preset time point in the second period of i−1 second. That is, there may be a specific time difference between the receiving time point of the main control device 210 receiving the first reference 1PPS signal RS and the preset time point in the second period of the i-1th second. In this case, the compensation estimation circuit 211 of the main control device 210 can generate corresponding first phase compensation information 414 based on the specific time difference, so that the first The phase compensation information 414 is notified to the slave device 220 .

According to the content of the first phase compensation information 414, the slave device 220 can send the first reference 1PPS signal RS in advance/delay in the second period T2, so as to try to make the master device 210 A first reference 1PPS signal RS is received.

In an embodiment, the compensation estimating circuit 211 can obtain a preset time point in the second period of the i-1th second. In one embodiment, the compensation estimation circuit 211 can obtain the synchronization signal frame of the i-1th second, and add a preset protection time after the end time of the synchronization signal frame as the second period of the i-1th second The preset time point in . In different embodiments, the above-mentioned preset protection time can be determined according to the requirements of the designer.

In one embodiment, assuming that the length of the second period is set to be N bits, the preset protection time can be set to, for example, N/2 bits, but it is not limited thereto. For example, assuming that N is 240, the compensation estimation circuit 211 may add a preset protection time of 120 (ie 240/2) bits after the synchronization signal frame of the i-1th second as the i-th - a preset time point in the second period of 1 second, but not limited thereto. In other words, if there is perfect synchronization between the master device 210 and the slave device 220, only the 120th bit should be 1 (ie, the first reference 1PPS signal RS) during the second period of the i-1th second. , and the other bits are all 0. However, if the synchronization between the master device 210 and the slave device 220 is not perfect, the position where the first reference 1PPS signal RS appears will not be located at the 120th bit in the second period.

Therefore, the compensation estimation circuit 211 can obtain the specific time difference between the receiving time point of receiving the first reference 1PPS signal RS in the second period of i-1 second and the above-mentioned preset time point, and determine the second time point based on the above-mentioned specific time difference. A phase compensation information 414 .

In one embodiment, in response to determining that the receiving time point is ahead of the preset time point by a certain time difference, the compensation estimation circuit 211 may set the first phase compensation information 414 as the second During the period T2, the first reference 1PPS signal RS is sent after a certain time difference. For example, assuming that the position where the first reference 1PPS signal RS appears is the 118th bit in the second period, this means that the first reference 1PPS signal RS is received by the master device 210 2 bits ahead of time (that is, a specific time difference) . Therefore, the compensation estimation circuit 211 can set the first phase compensation information 414 to request the slave device 220 to transmit the first reference 1PPS signal RS with a delay of 2 bits in the second period T2 of the i-th second.

On the other hand, in response to determining that the receiving time point lags behind the preset time point by a certain time difference, the compensation estimation circuit 211 may set the first phase compensation information 414 as the second period T2 for requesting the slave device 220 in the ith second The first reference 1PPS signal RS is sent in advance by a specific time difference. For example, assuming that the position where the first reference 1PPS signal RS appears is the 123th bit of the second period, this means that the first reference 1PPS signal RS is received by the master device 210 after a delay of 3 bits (that is, a specific time difference) arrive. Therefore, the compensation estimation circuit 211 can set the first phase compensation information 414 to request the slave device 220 to send the first reference 1PPS signal RS by 3 bits in advance in the second period T2 of the i-th second.

In one embodiment, assuming that the preset signal length of the first phase compensation information 414 is 32 bits, its most significant bit (most significant bit, MSB), for example, can be used to indicate that the slave device 220 should send earlier/delay The first refers to the 1PPS signal RS, and the remaining 31 bits can be used to represent the above-mentioned specific time difference. For example, when the MSB of the first phase compensation information 414 is 1, the first phase compensation information 414 may be used, for example, to request the slave device 220 to send the first reference 1PPS signal RS after a certain time difference. In addition, when the MSB of the first phase compensation information 414 is 0, the first phase compensation information 414 may be used, for example, to request the slave device 220 to send the first reference 1PPS signal RS ahead of a certain time difference, but it is not limited thereto.

Based on this, in step S322 , the processing circuit 222 of the slave device 220 corrects the sending time point of sending the first reference 1PPS signal RS in the second period T2 of the i-th second according to the first phase compensation information 414 .

In one embodiment, the processing circuit 222 of the slave device 220 obtains a preset time point for sending the first reference 1PPS signal RS in the second period T2 of the ith second. In one embodiment, the processing circuit 222 of the slave device 220 may add the preset guard time GT as the preset time point PT after the end time of the synchronization signal frame F1, but it is not limited thereto.

Afterwards, in response to determining that the first phase compensation information 414 indicates to delay sending the first reference 1PPS signal RS by a specific time difference, the processing circuit 222 may delay the preset time point GT by a specific time difference as the sending time point PT'. For example, when the MSB of the first phase compensation information 414 is 1, the processing circuit 222 may delay the preset time point PT according to a specific time difference indicated by the remaining 31 bits of the first phase compensation information 414 .

On the other hand, in response to determining that the first phase compensation information 414 indicates to send the first reference 1PPS signal RS earlier by the specific time difference, the processor 222 may advance the preset time point GT by the specific time difference as the sending time point PT'. For example, when the MSB of the first phase compensation information 414 is 0, the processing circuit 222 can advance the preset time point PT according to the specific time difference indicated by the remaining 31 bits of the first phase compensation information 414 .

After that, in step S323, the processing circuit 222 of the slave device 220 sends the first reference 1PPS signal RS to the master device 210 at the sending time point PT' of the second period T2 of the ith second. Correspondingly, in step S312 , the compensation estimation circuit 211 of the master device 210 receives the first reference 1PPS signal RS from the slave device 220 in the second period T2 of the ith second.

Afterwards, in step S313 , the compensation estimation circuit 211 determines the second phase compensation information to be sent to the slave device 220 during the first period of the i+1th second according to the receiving time point of the first reference 1PPS signal RS.

In one embodiment, the method of determining the second phase compensation information by the compensation estimation circuit 211 is similar to the method of determining the first phase compensation information 414 . For example, the compensation estimation circuit 211 obtains a preset time point PT in the second period T2 of the i-th second. For example, the compensation estimation circuit 211 may add a preset guard time GT after the end time of the synchronization signal frame F1 as the preset time point PT in the i-th second period T2, but it is not limited thereto. Afterwards, the compensation estimation circuit 211 can obtain a specific time difference between the receiving time point and the preset time point PT, and determine the second phase compensation information based on the specific time difference.

In one embodiment, in response to determining that the receiving time point is ahead of the preset time point PT by a specific time difference, the compensation estimation circuit 211 may set the second phase compensation information as used for requesting the slave device 220 to receive the time point at the i+1th second Sending the first reference 1PPS signal RS is delayed by a specific time difference in the second period of . On the other hand, in response to determining that the receiving time point lags behind the preset time point PT by a specific time difference, the compensation estimation circuit 211 may set the second phase compensation information as used to request the slave device 220 to perform the second phase compensation at the i+1th second. In the second period, the first reference 1PPS signal RS is sent ahead of a specific time difference. For details of the above means, reference may be made to the descriptions of the previous embodiments, and details are not repeated here.

After that, the master device 210 can correspondingly generate the synchronization signal frame F2 corresponding to the i+1th second, and then control the slave device 220 to modify and send the first reference 1PPS signal during the second period of the i+1th second The sending time point of the RS, but not limited thereto.

As can be seen from the above, the embodiments of the present invention allow the master device 210 and the slave device 220 to communicate bidirectionally even though they are only connected through a single signal transmission line (such as a synchronous serial bus). Furthermore, the master device 210 can determine the phase compensation information to be provided to the slave device 220 in the next second according to the status of the first reference 1PPS signal RS fed back by the slave device 220 in the previous second. In this way, the slave device 220 can correct the time point of sending the first reference 1PPS signal according to the phase compensation information, so that the master device 210 and the slave device 220 can achieve a better synchronization effect with each other.

Please refer to FIG. 5 , which is a schematic diagram of the master control device shown in FIG. 2 . In FIG. 5 , besides the compensation estimation circuit 211 , the processing circuit 212 and the time of day circuit 213 , the main control device 210 may further include an oscillator 511 , a phase-locked loop 512 and a bidirectional transmission controller 513 .

In one embodiment, the oscillator 511 is, for example, an Oven Controlled Crystal Oscillator (OCXO) or other precise and controllable clock signal generators, and can be used to provide the local clock signal LC1 .

In one embodiment, the phase locked loop 512 is coupled to the oscillator 511 , the compensation estimation circuit 211 , the processing circuit 212 and the time of day circuit 213 , and can be implemented as a digital phase lock loop (DPLL). In one embodiment, the phase-locked loop 512 can receive the external clock signal EC, the external 1PPS signal EP and the local clock signal LC1 from the oscillator 511 , and can generate the system clock signal SC1 and the first 1PPS signal 412 accordingly.

In one embodiment, the time-of-day circuit 213 can obtain the system clock signal SC1 and the first 1PPS signal 412 from the phase-locked loop 512 , and determine the second component 413b of the time-of-day information 413 according to the previous teaching.

In one embodiment, the compensation estimation circuit 211 can determine the first phase compensation information 414 according to the first reference 1PPS signal RS received during the second period of the i-1th second, and the first phase compensation information 414 A pre-processing circuit 212 is provided.

In one embodiment, the processing circuit 212 can obtain the system clock signal SC1 and the time of day information 413 from the time-of-day circuit 213, the first 1PPS signal 412 from the phase-locked loop 512, and the first 1PPS signal from the compensation estimation circuit 211. After the phase compensation information 414, the above information is encoded into a synchronous signal frame F1 through a mechanism such as PWM.

In one embodiment, the bidirectional transmission controller 513 can be connected to the slave device 220 , for example, and can be used to control the bidirectional transmission between the master device 210 and the slave device 220 . For example, in the first period T1 of the i-th second, the bidirectional transmission controller 513 may switch the synchronous serial bus between the master device 210 and the slave device 220 to a low impedance state (commonly known as low- Z state), so that the processing circuit 212 sends the generated sync signal frame F1 to the slave device 220 .

In addition, during the second period T2 of the i-th second, the bidirectional transmission controller 513 can switch the synchronous serial bus between the master device 210 and the slave device 220 to a high impedance state (commonly known as a high-Z state) ), so that the compensation estimation circuit 211 can listen to the first reference 1PPS signal RS from the slave device 220 . Afterwards, the compensation estimation circuit 211 can generate second phase compensation information according to the first reference 1PPS signal RS received in the second period T2, so that the processing circuit 212 can generate a synchronization signal corresponding to the i+1th second frame. Relevant details can refer to the descriptions in the previous embodiments, and will not be repeated here.

Please refer to FIG. 6 , which is a schematic diagram of the slave device shown in FIG. 2 . In FIG. 6 , the slave device 220 includes an oscillator 611 and a bidirectional transmission controller 615 in addition to the receiver 221 and the processing circuit 222 .

In one embodiment, the two-way transmission controller 615 can be used to receive the corresponding synchronization signal frame from the main control device 210 during the first period of each second, and transfer the first reference 1PPS frame provided by the processing circuit 222 to the second period during the second period. The signal RS is sent to the master device 210 .

In one embodiment, the receiver 211 may include a phase locked loop 612 , a decoder 613 and a time of day circuit 614 . In one embodiment, during the first period T1 of the i-th second, the decoder 613 can decode the synchronization signal frame F1 after obtaining the synchronization signal frame F1 from the master device 210 from the two-way transmission controller 615 to obtain the second A 1PPS signal 412, time of day information 413, first phase compensation information 414 and a signal frequency FS corresponding to the synchronization signal frame F1.

In one embodiment, the decoder 613 can estimate the signal frequency FS of the sync signal frame F1 based on the time difference between bits in the sync signal frame F1. For example, assuming that the time difference between the bits of the sync signal frame F1 is 8 ns, the decoder 613 can estimate that the signal frequency FS of the sync signal frame F1 is 125 MHz (ie 1/8 ns), but it is not limited thereto.

In one embodiment, the oscillator 611 is, for example, an OCXO or other precisely controllable clock signal generators, and can be used to provide the local clock signal LC2.

In one embodiment, the phase-locked loop 612 is coupled to the oscillator 611 and the decoder 613, and can generate the system clock signals SC1 and The first reference 1PPS signal RS.

In one embodiment, the time-of-day circuit 614 is coupled to the decoder 613 and the phase-locked loop 612, and can receive the time-of-day information 413 and the first phase compensation information 414 from the decoder 613, and receive the system clock from the phase-locked loop 612 The signal SC1 and the first reference 1PPS signal RS.

In one embodiment, the time of day circuit 614 can use the first component 413a of the time of day information 413 as the first time component of the system time of day ST (with an accuracy of seconds), and then based on the system clock signal SC1 and the time of day information 413 The second component 413b estimates a second time component (with ns accuracy) of the system time of day ST.

For example, as mentioned above, the second component 413b is the first count value obtained by counting by the time-of-day circuit 213, and its value (indicated by K) represents how many 8ns the time-of-day circuit 213 has counted previously. Therefore, the time of day circuit 614 can correspondingly obtain the second time component of the system time of day ST by counting K 8 ns. Afterwards, the time-of-day circuit 614 may combine (eg add) the first time component and the second time component to obtain the system time of day ST, but it is not limited thereto.

In one embodiment, the time-of-day circuit 614 can modify the sending time point of the first reference 1PPS signal RS based on the first phase compensation information 414 . For example, when the MSB of the first phase compensation information 414 is 1, the time-of-day circuit 614 can acquire the preset time point of sending the first reference 1PPS signal RS in the second period T2 and the first phase compensation information 414 After the specific time difference indicated by the remaining 31 bits, the preset time point is delayed by the specific time difference to modify the sending time point of the first reference 1PPS signal RS. In addition, when the MSB of the first phase compensation information 414 is 0, the time-of-day circuit 614 can obtain the preset time point of sending the first reference 1PPS signal RS in the second period T2 and the rest of the first phase compensation information 414 After the specific time difference indicated by 31 bits, the preset time point is advanced by the specific time difference to modify the sending time point of the first reference 1PPS signal RS.

Afterwards, the processing circuit 222 can send the first reference 1PPS signal to the main control device 210 according to the corrected sending time point of the first reference 1PPS signal RS provided by the time-of-day circuit 614 .

Correspondingly, the main control device 210 can then adaptively adjust the value of the second phase compensation information in the synchronization signal frame corresponding to the (i+1)th second according to the situation of receiving the first reference 1PPS signal RS in the second period T2 content, the details of which will not be repeated here.

In one embodiment, after the slave device 220 acquires the first 1PPS signal 412, the signal frequency FS, and the system time ST, the slave device 220 may perform a synchronization operation based on it to try to synchronize with the master device 210, but it is not limited thereto. .

In some embodiments, the i-th second may further include a third period T3 shown in FIG. During the first period of frame F2, neither the master device 210 nor the slave device 220 may transmit/receive in the third period T3, but it is not limited thereto. In addition, in one embodiment, the master device 210 can only transmit the frequency signal (for example, 50% of the duty cycle) to the slave device 220 during the third period T3, so that the slave device 220 can maintain the relationship with the master device 210. frequency synchronization.

In addition, in some embodiments, although the master device 210 does not send a signal to the slave device 220 during the second period T2, the phase-locked loop 612 of the slave device 220 can enter a holdover mode, so that during the second period T2 Synchronization with the master device 210 is maintained in T2.

To sum up, the embodiments of the present invention allow the master device and the slave device to communicate bidirectionally when only connected through a single synchronous serial bus. For example, the master device can determine the phase compensation information to be provided to the slave device in the next second according to the status of the first reference 1PPS signal RS fed back by the slave device in the previous second. In this way, the slave device can correct the time point of sending the first reference 1PPS signal according to the phase compensation information, so that the master device and the slave device can achieve a better synchronization effect with each other.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

200: synchronous system 210: master control device 211: compensation estimation circuit 212: processing circuit 213: day time circuit 220: slave device 221: Receiver 222: Processing circuit 411: Synchronization header 412: The first 1PPS signal 413: First day time information 413a: first component 413b: Second component 414: First phase compensation information 511: Oscillator 512: PLL 513: Two-way transmission controller 611: Oscillator 612: PLL 613: decoder 614: day time circuit 615: Two-way transmission controller F1: Sync signal box RS: first reference 1PPS signal SC1: System clock signal ET: External Day Time T1: first period T2: the second period T3: the third period GT: preset protection time PT: preset time point EC: external clock signal EP: external 1PPS signal LC1: local clock signal ST: system day time FS: signal frequency S311~S313, S321~S323: steps

FIG. 1A is a schematic diagram of a conventional synchronization mechanism. FIG. 1B is a schematic diagram of another conventional synchronization mechanism. FIG. 1C is a schematic diagram of a conventional PWM. FIG. 2 is a schematic diagram of a synchronization system according to an embodiment of the present invention. FIG. 3 is a flowchart of a synchronous calibration method according to an embodiment of the invention. FIG. 4 is a schematic diagram of a first period and a second period of the i-th second according to an embodiment of the present invention. FIG. 5 is a schematic diagram of the main control device shown in FIG. 2 . FIG. 6 is a schematic diagram of the slave device shown in FIG. 2 .

210: master control device

220: slave device

F1: Sync signal box

RS: first reference 1PPS signal

S311~S313, S321~S323: steps

Claims (22)

A synchronization correction method, suitable for a master control device, comprising: During the first period of the i-th second, a synchronization signal frame is sent to a slave device, wherein the synchronization signal frame includes a synchronization header, a first pulse per second (a pulse per second, 1PPS) signal, a first time of day information and first phase compensation information, wherein the first phase compensation information is used to request the slave device to correct a transmission time point for transmitting a first reference 1PPS signal during the second period of the i second; receiving the first reference 1PPS signal from the slave device during the second period of the ith second; A second phase compensation information sent to the slave device during the first period of the (i+1)th second is determined according to a receiving time point of receiving the first reference 1PPS signal. The method as described in claim 1, wherein the determination of the second phase compensation information sent to the slave device during the first period of the i+1th second is determined according to the receiving time point of receiving the reference 1PPS signal Steps include: obtain a predetermined time point in the second period of the i second; obtaining a specific time difference between the receiving time point and the preset time point; The second phase compensation information is determined based on the specific time difference. The method as claimed in claim 2, wherein the step of determining the second phase compensation information based on the specific time difference comprises: In response to determining that the receiving time point is ahead of the preset time point by the specified time difference, setting the second phase compensation information to request the slave device to delay the specified time point in the second period of the i+1th second Sending the first reference 1PPS signal with a time difference; In response to determining that the receiving time point lags behind the preset time point by the specified time difference, setting the second phase compensation information to request the slave device to advance the The first reference 1PPS signal is sent with a specific time difference. The method as claimed in claim 2, wherein the step of obtaining the preset time point in the second period of the i-th second comprises: A preset guard time is added after the end time of the synchronization signal frame as the preset time point in the second period of the ith second. The method as described in Claim 1, further comprising: Obtain an external time of day corresponding to the i-th second, and determine a first component of the first time of day information accordingly; A second component of the first time of day information is estimated based on a system clock signal. The method of claim 5, wherein the external time of day includes an epoch time, and the method includes using the epoch time as the first component of the first time of day information. The method of claim 5, wherein the system clock signal comprises a plurality of pulses, and the step of estimating the second component of the first time of day information based on the system clock signal comprises: In response to detecting one of the pulses of the system clock signal, increment a first count value and use the first count value as the second component of the first time of day information. The method of claim 1, wherein the synchronization signal sequentially includes the synchronization header, the first 1PPS signal, the first time of day information, and the first phase compensation information. A master control device, comprising: A processing circuit configured to: During the first period of the i-th second, a synchronization signal frame is sent to a slave device, wherein the synchronization signal frame includes a synchronization header, a first pulse per second (a pulse per second, 1PPS) signal, a first time of day information and first phase compensation information, wherein the first phase compensation information is used to request the slave device to correct a transmission time point for transmitting a first reference 1PPS signal during the second period of the ith second; a compensation estimation circuit coupled to the processing circuit and configured to: receiving the first reference 1PPS signal from the slave device during the second period of the ith second; A second phase compensation information sent to the slave device during the first period of the (i+1)th second is determined according to a receiving time point of receiving the first reference 1PPS signal. The master control device as claimed in claim 9, wherein the compensation estimation circuit is configured to: obtain a predetermined time point in the second period of the i second; obtaining a specific time difference between the receiving time point and the preset time point; The second phase compensation information is determined based on the specific time difference. The master control device as claimed in claim 10, wherein the compensation estimation circuit is configured to: In response to determining that the receiving time point is ahead of the preset time point by the specified time difference, setting the second phase compensation information to request the slave device to delay the specified time point in the second period of the i+1th second Sending the first reference 1PPS signal with a time difference; In response to determining that the receiving time point lags behind the preset time point by the specified time difference, setting the second phase compensation information to request the slave device to advance the The first reference 1PPS signal is sent with a specific time difference. The master control device as claimed in claim 10, wherein the compensation estimation circuit is configured to: A preset guard time is added after the end time of the synchronization signal frame as the preset time point in the second period of the ith second. The main control device as described in claim 9, further comprising a time of day circuit coupled to the processing circuit, wherein the time of day circuit is configured to: Obtain an external time of day corresponding to the i-th second, and determine a first component of the first time of day information accordingly; A second component of the first time of day information is estimated based on a system clock signal. The master device of claim 13, wherein the external time of day includes an epoch time, and the time of day circuit is configured to use the epoch time as the first component of the first time of day information. The master control device as claimed in claim 13, wherein the system clock signal comprises a plurality of pulses, and the time of day circuit is configured to: In response to detecting one of the pulses of the system clock signal, increment a first count value and use the first count value as the second component of the first time of day information. The master control device as claimed in claim 9, wherein the synchronization signal sequentially includes the synchronization header, the first 1PPS signal, the first time of day information and the first phase compensation information. A synchronization correction method suitable for a slave device, comprising: During the first period of the i-th second, a synchronization signal frame is received from a master device, wherein the synchronization signal frame includes a synchronization header, a first pulse per second (a pulse per second, 1PPS) signal, a second Time of day information and first phase compensation information; Correcting a sending time point of sending a first reference 1PPS signal during the second period of the i-th second according to the first phase compensation information; Sending the first reference 1PPS signal to the master control device at the sending time point of the second period of the i-th second. The method as claimed in claim 17, wherein the step of correcting the sending time point of sending the first reference 1PPS signal in the second period of the ith second according to the first phase compensation information comprises: obtaining a predetermined time point at which the first reference 1PPS signal is transmitted during the second period of the ith second; Responding to determining that the first phase compensation information indicates to delay sending the first reference 1PPS signal by a specific time difference, delaying the preset time point by the specific time difference as the sending time point; In response to determining that the first phase compensation information indicates that the first reference 1PPS signal is sent ahead of the specific time difference, the predetermined time point is advanced by the specific time difference as the sending time point. The method as claimed in claim 18, wherein the step of obtaining the preset time point for sending the first reference 1PPS signal during the second period of the i second comprises: A preset guard time is added after the end time of the synchronization signal frame as the preset time point. A slave device, comprising: a receiver configured to: During the first period of the i-th second, a synchronization signal frame is received from a master device, wherein the synchronization signal frame includes a synchronization header, a first pulse per second (a pulse per second, 1PPS) signal, a second Time of day information and first phase compensation information; a processing circuit coupled to the receiver and configured to: Correcting a sending time point of sending a first reference 1PPS signal during the second period of the i-th second according to the first phase compensation information; Sending the first reference 1PPS signal to the master control device at the sending time point of the second period of the i-th second. The slave device of claim 20, wherein the processing circuit is configured to: obtaining a predetermined time point at which the first reference 1PPS signal is transmitted during the second period of the ith second; Responding to determining that the first phase compensation information indicates to delay sending the first reference 1PPS signal by a specific time difference, delaying the preset time point by the specific time difference as the sending time point; In response to determining that the first phase compensation information indicates that the first reference 1PPS signal is sent ahead of the specific time difference, the predetermined time point is advanced by the specific time difference as the sending time point. The slave device of claim 21, wherein the processing circuit is configured to: A preset guard time is added after the end time of the synchronization signal frame as the preset time point.

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