JP3191883B2 - Active matrix substrate inspection equipment for liquid crystal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, in which each pixel is sequentially selected by using a thin film transistor formed for selectively displaying the pixel, and an electric charge corresponding to a video signal is stored in an auxiliary capacitor. The present invention relates to an inspection apparatus for inspecting a matrix substrate of a thin film transistor before liquid crystal is sealed therein.

[0002]

2. Description of the Related Art FIG. 3 shows an active matrix substrate for liquid crystal. A plurality of gate lines 12 ₁ to 12 _m were parallel to each other on a transparent substrate 11 such as glass is provided. Perpendicular to the gate lines 12 ₁ to 12 _m are a plurality of data lines 13 ₁ to 13 _n are provided in parallel. At each intersection of these gate lines and data lines, thin film transistors 14 ₁₁ to 14 _mn are respectively provided, these thin-film transistor has a gate connected to the immediate vicinity of the gate line, a source connected to a data line, a drain in FIG. Although not shown, it is connected to the pixel electrode. Usually are connected to one respective end of the auxiliary capacitor 15 ₁₁ to 15 _mn for capacity is small between the common electrode and the pixel electrode by the liquid crystal itself corresponds drain of the thin film transistors 14 ₁₁ to 14 _mn, these auxiliary capacitance 15 ₁₁ to The other _ends of the 15 _mn are connected to the auxiliary capacitance common ground terminal 16. That is, when the liquid crystal display is actually manufactured, liquid crystal capacitors 17 based on the liquid crystal between each pixel electrode and the common electrode are formed in parallel with each auxiliary capacitor as shown by a dotted line.

[0003] are connected sequentially to each shift stage of the gate lines 12 ₁ to 12 _m row selection shift register 18. The data lines 13 _{1 to} 13 _n are connected to the video input terminal 21 through column selection switches 19 _{1 to} 19 _n , respectively. The gates of the respective thin film transistors as the column selection switches 19 _{1 to} 19 _n are sequentially connected to corresponding ones of the n shift stages of the column selection shift register 22. These thin film transistors 14 _{11 to} 14 _mn ,
Switch 19 ₁ to 19 _n are those active region are composed of a polycrystalline silicon, respectively. The row selection shift register 18 and the column selection shift register 22 are also formed of similar thin film transistors.

The terminal 23 of the row selection shift register 18
A direct start signal is given, and a vertical operation clock is
Is applied to terminal 24, row selection shift every horizontal cycle
The register 18 sequentially outputs a high level to the shift stage,
That is, the gate line 12₁To 12 _mHigh level
Power. Similarly, the terminal 25 of the column selection shift register 22
A horizontal start signal is supplied, and a horizontal operation clock is
Is given, the column selection shift register
Become sequentially high, and the column selection switch 19
₁To 19_nAre sequentially given a high level. Obedience
For example, the gate line 12₁Row selection between high levels
Selection switch 19₁When the gate of the
Transistor 14₁₁Turns on and the video signal at terminal 21
Itch 19₁Through the thin film transistor 14₁₁Through
15 storage capacity₁₁Power to the video input level.
The load is charged. This gate line 12₁While high level
Column selection switch 19₁To 19_nAre turned on sequentially
The thin film transistor 14₁₁To 14_1nAre turned on sequentially
Is the video signal at that time from the video input terminal 21
Auxiliary capacity 15 corresponding to level₁₁To 15_1nTo
Is charged. Then the gate line 12_TwoIs high
Level, and scanning is performed for the pixels on that gate line.
Is In the same manner, the entire thin film transistor mat
Rix, that is, scanning for each pixel electrode is performed
Will be.

[0005] Such an active matrix for liquid crystal.
As a test on the substrate, that is, enclose the liquid crystal
In the previous test, the gate line 12₁To 12_mAnd data lines
13 ₁Thirteen to thirteen_nAn auxiliary pad is set on the substrate 11 for
To determine whether they are in a short-circuit or open state.
Only the inspection is performed.
Check whether the cable is connected to the
Inspect whether the membrane transistor operates correctly, and furthermore
Checking whether the auxiliary capacity is normal is done conventionally
I couldn't do that. For this reason, after filling the liquid crystal, the liquid crystal display
The display operation is performed as a
Check that the display is correct, that is, check for pixel defects.
An inspection was being conducted. Therefore the completed liquid crystal display
If this is bad because it is inspected with a container, it will be a great waste
There was a problem.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of inspecting a liquid crystal active matrix substrate for good and bad for each pixel such as a thin film transistor and an auxiliary capacitor before the liquid crystal is sealed. The present invention provides an active matrix substrate inspection apparatus for use.

[0007]

According to the present invention, each pixel of the active matrix substrate for the liquid crystal under test is sequentially selected by the scanning means, and the inspection signal generating section supplies the pixel selection period in synchronization with the selection of each pixel. A test signal shorter than the selection period, which is later than the start, is generated for each pixel and supplied to the auxiliary capacitance common ground terminal or the video input terminal. In addition, the output from the video input terminal or the auxiliary capacitor common ground terminal is taken into the processing section in synchronization with the pixel selection, and the output level of each pixel of the liquid crystal active matrix substrate under test is determined based on the relative level of each pixel. , A defect is determined. A switch is provided between a terminal from which the output of the video input terminal or the auxiliary capacitance common ground terminal is taken out and a common potential point terminal of the device, and the switch is controlled to be turned on for a short time at the beginning of each pixel selection period. You.

[0008]

An embodiment of the present invention will be described with reference to FIG. In FIG. 1A, an active matrix substrate 31 for a liquid crystal under test has the same configuration as that shown in FIG. 3, but in this figure, one column selection switch 19 _1.
And the thin film transistors 14 _{11 to} 14 _m1 connected thereto.
, And the rest is omitted. Scan timing generator 32
3, corresponding signals are supplied to the vertical start signal terminal 23, the vertical operation clock terminal 24, the horizontal start signal terminal 25, and the horizontal operation clock terminal 26 in FIG. Although not shown in the figure, the row selection shift register 18 and column selection register 22 of the liquid crystal active matrix substrate 31 to be tested are operated by these signals to turn on the thin film transistors 14 _{11 to} 14 _mn sequentially as in FIG.
That is, each pixel is sequentially scanned. When a certain gate line is selected, that is, when the gate line is at a high level, a column selection switch is sequentially turned on for each pixel selection period T as shown in FIG. 1B and connected to the gate line. The thin film transistors are sequentially turned on during the pixel selection period T.

FIG. 1B shows the signal from the test signal generator 33.
From the beginning of each pixel selection period T₁Standing up just late
A rising square wave test signal is output. This test signal is
Fall before the end of the pixel selection cycle of
△ t from the falling edge of the signal to the end of the pixel selection cycle
_TwoIs a period when there is no signal. Such a pixel selection cycle
Shorter test signal in this example is the auxiliary capacitance common ground
It is supplied to terminal 16. Therefore, in this pixel selection cycle,
Thin film transistor 14 turned on_ij(I = 1,
2, ... m, j = 1,2, ... n)
Selection switch 19 _jThrough the auxiliary capacity 15_ijCharge for
Is supplied to the video input terminal 21 as its output.
Thus, for example, an output having a waveform as shown in FIG.
You.

The output appearing at the video input terminal 21 is converted from a high-impedance input to a low-impedance output by an impedance conversion circuit 34 and supplied to a sample-and-hold circuit 35, where the sample is held near the end of each test signal, and its output is output. Is amplified by the amplifier 36 and then A
The signal is converted into a digital signal by the / D converter 37 and supplied to the image processing unit 38. 1B in the A / D converter 37.
As shown in (b), after the sample and hold in the sample and hold circuit 35 and by the sampling pulse for the period near the end of the test signal, the sampled value is converted into a digital value. The image processing unit 38 relatively compares the relative level of the input data between adjacent pixels, that is, the level of the signal output from the terminal 21, and checks the presence or absence of a defect from these levels.

That is, for example, when the auxiliary capacitance 15 _ij is short-circuited, a large output is generated at the video input terminal 21 when the thin film transistor 14 _ij to which the auxiliary capacitance 15 _ij is connected is selected and turned on. FIG. 2A shows the arrangement of each pixel in the horizontal direction, that is, the thin film transistor 1 along the gate line.
4 shows an arrangement of the _ij, shows the arrangement of the gate lines 12 _i in the depth direction, shows an example of a state of displaying the output level corresponding to the pixel arrangement in each their respective gate lines on the screen.
The low level portion on both sides of FIG. 2A indicates a state where all of the thin film transistors are turned off and no output is generated, holds a substantially constant level, and is a peripheral invalid screen portion. In other words, a portion that is an effective pixel and is in a state of substantially the same level higher than the invalid screen portion indicates that each pixel is good, but the peak 39 occurs halfway along that position. This indicates that the storage capacitor of the corresponding pixel is short-circuited and a large peak has occurred. That is, for example, when a square wave of 6 V is input as a peak of the square wave of the test signal, a peak of 151 mV is generated as a peak 39 due to an amplitude difference from other pixels. When 1 V DC was applied to the terminal 16, an output of 49 mV was generated at the terminal 21 at the data line corresponding to the position where the peak 39 occurred. Is reduced, and it is estimated that short-circuit failure of the auxiliary capacitance occurs.

FIG. 2B shows an example of a display measured in the same manner.
The occurrence of a large peak near the right end indicates a line defect, that is, a state where a data line corresponding to this position is defective and a peak always occurs when this data line is selected. . On the right side of the line defect indicated by the peak 41, there is a low-level portion 42 whose level has dropped near the middle of the gate line row. That is, the 6
-4 mV is applied to the terminal 21 with respect to the application of the peak square wave of V.
Occurs, and an amplitude difference occurs with the other pixels, which is presumed to be based on the poor connection of the thin film transistor _{14ij in} that portion. In this way, the image processing unit 38 performs image processing, and displays the inspection result as an image as shown in FIGS. 2A and 2B. By viewing the inspection result, the presence or absence of a defect is displayed for each pixel.

By the way, the auxiliary capacitance 15_ijShort circuit, etc.
If an overcurrent flows when a test signal is applied to the
Terminal 21 and column selection switch 19₁To 19_nEach connection with
Stray capacitance to the common potential point including these
Raw capacity) 44, and charging for this is large.
And each data line 13_jAlso at the common potential point
In contrast, stray capacitance (parasitic capacitance) 45₁To 45_n
Exists, but an overcurrent flows through the defective data line
And the stray capacitance 45 for the data line_jToo
Charging is done. The stray capacitance 44 is overcharged
And one thin film transistor 14_ijSelect and turn on,
In the next pixel selection cycle, the adjacent thin film transistor 14
_{ij + 1}When the switch is turned on, the charge of the stray capacitance 44 remains.
Is output to the terminal 21 and the thin film transistor selected at that time is output.
Transistor 14_{ij + 1}Even if the pixel containing
Is erroneously detected as a defect. Similarly stray capacitance
45 _jIs also overcharged, and the overcharge
Later, after one horizontal cycle, the data line and the next gate line
Thin film transistor 14 connected to_{i + 1j}Was turned on
Sometimes stray capacitance 45_jCharge remains on the thin film transformer.
Vista 14_{i + 1j}Even if the pixel containing
There is a risk that.

From such a point, the switch 46 is connected between the terminal 21 and the common potential point of the device as shown in FIG. 1A. The switch 46 has a low on-resistance and operates at high speed.
Moreover, it has a small terminal capacitance and is constituted by, for example, an FET switch. As shown in FIG. 1B, the switch 46 is turned on from the scanning timing generator 32 in the first section and the last section of each pixel selection cycle in this example. Therefore, the switch 46 is turned on at the beginning of the pixel selection cycle, and the charge stored in the floating capacitance 44 is immediately discharged through the switch 46. When, for example, the column selection switch 19 ₁ is turned on at the beginning of the pixel selection cycle, the charges stored in the floating capacitance 45 ₁ of the data line 13 ₁ connected thereto are switched to the switches 19 ₁ and 46.
Immediately discharged through

As described above, the stray capacitances 44 and 45_jIs discharged
Since the inspection signal is supplied to the terminal 16 after the
Surveys can be conducted. Also, in this example, the inspection signal
Between the falling edge and the end of the pixel selection cycle.
Switch 46 is turned on even if the
Stray capacitance 44 or stray capacitance 45 due to failure _j
Switch 46 and the column selection switch
Chi 19_jEach discharge through the
Even if the discharge failed, the next pixel selection cycle (or
Switch at the beginning of the pixel selection cycle after one horizontal cycle)
By turning on 46, the stray capacitances 44 and 45_jRemains of
Is discharged, and stray capacitances 44 and 45 are discharged._jCharge of
Can be completely zero and the correct check
I can.

In the above description, the switch 46 may be turned on only at the beginning of the pixel selection period. The inspection signal may be supplied to the video signal input terminal 21 to take out the output from the auxiliary capacitance common ground terminal 16. Further, in the above description, the scanning means is constituted by the scanning timing generating section 32, the row selection shift register 18 in the active matrix substrate 31 for liquid crystal under test, the column selection shift register 22, and the like. When the register is not provided, these may be provided outside to scan the pixels of the active matrix substrate. Further, the present invention can be applied not only to a thin film transistor using an active region using polycrystalline silicon but also to a test using a thin film transistor using an amorphous silicon to form an active matrix substrate.

[0017]

As described above, according to the present invention, each pixel of the active matrix formed on the substrate before enclosing the liquid crystal is sequentially selected and scanned, and the inspection signal is generated in synchronization with the scanning. At least at the beginning of each pixel selection period, a correct test can be performed at a high speed in order to remove a stray capacitance of a portion from which each test signal is extracted and a stray capacitance of a data line. That is, a defect in the auxiliary capacitance, a defect in the thin film transistor, and the like can be correctly detected. Therefore, it is possible to detect and discard a defective product at a lower cost than in a case where the liquid crystal display device is inspected after being configured as a liquid crystal display and becomes defective and discarded, thereby reducing waste.

The power supply voltage is applied to the impedance conversion circuit 34 before the output is generated from the terminal 21 before the test, and the output of the high-resistance resistance element 47 connected in parallel with the switch 46 is output. Or a negative level, and it takes time to start the test and reach a steady state. Therefore, it is preferable to set the input side of the impedance conversion circuit 34 to the common potential point potential through the high resistance element 47.

[Brief description of the drawings]

FIG. 1A is a block diagram showing an embodiment of an inspection apparatus according to the present invention, and FIG. 1B is a time chart showing operation waveforms of each section.

FIG. 2 is a diagram showing a display example of an image processing result in an image processing unit 38 in the embodiment of FIG. 1A.

FIG. 3 is a connection diagram showing an example of a liquid crystal active matrix substrate.

Claims (1)

(57) [Claims] 1. A scanning means for sequentially selecting each pixel of an active matrix substrate for a liquid crystal under test, and a test signal, which is delayed from the beginning of the pixel selection cycle and shorter than the pixel selection cycle in synchronization with the pixel selection, is supplied to each pixel. A test signal generator which is generated for each selection cycle and is applied to one of the auxiliary capacitance common ground terminal and the video input terminal of the active matrix substrate for liquid crystal under test; and the test signal is input from the auxiliary capacitance common ground terminal.
Output from the video input terminal when the
A process of taking out an output from the auxiliary capacitance common ground terminal when the test signal is input from the terminal in synchronization with the pixel selection, and processing the active matrix substrate for a liquid crystal under test so as to determine whether it is good or bad. A switch provided between the video input terminal or the auxiliary capacitance common ground terminal from which the output is taken out and a common potential point of the device, and turned on at the beginning of each pixel selection period. Active matrix substrate inspection equipment for liquid crystal.