JP3191252B2 - Quadrature detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature detection circuit used for a demodulator in digital radio communication.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional digital quadrature detection circuit. The binary-quantized received modulation signal A is input to exclusive-OR circuits 1 and 2 and multiplied by 1 bit with the quadrature detection signals B1 and B2, respectively, to become signals C1 and C2. The signals C1 and C2 are latched by the high-speed clock T in the latch circuits 10 and 11, and become signals D1 and D2.
1 and D2 are input to the accumulation circuits 40 and 41. The cumulative addition circuits 40 and 41 perform cumulative addition of the positive (“1”) number of the signals D1 and D2 in a certain period, and output the quadrature detection signals H1 and H from which output harmonic components have been removed.
2 is output. In the correspondence with the analog quadrature detection circuit, the exclusive OR circuit corresponds to the mixer, and the latch circuit and the accumulation circuit correspond to the low-pass filter.

Incidentally, in order to prevent deterioration in the quadrature detection section, the frequency of the high-speed clock T needs to be about 100 times or more the frequency of the modulation signal clock.

[0004]

Since the conventional digital quadrature detection circuit operates at a very high operation speed (about 100 times the modulation signal clock rate), it is very difficult to realize a demodulator by LSI or the like. Requires a lot of power consumption. Therefore, in a receiver for a mobile device or the like, which has severe restrictions on power consumption, low power consumption of the quadrature detection circuit is an issue.

An object of the present invention is to provide a digital quadrature detection circuit that operates with a low-speed circuit.

[0006]

The feature of the present invention to achieve the above object is to provide an exclusive OR (E) for multiplying a quadrature detection signal by one bit with a binary-quantized reception phase modulation signal.
x-OR) circuit, a latch circuit that latches the output of the exclusive OR circuit with a high-speed clock, a serial-parallel conversion circuit that converts the latch circuit output into M parallel sequences, and outputs the serial-parallel conversion. The quadrature detection circuit includes a counting circuit that counts the number of positive (“1”) in the circuit output and a cumulative addition circuit that performs cumulative addition for a certain period and outputs a cumulative added value.

[0007]

The multiplication output is M
The operation speed of the accumulative addition circuit having a large ratio of the circuit scale is reduced to a fraction (1 / M) of the conventional speed because the data is converted into the parallel series and processed. Therefore, the power consumption of the entire quadrature detection circuit can be reduced.

[0008]

FIG. 1 is a block diagram showing an embodiment of the present invention. The binary-quantized received modulation signal A is input to exclusive-OR circuits 1 and 2 and multiplied by 1 bit with the quadrature detection signals B1 and B2, respectively, to become signals C1 and C2. The signal C
1 and C2 are latched by the high-speed clock T in the latch circuits 10 and 11, and become signals D1 and D2. The signals D1,
D2 is input to the serial / parallel conversion circuits 20 and 21 and becomes M-bit parallel signals E1 and E2. The signal E
1 and E2 are input to counting circuits 30 and 31, and the parallel signals E1 and E1 are output at an operation speed of 1 / M of the high-speed clock T.
The count value of the positive ("1") number in 2 is output as signals F1 and F2. The signals F1 and F2 are equal to M of the high-speed clock T.
Input to the cumulative addition circuits 40 and 41 operating at 1 /
The cumulative addition result is output as the quadrature detection signals G1 and G2 from which the harmonic components have been removed.

[0009]

In the digital quadrature detection circuit, an accumulative adding circuit having a large circuit scale is reduced to a fraction of the conventional speed.
Since the operation is performed at (1 / M), the power consumption of the quadrature detection circuit is greatly reduced. A practical numerical value of M is, for example, 5 to 6.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a conventional example.

[Explanation of symbols]

 1, 2 Exclusive OR (Ex-OR) circuit 10, 11 Latch circuit 20, 21 Serial / parallel conversion circuit (1 → M sequence) 30, 31 Count circuit 40, 41 Cumulative addition circuit 50 M frequency dividing circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03D 3/00 H03D 3/06 H04L 27/233

Claims (1)

(57) [Claims] 1. A pair of exclusive OR circuits (1) for multiplying a binary-quantized phase modulation signal (A) by one bit each of quadrature detection signals 0 ° and 90 ° (B1, B2). ,
2); a latch circuit (10, 11) for latching the output (C1, C2) of the circuit with a high-speed clock (T); and M outputs (D1, D2) of the circuit (M is 2 or more). A serial-to-parallel conversion circuit (20, 21) for outputting a parallel series of integers), a counting circuit (30, 31) for counting the number of positive outputs among the M outputs of the circuit, A cumulative addition circuit (4) that cumulatively adds outputs over a certain period and outputs the cumulative addition value as a quadrature detection output.
0, 41).