CN113872604A - Sigma-delta modulator capable of reducing fractional spurs and high-frequency quantization noise - Google Patents
Sigma-delta modulator capable of reducing fractional spurs and high-frequency quantization noise Download PDFInfo
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Abstract
The invention discloses a sigma-delta modulator capable of reducing fractional spurs and high-frequency quantization noise, and belongs to the field of integrated circuit design. One end of the sigma-delta modulator is connected with the divide-by-4 divider, the other end of the sigma-delta modulator is connected with the notch filter, the divide-by-4 divider is used for receiving an external data signal, the notch filter outputs a modulated data signal, the sigma-delta modulator comprises 19-bit CLA, a first 24-bit CLA, a second 24-bit CLA, a 1-bit register and a noise elimination circuit, the 19-bit CLA is respectively connected with the divide-by-4 divider and the first 24-bit CLA, and the first 24-bit CLA is connected with the second 24-bit CLA; the input end of the noise elimination circuit is respectively connected with the 19-bit CLA, the first 24-bit CLA and the second 24-bit CLA through the 1-bit register, and the noise elimination circuit is connected with the notch filter. According to the invention, two MASH structures are combined and a notch filter structure is added, so that a smoother quantized noise power spectrum is obtained; while reducing quantization noise components at high frequencies and reducing the effect of non-linear factors in the phase locked loop on phase noise.
Description
Technical Field
The invention relates to a sigma-delta modulator capable of reducing fractional spurs and high-frequency quantization noise, and belongs to the field of integrated circuit design.
Background
The frequency synthesizer is an important component in a modern electronic system and is widely applied to the fields of communication, radar, aerospace, navigation and the like. In the field of wireless communication, a frequency synthesizer is often used in a wireless radio frequency transceiver system to provide a local oscillator signal with high resolution, low phase noise and high spectral purity for a radio frequency front end. With the rapid development of large-scale integrated circuit technology, a fully integrated and high-performance phase-locked loop circuit develops rapidly, and a frequency synthesizer based on the phase-locked loop becomes a very widely applied structure at present due to the superior performance of the frequency synthesizer. The traditional integer frequency division phase-locked loop cannot meet the requirements of some high-precision systems due to low frequency resolution. The decimal frequency division phase-locked loop can improve the frequency resolution without reducing the reference frequency, and realize the frequency output with high precision and low phase noise.
In the phase-locked loop type fractional frequency division synthesizer, a frequency divider realizes fractional frequency division on average by constantly changing instantaneous frequency division ratio, and fractional stray is formed when the fractional stray reaches the output of a VCO through a phase-locked loop. In order to suppress fractional spurs and achieve high resolution frequency output, sigma-delta modulation techniques are often introduced in frequency dividers. The technology adopts a noise forming technology to push the fractional spur to the high frequency in the form of quantization noise, and then utilizes the low-pass characteristic of the phase-locked loop to filter the fractional spur, thereby effectively inhibiting the fractional spur in the fractional frequency synthesizer. The sigma-delta modulation technique was originally used for oversampling a/D conversion circuits, and did not begin to be applied to frequency synthesizers until the mid-90 th century.
The problems existing in the technology are as follows: the combination of large-scale divide ratio jitter and loop nonlinearity can degrade the phase noise of the circuit, and at some fractional inputs the modulator output sequence is too short and the periodicity is too strong to degrade the fractional spurs, and finally the existence of high-frequency quantization noise is not favorable for the design of the phase-locked loop bandwidth.
Disclosure of Invention
The invention aims to provide a sigma-delta modulator capable of reducing fractional spurs and high-frequency quantization noise, which can realize that the output sequence length is long enough under any decimal input and the randomness is stronger, and meanwhile, the adopted notch filtering technology can inhibit the high-frequency quantization noise to a certain extent, and simultaneously, the output variation range of the sigma-delta modulator is also reduced, and the influence of the nonlinearity of a phase-locked loop on the phase noise is reduced.
To achieve the above object, the present invention provides a sigma-delta modulator capable of reducing fractional spurs and high frequency quantization noise, the sigma-delta modulator being connected to a receiving circuit at one end and to a notch filter at the other end, the receiving circuit including a divide-by-4 divider for receiving an external data signal, the notch filter for outputting a modulated data signal, the sigma-delta modulator comprising:
the input end of the 19-bit carry look ahead adder is connected with the output end of the divide-by-4 divider;
a first 24-bit carry look ahead adder, an input end of the first 24-bit carry look ahead adder being connected to an output end of the 19-bit carry look ahead adder;
a 5-bit shift module, wherein an input end of the 5-bit shift module is connected to the 19-bit carry look ahead adder, and an output end of the 5-bit shift module is connected to an input end of the first 24-bit carry look ahead adder;
the input end of the second 24-bit carry look ahead adder is connected with the output end of the first 24-bit carry look ahead adder;
the input end of the 1-bit register is respectively connected with the output end of the 19-bit carry look ahead adder, the output end of the first 24-bit carry look ahead adder and the output end of the second 24-bit carry look ahead adder;
and the input end of the noise elimination circuit is connected with the output end of the 1-bit register, and the output end of the noise elimination circuit is connected with the input end of the notch filter.
As a further improvement of the present invention, the sigma-delta modulator further includes a 19-bit register and a fourth register, the fourth register is a 1-bit register, input ends of the 19-bit register and the fourth register are respectively connected to an output end of the 19-bit carry look ahead adder, and output ends of the 19-bit register and the fourth register are respectively connected to an input end of the 19-bit carry look ahead adder.
As a further improvement of the present invention, the 19-bit carry look ahead adder includes a first 5-bit carry look ahead adder, a second 5-bit carry look ahead adder, a third 5-bit carry look ahead adder, a seventh 4-bit carry look ahead adder, and three 1-bit registers;
the input end of the first 5-bit carry look-ahead adder is connected with the output end of the fourth register;
the input end of the second 5-bit carry look ahead adder is connected with the output end of the first 5-bit carry look ahead adder through the 1-bit register;
the input end of the third 5-bit carry look ahead adder is connected with the output end of the second 5-bit carry look ahead adder through the 1-bit register;
the input end of the seventh 4-bit carry look ahead adder is connected with the output end of the third 5-bit carry look ahead adder through the 1-bit register;
the input end of the first 24-bit carry look ahead adder is connected with the output end of the seventh 4-bit carry look ahead adder;
the input end of the first 5-bit carry look-ahead adder, the input end of the second 5-bit carry look-ahead adder, the input end of the third 5-bit carry look-ahead adder and the input end of the seventh 4-bit carry look-ahead adder are respectively connected with the output end of the 19-bit register;
the input end of the first 5-bit carry look ahead adder, the input end of the second 5-bit carry look ahead adder, the input end of the third 5-bit carry look ahead adder and the input end of the seventh 4-bit carry look ahead adder are respectively connected with the output end of the divide-by-4 divider;
the input end of the 5-bit shift module is connected to the input end of the first 5-bit carry look ahead adder, the input end of the second 5-bit carry look ahead adder, the input end of the third 5-bit carry look ahead adder, and the output end of the 4-bit carry look ahead adder, respectively.
As a further improvement of the present invention, the sigma-delta modulator further includes a 24-bit register, an input end of the 24-bit register is connected to an output end of the first 24-bit carry look ahead adder or an output end of the second 24-bit carry look ahead adder respectively, and an output end of the 24-bit register is connected to an input end of the first 24-bit carry look ahead adder or the second 24-bit carry look ahead adder respectively.
As a further improvement of the present invention, each of the first 24-bit carry look ahead adder and the second 24-bit carry look ahead adder includes six 4-bit carry look ahead adders and five 1-bit registers, the six 4-bit carry look ahead adders are sequentially connected, and every two 4-bit carry look ahead adders are connected through a 1-bit register;
the input ends of the six 4-bit carry look ahead adders are connected with the output end of the 5-bit shift module or the output end of the first 24-bit carry look ahead adder;
the input ends of the six 4-bit carry look-ahead adders are all connected with the output end of the 24-bit register;
and the input ends of the 24-bit registers are respectively connected with the output ends of the six 4-bit carry look-ahead adders.
As a further improvement of the present invention, the 19-bit carry look ahead adder, the first 24-bit carry look ahead adder and the second 24-bit carry look ahead adder are all provided with 1-bit output ends, the 1-bit register includes a first register, a second register and a third register, and the 1-bit output end of the 19-bit carry look ahead adder is connected with the input end of the noise elimination circuit through the first register; the 1-bit output end of the first 24-bit carry look ahead adder is connected with the input end of the noise elimination circuit through the second register; and the 1-bit output end of the second 24-bit carry look-ahead adder is connected with the input end of the noise elimination circuit through the third register.
As a further improvement of the present invention, the noise cancellation circuit includes a first logic circuit, a second logic circuit, and an eighth 4-bit carry look ahead adder, an output end of the third register is connected to an input end of the second logic circuit, and an output end of the second logic circuit is connected to an input end of the eighth 4-bit carry look ahead adder;
the output end of the second register is connected with the input end of the first logic circuit, and the output end of the first logic circuit is connected with the input end of the eighth 4-bit carry look ahead adder;
the output end of the register is connected with the input end of the eighth 4-bit carry look-ahead adder;
and the output end of the eighth 4-bit carry look-ahead adder is connected with the input end of the notch filter.
As a further improvement of the present invention, the first logic circuit includes a first 1-bit register, a second 1-bit register, a first two-input xor gate, a second two-input xor gate, a first conventional two-input and gate, a second conventional two-input and gate, a first two-input or gate, a second two-input or gate, a first unconventional two-input and gate, and a second unconventional two-input and gate;
the input end of the first 1-bit register is connected with the output end of the third register;
the input end of the second 1-bit register is connected with the output end of the first 1-bit register;
the input end of the first two-input exclusive-or gate is respectively connected with the output end of the first 1-bit register and the output end of the second 1-bit register;
the input end of the second input exclusive-or gate is respectively connected with the output end of the third register and the output end of the second 1-bit register;
the input end of the first conventional two-input AND gate is respectively connected with the output end of the third register and the output end of the first 1-bit register;
the input end of the second conventional two-input AND gate is respectively connected with the output end of the third register and the output end of the first two-input XOR gate;
the input end of the first unconventional two-input AND gate is respectively connected with the output end of the third register and the output end of the first 1-bit register;
the input end of the second unconventional two-input AND gate is respectively connected with the output end of the second 1-bit register and the output end of the first conventional two-input AND gate;
the input end of the first two-input OR gate is respectively connected with the output end of the second conventional two-input AND gate and the output end of the first unconventional two-input AND gate;
and the input end of the second input OR gate is respectively connected with the output end of the first unconventional two-input AND gate and the output end of the second unconventional two-input AND gate.
As a further improvement of the present invention, the second logic circuit includes a third 1-bit register, a third two-input xor gate, and a third unconventional two-input and gate;
the input end of the third 1-bit register is connected with the output end of the second register;
the input end of the third second input exclusive-or gate is respectively connected with the output end of the second register and the output end of the third 1-bit register;
and the input end of the third unconventional two-input AND gate is respectively connected with the output end of the second register and the output end of the third 1-bit register.
As a further improvement of the present invention, an input end of the 4-bit carry look-ahead adder is respectively connected to an output end of the second-input xor gate, an output end of the first second-input xor gate, an output end of the second-input xor gate, an output end of the third unconventional second-input and gate, and an output end of the first register; and the output end of the 4-bit carry look-ahead adder is connected with the input end of the notch filter.
The invention has the beneficial effects that: the sigma-delta modulator capable of reducing fractional spurs and high-frequency quantization Noise adopts the combination of two Multistage cascade Noise Shaping structures (MASH), and has output sequence length long enough when all fractions are input, so that a smoother quantization Noise power spectrum can be obtained, and fractional spurs are effectively inhibited; by setting the first-stage adder to 19 bits and widening the bits of the second-stage adder to 24 bits, the circuit area can not be excessively increased while the advantages of the two structures are realized; by adding a notch filter structure to the sigma-delta modulator output, the quantization noise component of the sigma-delta modulator at high frequencies can be reduced and the effect of non-linear factors in the phase-locked loop on the phase noise can be reduced.
Drawings
Fig. 1 is a schematic diagram of a sigma-delta modulator capable of reducing fractional spurs and high frequency quantization noise according to the present invention.
Fig. 2 is a schematic diagram of a 19-bit carry look-ahead adder of fig. 1.
Fig. 3 is a schematic diagram of the 24-bit carry look-ahead adder of fig. 1.
Fig. 4 is a schematic diagram of the noise cancellation circuit of fig. 1.
Fig. 5 is a schematic diagram of the structure of the notch filter of fig. 1.
Fig. 6 is a code simulation diagram of a sigma-delta modulator of the present invention that reduces fractional spurs and high frequency quantization noise.
Fig. 7 is a graph showing a simulation of the output transient of the notch filter in the present invention.
Fig. 8 is a simulation diagram of the output power spectrum of the notch filter in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
Referring to fig. 1, the present invention provides a sigma-delta modulator 100 capable of reducing fractional spurs and high frequency quantization noise, and outputting data with a long enough output sequence and stronger randomness when any fractional number is inputted. The sigma-delta modulator 100 (i.e., the aforementioned sigma-delta modulator 100 capable of reducing fractional spurs and high frequency quantization noise) is connected to a receiving circuit at one end and connected to the notch filter 200 at the other end, the receiving circuit includes a divide-by-4 divider 300, the divide-by-4 divider 300 is configured to receive an external data signal, and the notch filter 200 outputs a modulated data signal, specifically: the input end of the divide-by-4 divider 300 is connected to the receiving circuit, the raw data is input to the divide-by-4 divider 300 through the receiving circuit, the output end of the divide-by-4 divider 300 is connected to the input end of the sigma-delta modulator 100, the output end of the sigma-delta modulator 100 is connected to the input end of the notch filter 200, and the output end of the notch filter 200 outputs the modulated data signal.
The original data is input to the input terminal IN of the divide-by-4 divider 300, then the divide-by-4 divider 300 divides the original data by 4 to obtain X, then the X is modulated by the sigma-delta modulator 100 to obtain the output Y, then the Y is input to the notch filter 200 circuit, and the modulated output OUT is obtained after the processing of the notch filter 200.
The circuit of the sigma-delta Modulator 100 is shown In fig. 1 by a large dashed box, and the first-stage Error Feedback Model (EFM) adopts the HK-EFM structure proposed by Hosseini and Kennedy, and the second and third stages adopt the SP-EFM structure proposed by Jinook Song and In-chell Park. The first-stage HK-EFM structure is composed of a 19-bit Carry look-ahead Adder 1 (CLA) and a fourth register 84 (1-bit register), the Carry output of the Adder of the structure is fed back to the Carry input of the Adder after delaying for one unit time through the 1-bit register, the accumulated value of the Adder is fed back to the input end through the 19-bit register, the Carry output is connected with the Carry input of the Adder of the next stage, and the structure has a fixed output sequence length of 219-1. The later two-stage SP-EFM structure adopts a 24-bit Carry look-ahead Adder (CLA), the Carry output of the former stage Adder is sent to the Carry input of the next stage Adder, the accumulated value of the Adder is fed back to the input end through a 24-bit register 5, the length of the output sequence of the structure is 224. A 1-bit register is inserted between the adder and the noise cancellation circuit 7 at each stage to maintain synchronism of the output at each stage. The first stage 19-bit CLA1 is connected with the second stage 24-bit CLA through a 5-bit shift module 3, and the output of the first stage is leftShifted by 5 bits and input to the second stage. Due to the addition of the second and third stages having a bit width of 24, the three-stage sigma-delta modulator 100 may ultimately achieve a fixed output sequence length of approximately 267And is not affected by the input decimal value. A sufficiently long output sequence length can obtain a smoother quantization noise power spectrum, which has a significant effect on spurious suppression, and the structure stability of the sigma-delta modulator 100 is high due to the fixed output sequence length.
The sigma-delta modulator 100 includes: 19 bits CLA1, a 19 bits register 2, a first 24 bits CLA4, a second 24 bits CLA6, a 24 bits register 5, a 5 bits shift module 3, a1 bits register, a noise elimination circuit 7 and a clock signal, wherein the input end of the 19 bits CLA1 is connected with the output end of the divide-by-4 divider 300; the input end of the first 24-bit CLA4 is connected with the output end of the 19-bit CLA 1; the input end of the second 24-bit CLA6 is connected with the output end of the first 24-bit CLA 4; the input end of the 1-bit register is respectively connected with the output end of the 19-bit CLA1, the output end of the first 24-bit CLA4 and the output end of the second 24-bit CLA 6; an input terminal of the noise canceling circuit 7 is connected to an output terminal of the 1-bit register, and an output terminal of the noise canceling circuit 7 is connected to an input terminal of the notch filter 200.
Specifically, the method comprises the following steps: the output end of the 19-bit CLA1 is connected with the input end of the first register 81, and the output end of the first register 81 is connected with the input end of the noise elimination circuit 7; the output end of the first 24-bit CLA4 is connected with the input end of the second register 82, and the output end of the second register 82 is connected with the input end of the noise elimination circuit 7; the output terminal of the second 24-bit CLA6 is connected to the input terminal of the third register 83, and the output terminal of the third register 83 is connected to the input terminal of the noise cancellation circuit 7.
The input of the 19-bit CLA1 is connected to the 19-bit output of the divide-by-4 divider 300, i.e. the divide-by-4 divider 300 transmits X via the output to the input of the 19-bit CLA.
The input ends of the 19-bit register 2 and the fourth register 84 are respectively connected with the output end of the 19-bit CLA1, and the output ends of the 19-bit register 2 and the fourth register 84 are respectively connected with the input end of the 19-bit CLA 1. Specifically, the input end of the 19-bit CLA1 is connected to the output end of the divide-by-4 divider 300 with 19 bits, the output end of the 19-bit register 2 and the output end of the fourth register 84, respectively; the 19-bit output end of the 19-bit CLA1 is respectively connected with the input end of the 19-bit register 2 and the input end of the 5-bit shifting module 3; the 1-bit output of the 19-bit CLA1 is connected to the input of the first register 81, the input of the fourth register 84 and the input of the first 24-bit CLA4, respectively.
Referring to fig. 2, the circuit structure of 19-bit CLA1 adopts a pipeline design method, and the structure is composed of three 5-bit CLAs, one 4-bit CLA and three 1-bit registers 15. The input and output of 19 bits CLA1 are divided into 4 parts for addition operation, the carry output of the preceding stage CLA is used as the input of the subsequent stage, and the obtained operation results are spliced together to form the final summation result. The result S [18:0] of the summation of the 19-bit CLA1 is changed into { S [18:0], 5' b00000} by a 5-bit shift block 3 and then connected to a 24-bit input terminal of the first 24-bit CLA 4. The carry output of the 19-bit CLA1 is connected to the external three 1-bit registers 15, wherein the output of one register is connected to the carry input of the 19-bit CLA1, and the other two registers are respectively connected to the noise cancellation circuit 7 and the carry input of the lower 24-bit CLA. To make the path delay the same, a 1-bit register 15 is added between every two CLAs. Compared with directly designing 19-bit CLA, the pipeline design method can obtain better compromise between speed and circuit area.
The 19-bit CLA1 comprises: the device comprises a first 5-bit CLA11, a second 5-bit CLA12, a third 5-bit CLA13, a seventh 4-bit CLA14 and three 1-bit registers 15, wherein the first 5-bit CLA11 and the second 5-bit CLA12 are connected through the 1-bit registers 15; the second 5-bit CLA12 and the third 5-bit CLA13 are connected through a 1-bit register 15; the third 5-bit CLA13 and the seventh 4-bit CLA14 are connected by a 1-bit register 15.
The input end of the first 5-bit CLA11 is connected to the output end of the fourth register 84, the output end of the divide-by-4 divider 300, and the output end of the 19-bit register 2, respectively; the output end of the first 5-bit CLA11 is connected to the input end of the 5-bit shift module 3 and the input end of the 1-bit register 15, specifically: two 5-bit input terminals of the first 5-bit CLA11 are respectively connected to A [4:0] and B [4:0] (respectively representing the output terminal of the divide-by-4 divider 300 and the output terminal of the 19-bit register 2), and a 5-bit output terminal and a carry output terminal of the first 5-bit CLA11 are respectively connected to S [4:0] (representing the input terminal of the 5-bit shift module 3) and the input terminal of the 1-bit register 15.
The input of the second 5-bit CLA12 is connected on the one hand via the 1-bit register 15 to the output of the first 5-bit CLA 11; on the other hand, the output of the divide-by-4 divider 300 and the output of the 19-bit register 2 are connected; the output end of the second 5-bit CLA12 is connected to the input end of the 5-bit shift module 3 and the input end of the 1-bit register 15, specifically: the two 5-bit inputs of the second 5-bit CLA12 are connected to A [9:5] and B [9:5] (representing the output of the divide-by-4 divider 300 and the output of the 19-bit register 2, respectively), and the 5-bit output and the carry output of the second 5-bit CLA12 are connected to S [9:5] (representing the input of the 5-bit shift module 3) and the input of the 1-bit register 15, respectively.
The input of the third 5-bit CLA13 is connected on the one hand via the 1-bit register 15 to the output of the second 5-bit CLA 12; on the other hand, the output of the divide-by-4 divider 300 and the output of the 19-bit register 2 are connected; the output end of the third 5-bit CLA13 is connected to the input end of the 5-bit shift module 3 and the input end of the 1-bit register 15, specifically: two 5-bit input terminals of the third 5-bit CLA13 are respectively connected to A [14:10] and B [14:10] (respectively representing the output terminal of the divide-by-4 divider 300 and the output terminal of the 19-bit register 2), and a 5-bit output terminal and a carry output terminal of the third 5-bit CLA13 are respectively connected to S [14:10] (representing the input terminal of the 5-bit shift module 3) and the input terminal of the 1-bit register 15.
The input of the seventh 4-bit CLA14 is connected on the one hand via the 1-bit register 15 to the output of the third 5-bit CLA 13; on the other hand, the output of the divide-by-4 divider 300 and the output of the 19-bit register 2 are connected; the output terminal of the seventh 4-bit CLA14 is connected to the input terminal of the 5-bit shift module 3, and to the input terminal of the first register 81, the input terminal of the fourth register 84, and the input terminal of the first 24-bit CLA4, specifically: two 5-bit input terminals of the seventh 4-bit CLA14 are respectively connected to A [18:15] and B [18:15] (respectively representing the output terminal of the divide-by-4 divider 300 and the output terminal of the 19-bit register 2), and a 5-bit output terminal and a carry output terminal of the seventh 4-bit CLA14 are respectively connected to S [18:15] (representing the input terminal of the 5-bit shift module 3) and the input terminal of the first register 81, the input terminal of the fourth register 84, and the input terminal of the first 24-bit CLA 4.
The input end of the first 24-bit CLA4 is connected to the 1-bit output end of the 19-bit CLA1, meanwhile, the input end of the 5-bit shift module 3 is connected to the 19-bit output end of the 19-bit CLA1, the 5-bit shift module 3 shifts the output of the 19-bit CLA1 by 5 bits to the left and inputs the output to the first 24-bit CLA4, and the 24-bit output end of the 5-bit shift module 3 is connected to the input end of the first 24-bit CLA4, that is, the 19-bit CLA1 and the first 24-bit CLA4 perform data transmission in two ways (1-bit data transmission and 5-bit shift module 3 data transmission, respectively).
An input of the 24-bit register 5 is connected to an output of the first 24-bit CLA4, and an output of the 24-bit register 5 is connected to an input of the first 24-bit CLA 4.
An input terminal of the second 24-bit CLA6 is connected to a 1-bit output terminal of the first 24-bit CLA4, and an input terminal of the second 24-bit CLA6 is connected to a 24-bit output terminal of the first 24-bit CLA4, that is, data transmission (1-bit data transmission and 24-bit data transmission, respectively) is performed between the first 24-bit CLA4 and the second 24-bit CLA 6.
An input of the 24-bit register 5 is connected to an output of the second 24-bit CLA6, and an output of the 24-bit register 5 is connected to an input of the second 24-bit CLA 6.
Referring to fig. 3, the circuit structure of 24-bit CLA is also designed in a pipeline manner, and the structure is composed of six 4-bit CLAs. The input and output of 24-bit CLA are divided into 6 parts, which are sent to 6 4-bit CLA respectively for operation, and the obtained results are spliced to form the final operation result. The carry output of the 24-bit CLA is connected to the next carry input and to a 1-bit register 47 which is connected to the noise cancellation circuit 7. A 1-bit register 47 is also added between every two 4-bit CLAs to ensure that each path delay remains approximately equal.
The first 24-bit CLA4 and the second 24-bit CLA6 each include six 4-bit CLAs and five 1-bit registers 47, the six 4-bit CLAs are sequentially connected, an input terminal of the first 4-bit CLA is connected to an output terminal of the 19-bit CLA1 or an output terminal of the first 24-bit CLA4, an output terminal of the last 4-bit CLA is connected to an input terminal of the second 24-bit CLA6 or an input terminal of the third register 83, and every two 4-bit CLAs are connected through the 1-bit registers 47.
Six 4-bit CLAs are respectively defined as a first 4-bit CLA 41, a second 4-bit CLA 4242, a third 4-bit CLA43, a fourth 4-bit CLA44, a fifth 4-bit CLA45 and a sixth 4-bit CLA 46; the method specifically comprises the following steps: the carry input terminal of the first 4-bit CLA 41 is connected to an external input Cin (Cin is a 1-bit output terminal of 19-bit CLA or a 1-bit output terminal of the first 24-bit CLA 4), two 4-bit input terminals of the first 4-bit CLA 41 are respectively connected to A [3:0] and B [3:0], and a 4-bit output terminal and a carry output terminal of the first 4-bit CLA 41 are respectively connected to S [3:0] and an input terminal of the 1-bit register 47.
The carry input end of the second 4-bit CLA 4242 is connected with the output end of the 1-bit register 47, two 4-bit input ends of the second 4-bit CLA 4242 are respectively connected with A [7:4] and B [7:4], and the 4-bit output end and the carry output end of the second 4-bit CLA 4242 are respectively connected with S [7:4] and the input end of the 1-bit register 47.
The carry input terminal of the third 4-bit CLA43 is connected to the output terminal of the 1-bit register 47, the two 4-bit input terminals of the third 4-bit CLA43 are respectively connected to A [11:8] and B [11:8], and the 4-bit output terminal and the carry output terminal of the third 4-bit CLA43 are respectively connected to S [11:8] and the input terminal of the 1-bit register 47.
The carry input end of the fourth 4-bit CLA44 is connected with the output end of the 1-bit register 47, two 4-bit input ends of the fourth 4-bit CLA44 are respectively connected with A [15:12] and B [15:12], and the 4-bit output end and the carry output end of the fourth 4-bit CLA44 are respectively connected with S [15:12] and the input end of the 1-bit register 47.
The carry input terminal of the fifth 4-bit CLA45 is connected to the output terminal of the 1-bit register 47, the two 4-bit input terminals of the fifth 4-bit CLA45 are respectively connected to A [19:16] and B [19:16], and the 4-bit output terminal and the carry output terminal of the fifth 4-bit CLA45 are respectively connected to S [19:16] and the input terminal of the 1-bit register 47.
The carry input terminal of the sixth 4-bit CLA46 is connected to the output terminal of the 1-bit register 47, two 4-bit input terminals of the sixth 4-bit CLA46 are respectively connected to a [23:20] and B [23:20], and the 4-bit output terminal and the carry output terminal of the sixth 4-bit CLA46 are respectively connected to S [23:20] and Cout (Cout is the input terminal of the second 24-bit or the 1-bit input terminal of the third register 83).
Wherein A [3:0], A [7:4], A [11:8], A [15:12], A [19:16] and A [23:20] represent the output of the 24-bit register 5; b [3:0], B [7:4], B [11:8], B [15:12] and B [23:20] represent the 24-bit output of the 5-bit shift module or the 24-bit output of the first 24-bit CLA 4; s [3:0], S [7:4], S [11:8], S [15:12], S [19:16] and S [23:20] represent the 24-bit input of a second 24-bit CLA6 or the input of 24-bit register 5.
Referring to fig. 4, a structure of the noise cancellation circuit 7 is shown, and the purpose of this part of the circuit is to cancel the quantization noise of the first two stages of EFMs through a series of delay and logic operations, and only leave the noise of the last stage of EFM. The last stage noise is shaped by high order and high frequency part is filtered by low pass filter in phase locked loop.
The noise cancellation circuit 7 includes a first logic circuit 71, a second logic circuit 72, and an eighth 4-bit CLA73, an output terminal of the third register 83 is connected to an input terminal of the second logic circuit 72, and an output terminal of the second logic circuit 72 is connected to an input terminal of the eighth 4-bit CLA 73; the output end of the second register 82 is connected with the input end of the first logic circuit 71, and the output end of the first logic circuit 71 is connected with the input end of the eighth 4-bit CLA 73; the output end of the first register 81 is connected to the input end of the eighth 4-bit CLA 73; an output of the eighth 4-bit CLA73 is connected to an input of the notch filter 200.
Specifically, the method comprises the following steps: the first logic circuit 71 includes a first 1-bit register 710, a second 1-bit register 711, a first two-input xor gate 712, a second two-input xor gate 713, a first conventional two-input and gate 714, a second conventional two-input and gate 715, a first two-input or gate 716, a second two-input or gate 717, a first unconventional two-input and gate 718, and a second unconventional two-input and gate 719.
An input of the first 1-bit register 710 is connected to an output of the third register 83.
The input of the second 1-bit register 711 is connected to the output of the first 1-bit register 710.
The input terminals of the first two-input xor gate 712 are connected to the output terminal of the first 1-bit register 710 and the output terminal of the second 1-bit register 711, respectively.
The inputs of the second input xor gate 713 are connected to the output of the third register 83 and to the output of the second 1-bit register 711, respectively.
The inputs of the first conventional two-input and gate 714 are connected to the output of the third register 83 and to the output of the first 1-bit register 710, respectively.
The input terminals of the second conventional two-input and gate 715 are connected to the output terminal of the third register 83 and the output terminal of the first two-input xor gate 712, respectively.
The inputs of the first unconventional two-input and gate 718 are connected to the output of the third register 83 and to the output of the first 1-bit register 710, respectively.
The inputs of the second non-conventional two-input and gate 719 are connected to the output of the second 1-bit register 711 and the output of the first conventional two-input and gate 714, respectively.
The input terminals of the first two-input or gate 716 are connected to the output terminal of the second conventional two-input and gate 715 and the output terminal of the first non-conventional two-input and gate 718, respectively.
The input of the second two-input or gate 717 is connected to the output of the first and second non-conventional two-input and gates 718 and 719, respectively.
The second logic circuit 72 includes a third 1-bit register 721, a third two-input xor gate 722, and a third unconventional two-input and gate 723.
An input of the third 1-bit register 721 is connected to an output of the second register 82.
The inputs of the third two-input xor gate 722 are connected to the output of the second register 82 and to the output of the third 1-bit register 721, respectively.
An input terminal of the third unconventional two-input and gate 723 is connected to an output terminal of the second register 82 and an output terminal of the third 1-bit register 721, respectively.
The input terminals (A [3:0] and B [3:0]) of the eighth 4-bit CLA73 are connected to the output terminal A [0] of the second input XOR gate 713, the output terminal A [1] of the first second input OR gate 716, the output terminal A [2]/A [3] of the second input OR gate 717, the output terminal B [1]/B [2]/B [3] of the third second input XOR gate 722, the output terminal B [0] of the third unconventional second input AND gate 723, and the output terminal of the first register 81, respectively; the output Y [3:0] of the eighth 4-bit CLA73 is connected to the input of the notch filter 200.
Referring to fig. 5, in the notch filter 200, the fractional input value is divided by 4 before passing through the sigma-delta modulator 100, and then the output of the sigma-delta modulator 100 passes through the filter circuit to recover the original value expectation. Since the output sequence range of the sigma-delta modulator 100 is-3 to +4, the number of output levels is large, which is very sensitive to the analog circuit nonlinearity in the fractional frequency synthesizer, thereby deteriorating the circuit noise performance. After the notch filter 200 is introduced, the output sequence level can be more concentrated, the sensitivity to the nonlinearity of an analog circuit is reduced, and the effect of optimizing the phase noise performance of the circuit is further achieved. Meanwhile, the structure can have a certain filtering effect on noise around fs/4 frequency (wherein fs is the working frequency of the sigma-delta modulator 100).
The notch filter 200 circuit includes a first 4-bit register 204, a second 4-bit register 205, a third 4-bit register 206, and a ninth 4-bit CLA 201, a tenth 4-bit CLA202, and an eleventh 4-bit CLA 203.
The input end of the first 4-bit register 204 is connected with an external input Y (Y is the output end of the noise elimination circuit 7); the input end of the second 4-bit register 205 is connected with the output end of the first 4-bit register 204; the input of the third 4-bit register 206 is terminated by the output of the second 4-bit register 205.
The input end of the ninth 4-bit CLA 201 is connected with the output end of the ninth 4-bit register and the external input Y; the input end of the tenth 4-bit CLA202 is connected with the output end of the ninth 4-bit CLA 201 and the output end of the tenth 4-bit register; the input end of the eleventh 4-bit CLA 203 is connected with the output end of the tenth 4-bit CLA202 and the output end of the eleventh 4-bit register; the output terminal OUT (outputs the modulated data signal) of the eleventh 4-bit CLA 203.
The clock signal determines the update period of each component, the clock input terminal of the notch filter 200 and the clock input terminals of all the circuits except the 5-bit shift module 3 are connected to the clock signal CLK, the output terminal of the notch filter 200 is connected to the outside, and the case of the english alphabet is not limited in this embodiment.
Referring to FIG. 6, the decimal input value fcw _ f in the code simulation diagram of the present invention is 262144 (i.e., 2)18) The integer input value fcw _ i is 222, clk and reset are the circuit operation clock signal and the reset signal, respectively. Since the input to the sigma-delta modulator 100 is 19 bits, the fractional value here represents 0.5 (i.e., 2)18Is divided by 219). dout is the sum of the output out _ fra of the notch filter 200 and the fixed division ratio 222, and taking the sum and averaging of 20 data as shown in the figure can result in a division ratio of 222.5 in the sense of an average, so that the sigma-delta modulator 100 functions normally.
Referring to fig. 7, it can be seen from the output transient simulation diagram of the notch filter 200 that the output range is-3- +4, and the number of times of high values-3 and +4 is very small, and the output level is mainly concentrated between-2- +3, which is in accordance with the design expectation.
Referring to fig. 8, it can be seen from the output power spectrum simulation of the notch filter 200 that the noise at high frequencies is suppressed to some extent. Because the decimal input value is 0.5, the output periodicity of the traditional MASH structure is very obvious to cause the power spectrum to be dispersed, while the output power spectrum of the invention is smooth and the output sequence has no obvious periodicity. The sampling frequency of the sigma-delta modulator 100 is 50MHz, so the resulting frequency point to be suppressed should be 12.5 MHz.
In summary, the sigma-delta modulator capable of reducing fractional spurs and high-frequency quantization noise of the present invention mainly includes a divide-by-4 divider 300, a sigma-delta modulator 100, and a notch filter 200, wherein the sigma-delta modulator 100 adopts a combination of two MASH structures, and has a sufficiently long output sequence length when all fractions are input, so as to obtain a smoother quantization noise power spectrum, and effectively suppress fractional spurs; by setting the first-stage adder to 19 bits and widening the bits of the second-stage adder to 24 bits, the circuit area can not be excessively increased while the advantages of the two structures are realized; by adding the notch filter 200 structure to the output of the sigma-delta modulator 100, the quantization noise component of the sigma-delta modulator 100 at high frequencies can be reduced and the influence of non-linear factors in the phase-locked loop on the phase noise can be reduced.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention.
Claims (10)
1. A sigma-delta modulator that reduces fractional spurs and high frequency quantization noise, comprising: one end of the sigma-delta modulator is connected with a receiving circuit, the other end of the sigma-delta modulator is connected with a notch filter, the receiving circuit comprises a divide-by-4 divider, the divide-by-4 divider is used for receiving an external data signal, the notch filter is used for outputting a modulated data signal, and the sigma-delta modulator comprises:
the input end of the 19-bit carry look ahead adder is connected with the output end of the divide-by-4 divider;
a first 24-bit carry look ahead adder, an input end of the first 24-bit carry look ahead adder being connected to an output end of the 19-bit carry look ahead adder;
a 5-bit shift module, wherein an input end of the 5-bit shift module is connected to the 19-bit carry look ahead adder, and an output end of the 5-bit shift module is connected to an input end of the first 24-bit carry look ahead adder;
the input end of the second 24-bit carry look ahead adder is connected with the output end of the first 24-bit carry look ahead adder;
the input end of the 1-bit register is respectively connected with the output end of the 19-bit carry look ahead adder, the output end of the first 24-bit carry look ahead adder and the output end of the second 24-bit carry look ahead adder;
and the input end of the noise elimination circuit is connected with the output end of the 1-bit register, and the output end of the noise elimination circuit is connected with the input end of the notch filter.
2. A sigma-delta modulator that reduces fractional spurs and high frequency quantization noise according to claim 1, characterized by: the sigma-delta modulator further comprises a 19-bit register and a fourth register, the fourth register is a 1-bit register, input ends of the 19-bit register and the fourth register are respectively connected with an output end of the 19-bit carry look ahead adder, and output ends of the 19-bit register and the fourth register are respectively connected with an input end of the 19-bit carry look ahead adder.
3. A sigma-delta modulator that reduces fractional spurs and high frequency quantization noise according to claim 2, characterized by: the 19-bit carry look ahead adder comprises a first 5-bit carry look ahead adder, a second 5-bit carry look ahead adder, a third 5-bit carry look ahead adder, a seventh 4-bit carry look ahead adder and three 1-bit registers;
the input end of the first 5-bit carry look-ahead adder is connected with the output end of the fourth register;
the input end of the second 5-bit carry look ahead adder is connected with the output end of the first 5-bit carry look ahead adder through the 1-bit register;
the input end of the third 5-bit carry look ahead adder is connected with the output end of the second 5-bit carry look ahead adder through the 1-bit register;
the input end of the seventh 4-bit carry look ahead adder is connected with the output end of the third 5-bit carry look ahead adder through the 1-bit register;
the input end of the first 24-bit carry look ahead adder is connected with the output end of the seventh 4-bit carry look ahead adder;
the input end of the first 5-bit carry look-ahead adder, the input end of the second 5-bit carry look-ahead adder, the input end of the third 5-bit carry look-ahead adder and the input end of the seventh 4-bit carry look-ahead adder are respectively connected with the output end of the 19-bit register;
the input end of the first 5-bit carry look ahead adder, the input end of the second 5-bit carry look ahead adder, the input end of the third 5-bit carry look ahead adder and the input end of the seventh 4-bit carry look ahead adder are respectively connected with the output end of the divide-by-4 divider;
the input end of the 5-bit shift module is connected to the input end of the first 5-bit carry look ahead adder, the input end of the second 5-bit carry look ahead adder, the input end of the third 5-bit carry look ahead adder, and the output end of the 4-bit carry look ahead adder, respectively.
4. A sigma-delta modulator that reduces fractional spurs and high frequency quantization noise according to claim 1, characterized by: the sigma-delta modulator further comprises a 24-bit register, an input end of the 24-bit register is connected with an output end of the first 24-bit carry look ahead adder or an output end of the second 24-bit carry look ahead adder respectively, and an output end of the 24-bit register is connected with an input end of the first 24-bit carry look ahead adder or an input end of the second 24-bit carry look ahead adder respectively.
5. A sigma-delta modulator that reduces fractional spurs and high frequency quantization noise according to claim 4, characterized by: the first 24-bit carry look ahead adder and the second 24-bit carry look ahead adder both comprise six 4-bit carry look ahead adders and five 1-bit registers, the six 4-bit carry look ahead adders are sequentially connected, and every two 4-bit carry look ahead adders are connected through the 1-bit registers;
the input ends of the six 4-bit carry look ahead adders are connected with the output end of the 5-bit shift module or the output end of the first 24-bit carry look ahead adder;
the input ends of the six 4-bit carry look-ahead adders are all connected with the output end of the 24-bit register;
and the input ends of the 24-bit registers are respectively connected with the output ends of the six 4-bit carry look-ahead adders.
6. A sigma-delta modulator that reduces fractional spurs and high frequency quantization noise according to claim 1, characterized by: the 19-bit carry look ahead adder, the first 24-bit carry look ahead adder and the second 24-bit carry look ahead adder are all provided with 1-bit output ends, the 1-bit register comprises a first register, a second register and a third register, and the 1-bit output end of the 19-bit carry look ahead adder is connected with the input end of the noise elimination circuit through the first register; the 1-bit output end of the first 24-bit carry look ahead adder is connected with the input end of the noise elimination circuit through the second register; and the 1-bit output end of the second 24-bit carry look-ahead adder is connected with the input end of the noise elimination circuit through the third register.
7. A sigma-delta modulator that reduces fractional spurs and high frequency quantization noise according to claim 6, characterized by: the noise elimination circuit comprises a first logic circuit, a second logic circuit and an eighth 4-bit carry look ahead adder, wherein the output end of the third register is connected with the input end of the second logic circuit, and the output end of the second logic circuit is connected with the input end of the eighth 4-bit carry look ahead adder;
the output end of the second register is connected with the input end of the first logic circuit, and the output end of the first logic circuit is connected with the input end of the eighth 4-bit carry look ahead adder;
the output end of the register is connected with the input end of the eighth 4-bit carry look-ahead adder;
and the output end of the eighth 4-bit carry look-ahead adder is connected with the input end of the notch filter.
8. A sigma-delta modulator that reduces fractional spurs and high frequency quantization noise according to claim 7, wherein: the first logic circuit comprises a first 1-bit register, a second 1-bit register, a first two-input exclusive-OR gate, a second two-input exclusive-OR gate, a first conventional two-input AND gate, a second conventional two-input AND gate, a first two-input OR gate, a second two-input OR gate, a first unconventional two-input AND gate and a second unconventional two-input AND gate;
the input end of the first 1-bit register is connected with the output end of the third register;
the input end of the second 1-bit register is connected with the output end of the first 1-bit register;
the input end of the first two-input exclusive-or gate is respectively connected with the output end of the first 1-bit register and the output end of the second 1-bit register;
the input end of the second input exclusive-or gate is respectively connected with the output end of the third register and the output end of the second 1-bit register;
the input end of the first conventional two-input AND gate is respectively connected with the output end of the third register and the output end of the first 1-bit register;
the input end of the second conventional two-input AND gate is respectively connected with the output end of the third register and the output end of the first two-input XOR gate;
the input end of the first unconventional two-input AND gate is respectively connected with the output end of the third register and the output end of the first 1-bit register;
the input end of the second unconventional two-input AND gate is respectively connected with the output end of the second 1-bit register and the output end of the first conventional two-input AND gate;
the input end of the first two-input OR gate is respectively connected with the output end of the second conventional two-input AND gate and the output end of the first unconventional two-input AND gate;
and the input end of the second input OR gate is respectively connected with the output end of the first unconventional two-input AND gate and the output end of the second unconventional two-input AND gate.
9. A sigma-delta modulator that reduces fractional spurs and high frequency quantization noise according to claim 8, wherein: the second logic circuit comprises a third 1-bit register, a third second input exclusive-OR gate and a third unconventional second input AND gate;
the input end of the third 1-bit register is connected with the output end of the second register;
the input end of the third second input exclusive-or gate is respectively connected with the output end of the second register and the output end of the third 1-bit register;
and the input end of the third unconventional two-input AND gate is respectively connected with the output end of the second register and the output end of the third 1-bit register.
10. A sigma-delta modulator that reduces fractional spurs and high frequency quantization noise according to claim 9, wherein: the input end of the 4-bit carry look-ahead adder is respectively connected with the output end of the second-input exclusive-or gate, the output end of the first second-input or gate, the output end of the second-input or gate, the output end of the third second-input exclusive-or gate, the output end of the third unconventional second-input and gate and the output end of the first register; and the output end of the 4-bit carry look-ahead adder is connected with the input end of the notch filter.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818376A (en) * | 1996-02-23 | 1998-10-06 | Sgs-Thomson Microelectronics S.R.L. | Introduction of a whitener signal in a Sigma Delta modulator in the conversion of digital audio signals |
| US20050078733A1 (en) * | 2003-10-09 | 2005-04-14 | Hershey John Erik | Time-delayed transmitted reference spread spectrum transmitter with digital noise generator |
| CN102394654A (en) * | 2011-10-10 | 2012-03-28 | 电子科技大学 | Delta-sigma modulator applicable to decimal frequency division |
| CN105024701A (en) * | 2015-07-08 | 2015-11-04 | 中国电子科技集团公司第四十一研究所 | Frequency dividing ratio modulator used for spurious suppression |
| CN106656102A (en) * | 2016-12-14 | 2017-05-10 | 东南大学 | Method for adding external disturbance signal of multilevel noise shaping digital Delta-Sigma modulators |
-
2021
- 2021-09-26 CN CN202111128198.8A patent/CN113872604B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818376A (en) * | 1996-02-23 | 1998-10-06 | Sgs-Thomson Microelectronics S.R.L. | Introduction of a whitener signal in a Sigma Delta modulator in the conversion of digital audio signals |
| US20050078733A1 (en) * | 2003-10-09 | 2005-04-14 | Hershey John Erik | Time-delayed transmitted reference spread spectrum transmitter with digital noise generator |
| CN102394654A (en) * | 2011-10-10 | 2012-03-28 | 电子科技大学 | Delta-sigma modulator applicable to decimal frequency division |
| CN105024701A (en) * | 2015-07-08 | 2015-11-04 | 中国电子科技集团公司第四十一研究所 | Frequency dividing ratio modulator used for spurious suppression |
| CN106656102A (en) * | 2016-12-14 | 2017-05-10 | 东南大学 | Method for adding external disturbance signal of multilevel noise shaping digital Delta-Sigma modulators |
Non-Patent Citations (1)
| Title |
|---|
| 陈静涛;: "一种新的适用于小数分频技术delta-sigma调制器结构", 硅谷, no. 18, 23 September 2011 (2011-09-23) * |
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