JPH0786838A - Quadrature detection circuit - Google Patents

Abstract

PURPOSE:To provide a digital quadrature detection circuit operated by a low- speed circuit. CONSTITUTION:This circuit is provided with a pair of exclusive OR circuits 1 and 2 for respectively one-bit multiplying binary-quantized phase modulation signals A and the singlas B1 and B2 of 0 deg. and 90 deg. for gradrature detection, latch circuits 10 and 11 for latching the output C1 and C2 of the circuits by a high-speed clock T, serial/parallel conversion circuits 20 and 21 for outputting the output D1 and D2 of the circutis in M (M is an integer equal to or more than 2) parallel series, counting circuits 30 and 31 for counting the number of positive output within M the output of the circuits and cumulative addition circuits 40 and 41 for cumulatively adding the output of the circuits over a fixed period of time and outputting a cumulative added value as quadrature detection output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature detection circuit used for a demodulator in digital radio communication.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional digital quadrature detection circuit. The binary-quantized reception modulation signal A is input to the exclusive OR circuits 1 and 2, and the quadrature detection signals B1 and B2 are respectively multiplied by 1 bit to become signals C1 and C2. The signals C1 and C2 are latched by the high-speed clock T in the latch circuits 10 and 11 and become signals D1 and D2.
1 and D2 are input to the cumulative addition circuits 40 and 41. The cumulative addition circuits 40 and 41 perform cumulative addition of a positive (“1”) number of the signals D1 and D2 in a certain period, and quadrature detection signals H1 and H from which output harmonic components are removed.
2 is output. Regarding the correspondence with the analog type quadrature detection circuit, the exclusive OR circuit corresponds to the mixer, and the latch circuit and the cumulative addition circuit correspond to the low pass filter.

By the way, in order to prevent the deterioration in the quadrature detection section, the frequency of the high speed clock T needs to be about 100 times as high as the modulation signal clock frequency or more.

[0004]

Since the conventional digital quadrature detection circuit operates at a very high operating speed (about 100 times the modulation signal clock rate), it is very difficult to realize a demodulator by using an LSI or the like. A lot of power consumption is required. Therefore, in a receiver for a mobile device, etc., in which power consumption is severely limited, it is an issue to reduce the power consumption of the quadrature detection circuit.

An object of the present invention is to provide a digital quadrature detection circuit which operates in a low speed circuit.

[0006]

The features of the present invention for achieving the above-mentioned object are an exclusive OR (E) for multiplying a binary quantized reception phase modulated signal by a quadrature detection signal by 1 bit.
x-OR) circuit, a latch circuit that latches the output of the exclusive OR circuit with a high-speed clock, a serial-parallel conversion circuit that outputs the latch circuit output in M parallel series, and the serial-parallel conversion circuit. The quadrature detection circuit includes a counting circuit that counts the number of positive (“1”) in the circuit output and a cumulative addition circuit that performs cumulative addition for a fixed period and outputs a cumulative addition value.

[0007]

In the digital quadrature detection circuit, the multiplication output is M
Since it is converted into the parallel series and processed, the operating speed of the cumulative addition circuit having a large circuit scale ratio is reduced to a fraction of the conventional speed (1 / M). Therefore, the power consumption of the quadrature detection circuit as a whole can be reduced.

[0008]

1 is a block diagram of an embodiment of the present invention. The binary-quantized reception modulation signal A is input to the exclusive OR circuits 1 and 2, and the quadrature detection signals B1 and B2 are respectively multiplied by 1 bit to become signals C1 and C2. The signal C
1 and C2 are latched by the high speed clock T in the latch circuits 10 and 11 and become signals D1 and D2. The signal D1,
D2 is input to the serial / parallel conversion circuits 20 and 21, and becomes M-bit parallel signals E1 and E2. The signal E
1 and E2 are input to the counting circuits 30 and 31, and the parallel signals E1 and E are operated at an operating speed of 1 / M of the high speed clock T.
The count value of the positive (“1”) number in 2 is output as signals F1 and F2. The signals F1 and F2 are M of the high-speed clock T.
It is input to the cumulative addition circuits 40 and 41 that operate at one-half,
The cumulative addition result is output as the quadrature detection signals G1 and G2 from which the harmonic components have been removed.

[0009]

EFFECTS OF THE INVENTION In a digital quadrature detection circuit, a cumulative addition circuit having a large circuit scale is used as a fraction of the conventional speed.
Since the operation is performed at (1 / M), the power consumption of the quadrature detection circuit is significantly reduced. A practical value for the value of M is 5 to 6, for example.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional example.

[Explanation of symbols]

 1, 2 Exclusive-OR (Ex-OR) circuit 10, 11 Latch circuit 20, 21 Serial parallel conversion circuit (1 → M series) 30, 31 Counting circuit 40, 41 Cumulative addition circuit 50 M Frequency divider circuit

Claims (1)

[Claims] 1. A pair of exclusive OR circuits (1) that multiplies a binary quantized phase modulation signal (A) and 0 ° and 90 ° quadrature detection signals (B1, B2) by 1 bit each. ，
2), a latch circuit (10, 11) for latching the output (C1, C2) of the circuit with a high-speed clock (T), and M outputs (D1, D2) of the circuit (M is 2 or more). A serial-parallel conversion circuit (20, 21) for outputting a parallel series of (integer), a counting circuit (30, 31) for counting the number of positive outputs among the M outputs of the circuit, A cumulative addition circuit (4) that cumulatively adds the outputs over a certain period and outputs the cumulative addition value as a quadrature detection output.
0, 41), and a quadrature detection circuit.