JP3190779B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a programmable controller having a processor dedicated to sequence processing and performing data processing and process control in addition to sequence control for high-speed scan processing. About.

[0002]

2. Description of the Related Art As a conventional programmable controller of this kind, there is one having a configuration shown in FIG. FIG.
1A, a sequence processing dedicated processor 1, a program memory 2, a data memory 3, and a numerical operation processor 4 are connected by a common bus 5, and the sequence processing dedicated processor 1 is stored in the program memory 2. Instructions are sequentially fetched and processing is performed. FIG. 8B is a time chart showing this processing mode. As shown in FIG. 8B, the sequence processing dedicated processor 1 performs the processing by itself each time the sequence instructions A and B are fetched. When a data processing instruction or a process control processing instruction FNC (C, D, E) is fetched, a processing request is issued to the numerical processor 4, and the sequence processing dedicated processor 1 enters a wait operation. The numerical operation processor 4 is started by the processing request, processes the data processing instruction or the sequence control instruction FNC (C, D, E), and then terminates the processing by the processor 1 dedicated to the sequence processing.
And the numerical operation processor 4 returns to the wait operation.
The sequence processing dedicated processor 1 cancels the wait operation in response to the processing completion notification, and sequentially fetches the next and subsequent sequence instructions F, G, H to continue the self processing.
In this way, the program instructions stored in the program memory 2 are repeatedly scanned at high speed.

[0003]

As described above, in the conventional programmable controller, a sequence instruction, a data processing instruction, and a process control instruction are executed serially, and the scan time is sequenced. It is determined by the total time of program instruction processing time including processing, data processing, and process control processing. Above all, it often depends on the execution time of data processing and process processing that require processing time.

For this reason, in addition to the sequence control which requires a high-speed scanning operation, there is a problem that the scanning is slow in a program which also performs data processing and process control, and further, the capacity of the program is increased. The problem that cannot be done has arisen.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to perform sequence control, data processing and process control without impairing the high-speed scanning operation of sequence control. You can control everything, and
It is an object of the present invention to provide a programmable controller capable of coping with an increase in program capacity.

[0006]

In order to achieve the above object, the present invention provides a sequence for sequentially reading out program instructions stored in a program memory and executing a sequence process.
The following means is provided in a programmable controller having a cans processor. (1) The invention according to claim 1 is characterized in that the program instruction is a secret code.
A data processing processor for executing the data processing instruction, including a sequence instruction, a data processing instruction, and a process control instruction; a process control processing processor for executing the process control instruction; and an operand of the program instruction. A data memory for storing data to be addressed and a control flag in pairs, wherein the data processing processor or the process control processor is executing the data processing instruction or the process control instruction while the data processing processor or the process control processor is executing the processing; -A sequence processing processor that sets a control flag at an address specified by an operand of a data processing instruction or a process control instruction and executes a sequence instruction in parallel with the data processing or the process control processing. When the control flag of the address specified by the operand of the sequence instruction is set, the sequence The processor is provided with means for the waiting state. (2) In the invention of claim 2, the program instruction is a secret code.
A data processor for executing the data processing instruction, the processor including a sequence instruction, a data processing instruction, and a process control instruction; a process control processor for executing the process control instruction; and the data processing processor. Alternatively, a means for outputting a monitor signal indicating that the process control processor is executing the data processing instruction or the process control instruction, and a sequence instruction in parallel with the data processing or the process control processing. When the sequence processor to be executed executes a predetermined program instruction, there is provided means for placing the sequence processor in a waiting state according to the state of the monitor signal. (3) In the invention according to claim 3, the program instruction is a secret code.
A data processing processor for executing the data processing instruction, the data processing instruction including a sequence instruction, a data processing instruction, and a process control instruction. And
A sequence instruction is included in parallel with the data processing or the process control processing. When the sequence processor to be executed reads the interrupt instruction, the data processing or the process control processing is interrupted, and when the restart instruction is read, the interrupted data processing or the process control processing is executed. Is provided.

[0007]

[Action]

(1) According to the first aspect of the present invention, if the program instruction fetched by the sequence processing processor is a sequence instruction, the processing is performed by itself, and if the fetched instruction is a data processing instruction or a process control instruction, the data processing is performed. A processing request is issued to the processor or the process control processor. The data processor or the data processor which has requested the processing first sets the control flag of the data memory addressed by the operand of the instruction. After this,
An operation restart notification is given to the sequence processor, and processing of the corresponding instruction is started. On the other hand, the sequence processing processor that has received the operation restart notification sequentially fetches the subsequent sequence instructions, and executes the sequence processing in parallel with the data processing or the process control processing. In this case, if the control flag of the data memory addressed by the operand of the sequence instruction processed in parallel is set, the processing of the sequence instruction is interrupted until the control flag is reset. A wait operation is performed. When the data processor or the process control processor completes the instruction processing, the control flag of the corresponding operand is reset. (2) The invention according to claim 2 performs the processing by itself if the program instruction fetched by the sequence processing processor is a sequence instruction, and performs data processing if the fetched instruction is a data processing instruction or a process control instruction. A processing request is issued to the processor or the process control processor. The data processor or process control processor requested to perform the processing sets a monitor signal indicating that the processing has been started, and starts processing the corresponding instruction. On the other hand, after making a processing request, the sequence processor sequentially fetches new sequence instructions and executes the sequence processing in parallel with the data processing or the process control processing. In this case, when a predetermined program instruction is fetched,
The can processor performs a wait operation until the monitor signal is reset. When the data processing processor or the process control processing processor completes the instruction processing, it resets the monitor signal. (3) The invention according to claim 3 is to perform the processing by itself if the program instruction fetched by the sequence processing processor is a sequence instruction, and perform the data processing if the fetched instruction is a data processing instruction or a process control instruction. A processing request is issued to the processor or the process control processor. The data processor or the process control processor requested to perform the processing starts the processing of the corresponding instruction.

After issuing a processing request, the sequence processor sequentially fetches new sequence instructions and executes the sequence processing in parallel with the data processing or the process control processing. In this case, the sequence processor interrupts the data processor or the process control processor when fetching the interrupt instruction, and resumes the interrupted processing when fetching the resume instruction.

[0009]

FIG. 1 shows a first embodiment of the present invention. In FIG. 1, a sequence processing dedicated processor 1, a program memory 2, a data processing dedicated processor 6, a process control processing dedicated processor 7, and a data memory 8 are connected by a common bus 5. The program memory 2 stores program instructions including a sequence instruction, a data processing instruction, and a process control instruction. Day
The data memory 8 stores the data of the operands of the program instruction. In this embodiment, the control flag 8a
Are stored in pairs with the data 8b.

The operation of this embodiment will be described with reference to a time chart shown in FIG. The sequence processing dedicated processor 1 sequentially fetches the program instructions stored in the program memory 2 and performs a high-speed scanning process. For example, as shown in FIG. 2A, when the sequence instructions A and B are sequentially fetched, the sequence processing dedicated processor 1
As shown in FIG. 2B, data processing of contacts is sequentially performed by itself, and as shown in FIG. 2C, data of addresses A and B specified by the operand of the sequence instruction is data. From the data memory 8 sequentially. Then, operands C, D,
When a data processing instruction having E or a process control processing instruction (hereinafter, referred to as an FNC (C, D, E) instruction) is fetched, the sequence processing dedicated processor 1 causes the FNC (C,
(D, E) instruction is passed to a processor 6 dedicated to data processing or a processor 7 dedicated to process control (hereinafter referred to as an FNC processor), and the FNC
Start the processing processor.

The activated FNC processor is shown in FIG.
As shown in (e), the data of the operands C and D in the FNC (C, D, E) instruction are sequentially read from the data memory 8.
After that, as shown in FIG. 2 (f), the control flag of the data memory 8 of the operand E for writing the processing result is set until the writing of the processing result is completed. After this,
The FNC processor outputs a response signal indicating that the processing request has been received to the sequence processing dedicated processor 1, and starts processing the FNC (C, D, E) instruction.
The sequence processing dedicated processor 1 having received the response signal sequentially fetches new sequence instructions F, G, H... I, E from the program memory 2 again as shown in FIG. In parallel with the sequence processing. When the sequence instruction dedicated processor 1 fetches the sequence instruction E, the control flag of the data memory 8 of the operand E is set to the state shown in FIG.
A wait state is entered as shown in FIG. And FIG.
As shown in (f), when the processing of the FNC processor is completed and the control flag of the data memory 8 of the operand E is reset, the sequence processing dedicated processor 1 is released from the wait state, and the sequence instruction The processing of E is restarted.

As described above, according to this embodiment, when the sequence processing dedicated processor 1 processes a sequence instruction, it checks the control flag of the data memory 8 for the operand of the sequence instruction. Until the same operand appears, processing can be performed in parallel with the data processing dedicated processor 2 and the process control processing dedicated processor 3.

According to the present embodiment, when the sequence processing is performed using the result of the FNC processing, other sequence processing not related to the FNC processing can be performed within the expected FNC processing time. -The effect of the can process on the high-speed scanning operation can be reduced.

FIG. 3A shows a second embodiment according to the second aspect of the present invention. In FIG. 3, a sequence processing dedicated processor 1, a program memory 2, a data memory 3,
The data processing dedicated processor 6 and the process control processing dedicated processor 7 are connected by a common bus 5, respectively. The data processing dedicated processor 6 and the process control processing dedicated processor 7 output monitor signals 6a and 7a, respectively, indicating that processing is being performed, and notify the sequence processing dedicated processor 1. The program memory 2 stores program instructions including a sequence instruction, a data processing instruction, and a process control instruction. Further, when the sequence processing processor 1 is performing the processing in parallel with the processing of the data processing dedicated processor 6 or the process control processing dedicated processor 7, the program instructions include the sequential processing until a predetermined condition is satisfied. It includes a predetermined program instruction for putting the processor dedicated to cans processing 1 into a wait state. FIG. 3B shows an example of the predetermined program instruction.
Instruction (WAIT DP) is a processor 6 dedicated to data processing.
The wait state is set according to the state of the monitor signal output from the processor 7, and the instruction (WAIT PP) in (b) is set to the wait state according to the state of the monitor signal output from the processor 7 dedicated to process control processing.

The operation of this embodiment will be described with reference to a time chart shown in FIG. The sequence processing dedicated processor 1 sequentially fetches the program instructions stored in the program memory 2 to perform high-speed scan processing. For example,
When the sequence instructions A and B are sequentially fetched as shown in FIG.
As shown in FIG. 4B, the data processing of the contacts is sequentially performed by itself, and as shown in FIG. 4C, the data of the addresses A and B specified by the operand of the sequence instruction is data. From the data memory 3 sequentially. Then, operands C, D,
When a data processing instruction having E or a process control instruction (hereinafter, referred to as an FNC (C, D, E) instruction) is fetched, the sequence processing dedicated processor 1 causes the FNC (C,
(D, E) instruction is passed to the data processing dedicated processor 6 or the process control processing dedicated processor 7 (hereinafter referred to as an FNC processing processor), and as shown in FIG.
Start the processing processor. The activated FNC processor immediately outputs (sets) the monitor signal 6a or 7a indicating that the FNC processing is being executed as shown in FIG. 4 (f), and outputs the operand C as shown in FIG. 4 (e). , D, and E, the FNC process is started. Therefore, from this point on, the sequence processing dedicated processor 1 and the FNC processor perform processing in parallel. Subsequently, the processor 1 dedicated to sequence processing
Sequence instructions are sequentially fetched and the data memories of operands F, G, H... I of the instruction are sequentially accessed to perform sequence processing. Here, when the sequence processing dedicated processor 1 fetches a predetermined program instruction (WAIT instruction), the monitor signal 6a or 7
a is checked to determine whether or not the FNC processor is being executed. If the FNC processor is being executed, a wait state is entered. If not, the next program instruction is fetched. FIGS. 4A, 4B, and 4C show an example in which the FNC processing processor is executing and is in a wait state until the FNC processing ends.

When the FNC processing is completed, the FNC processor sets the monitor signal 6a or 7 as shown in FIG.
a is reset, whereby the sequence processing dedicated processor 1 releases the wait state and resumes fetching the program instruction.

According to the present embodiment, by arranging a predetermined program instruction at an appropriate position in a program, the effect of the sequence control on the high-speed scan operation is reduced, and the operand data of the operand data is reduced. The sequence processing and the FNC processing can be executed in parallel without impairing the processing order.

FIG. 5A shows a third embodiment according to the third aspect of the present invention. The hardware configuration of the third embodiment is almost the same as that of the second embodiment, and the data processor 6 and the process control processor 7 are used.
Is different in that no monitor signal is output. The program memory 2 stores program instructions including a sequence instruction, a data processing instruction, and a process control instruction. The program instructions include an interruption instruction for interrupting the execution processing of the data processing dedicated processor 6 or the process control processing exclusive processor 7, and a restart instruction for restarting the interrupted execution processing.

FIG. 5B shows an example of the above-mentioned interrupt instruction and restart instruction. The instruction (a) (STOP DP) interrupts the execution process of the data processing dedicated processor 6, and
The instruction (B) (START DP) restarts the interrupted execution of the processor 6. Instruction of (c) (STOP
PP) interrupts the execution processing of the processor 7 dedicated to process control processing, and the instruction (START PP) of (d) restarts the execution processing of the interrupted processor 7.

The operation of this embodiment will be described with reference to a time chart shown in FIG. The sequence processing dedicated processor 1 sequentially fetches the program instructions stored in the program memory 2 to perform high-speed scan processing. If the fetched instruction is a sequence instruction, the sequence processing dedicated processor 1 performs processing by itself, and the fetched instruction is a data processing instruction or a process control instruction (hereinafter, FNC).
6A, the data processing dedicated processor 6 or the process control processing dedicated processor 7 (hereinafter referred to as an FNC processor) as shown in FIG.
An NC command is passed to make a processing request. As a result, the FNC
The processing processor is activated as shown in FIG. 6B, and starts processing the FNC instruction. From this point, the sequence processing dedicated processor 1 and the FNC processor execute processing in parallel.

If the execution result of the FNC instruction does not affect the operation of the sequence control, the FNC instruction can be executed in parallel with the execution of the sequence instruction. In this case, when executing an important process of the sequence processing dedicated processor 1, an interruption instruction is provided at an arbitrary position in the program to avoid interference from the FNC processor due to malfunction or the like. FIG 6 (a) (b) is to - when executing the scan time T ₀ is longer than the processing time of the FNC processing cans control, interruption instruction to the rear of the scan, and disposed restart command in front of the next scan , F during the scan switching period
This is an example in which the execution of the NC processor is interrupted to ensure the synchronization of the scan.

It goes without saying that the FNC process can be interrupted for a certain period during one scan. According to the present embodiment, the FNC processing with a long processing time unrelated to the sequence control during one scan can be processed in parallel with the sequence processing, and the high-speed scanning operation of the sequence control is secured. be able to.

FIG. 7 shows a fourth embodiment of the present invention. The fourth embodiment is an example of a detailed configuration corresponding to claim 1.
In FIG. 7, when a processor 1 dedicated to sequence processing fetches a data processing instruction or a process control processing instruction, output terminals REQ1 and REQ2 which issue processing requests.
And an input terminal WAIT for determining a wait state. 11 to 13 are OR circuits, 14 and 15 are memory circuits operated by set and reset signals, 16 is a flag latch circuit, and when the sequence processing dedicated processor 1 fetches the sequence instruction, The control flag 8a of the data memory 8 specified by the operand is latched.
17 is an inverting circuit.

In the above configuration, when the sequence processing dedicated processor 1 fetches a data processing instruction or a process control instruction, the output terminal REQ1 or REQ2 is set active and the data processing dedicated processor 6 or the process control processing dedicated processor. 7 is processed. This signal sets the memory circuit 14 via the OR circuit 11, and is input to the WAIT terminal of the sequence processing dedicated processor 1 via the OR circuit 13, and the sequence processing dedicated processor 1 is temporarily in a wait state. After receiving the processing request, the data processing dedicated processor 6 or the process control processing dedicated processor 7 sets the control flag 8a of the data memory 8 in which the processing result of the instruction is written, and then outputs a signal indicating that the processing request has been received. To reset the memory circuit 14 via the OR circuit 12, and release the wait state of the sequence processing dedicated processor 1. From this point,
Cans processing and data processing or process control processing are performed in parallel. Every time the sequence processing dedicated processor 1 fetches an instruction, the control flag 8a of the data memory 8 specified by the operand of the instruction is set to the flag latch circuit 16
Is read by When an instruction having an operand conflicting with the data processing or the process control processing is fetched, the set control flag 8a is read into the flag latch circuit 16, the memory circuit 15 is set, and the control circuit 8 is set via the OR circuit 13. -Put the processor 1 dedicated to can processing in the wait state. When the data processing or the process control processing ends, the control flag is reset and the wait state of the sequence processing dedicated processor 1 is released. According to this embodiment, the same effects as in the first embodiment can be obtained by adding simple hardware.

[0025]

According to the present invention, the sequence control and the data
In a programmable controller that performs integrated processing of data processing and process control processing, it is possible to provide a programmable controller that ensures a high-speed scan operation of sequence control and enables a large-capacity program.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment corresponding to claim 1 of the present invention.

FIG. 2 is a time chart for explaining the operation of the first embodiment.

FIGS. 3A and 3B show a second embodiment according to the second aspect of the present invention, wherein FIG. 3A is a hardware configuration diagram, and FIG.

FIG. 4 is a time chart for explaining the operation of the second embodiment.

FIGS. 5A and 5B show a third embodiment corresponding to claim 3 of the present invention, wherein FIG. 5A is a hardware configuration diagram, and FIG. 5B is a diagram showing an interrupt instruction and a restart instruction.

FIG. 6 is a time chart for explaining the operation of the third embodiment.

FIG. 7 is a detailed configuration diagram of a fourth embodiment corresponding to claim 1 of the present invention.

8A and 8B show a conventional programmable controller, in which FIG. 8A is a configuration diagram, and FIG. 8B is a time chart for explaining its operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Processor dedicated to sequence processing 2 ... Program memory 3 ... Data memory 5 ... Bus 6 ... Processor dedicated to data processing 7 ... Processor dedicated to process control processing 8 ... Data memory (including control flags) 11-13 ... OR circuit 14, 15… Memory circuit 16… Flag latch circuit 17… Inverting circuit

Claims (3)

(57) [Claims] 1. A sequence for sequentially reading out program instructions stored in a program memory and executing a sequence process.
In a programmable controller having a sequence processing processor, the program instructions include a sequence instruction, a data processing instruction and a process control instruction, and the data processing processor executes the data processing instruction; A process control processor for executing a process control instruction; and a data memory for storing data addressed by an operand of the program instruction and a control flag in a pair, wherein the data processor or the process control processor includes: During execution of the data processing instruction or the process control instruction, the control flag of the address specified by the operand of the data processing instruction or the process control instruction is set, and the data processing instruction or the process control instruction is executed in parallel. The sequence processor that executes the sequence instruction When the address control flags that are specified by the operand of the cans instruction is set, - the cans treated programmable controller processor is characterized in that a means for the waiting state - la. 2. A sequence for sequentially reading out program instructions stored in a program memory and executing a sequence process.
In a programmable controller having a sequence processing processor, the program instructions include a sequence instruction, a data processing instruction and a process control instruction, and the data processing processor executes the data processing instruction; A process control processor for executing a process control instruction; and a means for outputting a monitor signal indicating that the data processor or the process control processor is executing the data processing instruction or the process control instruction. When a sequence processor executing a sequence instruction in parallel with data processing or process control processing executes a predetermined program instruction, the sequence processor is controlled according to the state of the monitor signal. A programmable controller characterized in that a means for setting a standby state is provided. 3. A sequence for sequentially reading out program instructions stored in a program memory and executing a sequence process.
In a programmable controller having a sequence processing processor, the program instructions include a sequence instruction, a data processing instruction and a process control instruction, and the data processing processor executes the data processing instruction; A process control processor for executing a process control instruction, wherein the program instruction further includes an interrupt instruction for interrupting the execution of the data processor or the process control processor, and a restart for restarting the interrupted execution. When the sequence processor including the instruction and executing the sequence instruction in parallel with the data processing or the process control processing reads the interrupt instruction, the sequence processor interrupts the data processing or the process control processing. When the restart instruction is read out, the data processing or the process interrupted is read. La - programmable controller, characterized in that a means for resuming the control process.