JP3189493B2 - Character symbol generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television camera and a VTR.
The present invention relates to a character / symbol generator used when displaying characters and the like on a plurality of screens.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a schematic configuration of a conventional character / symbol generator. In FIG. 6, a RAM (R) storing codes of characters and symbols to be displayed is stored.
output of the random access memory)
When one system is given as the address 46 of the OM (Read Only Memory) 47, the corresponding display character data 49 is output via the output buffer 48 in one system.

As described above, the conventional character / symbol generator can output one character / symbol data for display by giving one ROM address.

[0004]

While however with [SUMMARY OF THE INVENTION], the above conventional character symbol generator in ROM and the output buffer is one system, and to work with the same driving pulse, respectively the synchronization of different screens characters In order to display a symbol, there is a problem that a plurality of character / symbol generators operating with respective synchronization signals are required.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide an excellent character / symbol generator capable of outputting character / symbols to a plurality of screens having different synchronizations in one ROM. I do.

[0006] In addition, the above-mentioned conventional character symbol generator R
Since the OM and the output buffer are one system, a plurality of character / symbol generators are required to display different character / symbols on each screen even if the screens are synchronized. Had.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide an excellent character / symbol generating device capable of outputting a plurality of character codes of different synchronizations with one ROM.

[0008]

Letter symbol generator of the present invention to achieve the above Symbol purposes SUMMARY OF THE INVENTION, at least one of RO
M and address pallets arranged in parallel in front of the ROM.
ROM address latches driven by
An address for driving each of the plurality of ROM address latches.
Determine whether the time positions of the dress pulses overlap,
A phase determining unit that outputs a result of the determination;
Multiplexers arranged in parallel at the subsequent stage and driven by data pulses
Number of ROM data latches and the address pulse and
A selector to which the data pulse is inputted,
The phase determination unit is configured to output the plurality of ROM addresses
The time between address pulses driving each of the latches
If the result of the judgment that the positions do not overlap is output,
The address pulse input and the data input
The pulse is applied to the ROM address latch and the R
Output to the OM data latch, and the phase determination unit
An address for driving each of the plurality of ROM address latches.
The result of the determination that the time positions of the dress pulses overlap
When output, delay of the input address pulse
Pulse and a delayed pulse of the input data pulse
ROM address latch and ROM data latch
Output to the ROM and a plurality of
It has a configuration for outputting character symbols on the surface .

[0009]

[0010]

[Action]

(Claim 1) With the above configuration, a plurality of R
The phase (time position) of the OM address is determined, and the address pulse and the data pulse are selected by the selector so as to operate with the address pulse and the data pulse having different phases for a plurality of accesses to the ROM based on the result, and the latch is performed. By performing parallel-to-serial conversion on the selected ROM data with the selected data pulses, a single ROM can output character symbols to a plurality of screens having different synchronizations.

[0011]

[0012]

【Example】

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of a first embodiment of the character / symbol output device of the present invention, and FIG. 2 is a time chart thereof.

In FIG. 1, 1 and 2 are ROM addresses, which are input to address latches 3 and 4, respectively. Reference numeral 23 denotes a phase determination unit that determines the phases of the address position pulse A21 and the address position pulse B22.
4 is being driven. The output of the selector 24 selects either the address pulse B6a or its delayed address pulse B6b, and is input to the address latch B4. The switching signal generator 25 selects one of the address latches 3 and 4, and one of them is connected to the ROM 8 via the address selector 7. The output of the ROM 8 is input to a data latch A9 and a data latch B10. The data latch B10 has a data pulse B12a and its delayed data pulse B12b.
Is connected to the output of the selector 24 for selecting either one of the above. The data latch B10 and the data latch A9 are connected to a parallel-serial converter B14 and a parallel-serial converter A13, respectively, and output a serial output A19 and a serial output B20 as display data, respectively.

Next, the operation of the first embodiment will be described with reference to FIG.
This will be described with reference to FIG. In FIG. 1, the phases of the address position pulse A21 and the address position pulse B22 are determined by the phase determination unit 23, and the selector 24 supplies a pulse to the address latch B4 so that the address pulse B6a and the delayed address pulse B6b do not overlap.
For example, when the address position pulses 21 and 22 overlap as shown in FIG.
6b and the delayed data pulse B12b. Further, the address latch A3 and the address latch B are generated by the switching signal 26 as shown in FIG.
The address A1 and the address B2 fetched in step 4 are sequentially selected by the address selector 7 to access the ROM 8.

The data of the ROM 8 is sequentially latched by the data latches A9 and B10 by the data pulses 11 and 12a as shown in FIG. 2, and the parallel pulses 15 and 1 shown in FIG.
6 is converted to parallel / serial, and serial clock 1 with different synchronization
7 and 18, the serial output A19 is output from the parallel / serial converter A13 and the parallel / serial converter B14 as character / symbol data.
And a serial output B20. As described above, according to the first embodiment, since one ROM is sequentially accessed by the address latches A3 and B4 and the data latches A9 and B10, the serial output A19 and the serial output B20 and two systems of character symbols can be output.

FIG. 3 is a diagram showing a circuit example of the phase determining section 23. In the drawing, reference numeral 28 denotes an AND gate circuit,
9 is a flip-flop circuit, and 30 is an inverter circuit.

(Embodiment 2) FIG. 4 is a block diagram showing a configuration of a second embodiment, and FIG. 5 is a time chart thereof.

In FIG. 4, reference numeral 32 denotes an address latch for latching an address 31, which is connected to the ROM 34. A data latch 35 connected to the output of the ROM 34,
36, and the parallel-to-serial converters 39 and 40 are the same as those in the first embodiment, and thus will not be described.

Next, the operation of the second embodiment will be described with reference to FIGS. In FIG. 4, the address 31 is fetched at the timing of the address pulse 33 of FIG.

As shown in FIG. 5, the data in the ROM 34 is sequentially fetched into the data latches 35 and 36 by a data pulse A37 and a data pulse B38 corresponding to the address pulse 33.
Hereinafter, the same operation as in the first embodiment is performed, and the parallel / serial converter 39 is used.
And 40, two characters are output as a serial output A43 and a serial output B44.

As described above, according to the second embodiment, two addresses are sequentially fetched into the address latch 32 by the address pulse 33 shifted in advance in time, and the ROMs are respectively stored in the two data latches 35 and 36.
34 data can be latched, so that one R
OM can output different character symbols to two screens synchronized with each other.

In the first and second embodiments, the data latch A9, data latch B10, data latch A3
5, the data latch B36 is provided, but the serial clock A17, the serial clock B18, and the serial clock 42 are shifted from the positions of the parallel pulses 15, 16, 41 to the serial clock 45 in FIG. These data latches may be omitted by giving the signals in such a delayed manner. In this case, the data latch can be omitted, so that in addition to the above advantage that different character symbols can be output to two screens with one ROM, the circuit can be simplified.

[0023]

As described above, the present invention has the following effects.

At least one ROM, and the ROM
It is arranged in parallel at the previous stage and driven by the address pulse
A plurality of ROM address latches and the plurality of ROM addresses;
Address pulses that drive each of the
Determines whether the time positions overlap and outputs the result of this determination.
And a phase judging unit to be applied,
ROM data drives driven by data pulses
Switch and the address pulse and the data pulse are input.
And a selector for inputting the phase.
The determining unit stores each of the plurality of ROM address latches.
If the time positions of the driving address pulses do not overlap,
When the result of the judgment of
Pulse and the input data pulse immediately before
The ROM address latch and the ROM data latch
And the phase determination unit outputs the plurality of ROM addresses.
Address pulses that drive each of the
When the result of the judgment that the time position overlaps is output,
And a delay pulse of the address pulse
The delay pulse of the data pulse to the ROM address
Output to the latch and the ROM data latch,
Output character symbols on multiple screens with different synchronization in the ROM
By providing a structure for the input at any time
More than one ROM address latch from the given address pulse
Can be accessed one ROM at a time.
From this ROM with any different data pulse
Generating multiple character symbols sequentially from data latches
An excellent character / symbol generation device capable of performing the above-described operations can be realized.

[0025]

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a character / symbol generating device according to a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the character / symbol generator in the first embodiment of the present invention.

FIG. 3 is a circuit connection diagram showing a circuit example of a phase determination unit of the character / symbol generator according to the first embodiment of the present invention.

FIG. 4 is a schematic block diagram of a character / symbol generator according to a second embodiment of the present invention;

FIG. 5 is a time chart for explaining the operation of the character / symbol generator in the second embodiment of the present invention.

FIG. 6 is a schematic block diagram of a conventional character / symbol generator.

[Explanation of symbols]

 3 Address Latch A (ROM Address Latch) 4 Address Latch B (ROM Address Latch) 8 ROM 9 Data Latch A (ROM Data Latch) 10 Data Latch B (ROM Data Latch) 13 Parallel / Serial Converter A 14 Parallel / Serial Converter B 23 phase determination unit 24 selector 25 switching signal generation unit

Claims (1)

(57) [Claims] At least one ROM, said ROM
Are arranged in parallel at the preceding stage and are driven by address pulses.
A plurality of ROM address latch that, said plurality of ROM A
Address pulses that drive each of the dress latches
It is determined whether or not the time positions overlap, and the result of this determination is
Output phase judging unit, placed in parallel after the ROM
ROM data driven by data pulses
A latch, the address pulse and the data pulse
And a selector to be inputted, wherein the selector is
A phase determination unit configured to control each of the plurality of ROM address latches;
Time positions of address pulses that drive
When the result of the judgment is output,
Pulse and the input data pulse as they are
ROM address latch and ROM data latch
Output to the plurality of ROM addresses.
Address pulses that drive each of the dress latches
When the result of the judgment that the time positions of
The delay pulse of the address pulse to be input and the input pulse
The delay pulse of the data pulse is stored in the ROM address.
Output to the latch and the ROM data latch
Te, character symbol generator for outputting a character symbol synchronization of a plurality of different screens in the ROM.