JP3162018U - Power semiconductor lead frame - Google Patents

Abstract

A lead frame capable of realizing a high-reliability and low-cost packaging technology for a power semiconductor such as SiC or GaN is provided. A source lead having a joined body to a source electrode of a vertical FET mounted on a heat sink, a gate lead having a joined body to a gate electrode, and a drain lead having a joined body to a heat sink are tie bars. The leads are extended from the tie bar and bent downward in the order of the drain lead, the source lead, and the gate lead, and the respective joined bodies are arranged at the tips extending downward. It has a structure. The drain lead joined body is rectangular, the source lead joined body is a rectangle having a rectangular opening at the center, the gate lead joined body is an elongated rectangle, and the gate lead joined body is a rectangular opening of the source lead. Located in. [Selection] Figure 1

Description

  The present invention relates to a lead frame for power semiconductors.

  SiC and GaN power semiconductors (Diode and MOS FET) do not deteriorate in characteristics even at high temperatures, and have a higher breakdown voltage and can operate at higher power than Si power semiconductors. . Specifically, it has been studied to operate the FET at a channel temperature of 200 ° C. or higher. However, various problems arise in such power semiconductor packaging (semiconductor assembly into a package). FIG. 8 shows a semiconductor resin-encapsulated package, and FIG. 7 shows its lead frame (Patent Document 1). Since conventional epoxy resin molds cannot be used in high temperature operation, high heat resistant resins have been actively developed in recent years. The bonding wire 22 shown in FIG. 8 normally uses an Al thick wire in a power semiconductor, but the loss is not negligible because it becomes longer in the space wiring. Therefore, a method of directly joining the lead to the power semiconductor electrode is also employed. Further, although the power semiconductor is mounted on the heat radiating plate 16, a mounting material for withstanding high temperature / high current operation has not been found at present. Alloy solders with high eutectic temperatures such as AuGe and AuSi are candidates, but vertical FETs can be mounted by migration because a large current flows from the source electrode formed on the chip surface to the drain electrode on the back side of the chip. The problem is that voids are generated in the bonding layer. This is because alloys generally have low migration resistance. Note that vertical FETs include JFETs and MOS FETs, which are generally called vertical FETs.

  On the other hand, Patent Document 2 discloses a technique in which metal nanoparticles are dispersed in a solvent to form a slurry on a metal plate, and the bonded plate is heated and pressurized. For example, when a Cu plate is heated and pressure bonded using a slurry of Cu nanoparticles as a bonding material, the bonding layer becomes bulky, so it can be easily conceived that the migration resistance is significantly improved as compared with the alloy. However, it takes 5 to 10 minutes for the metal nanoparticles to progress to the bulk, and the low process throughput is a bottleneck to cost reduction.

  FIG. 7 shows a conventional lead frame of a general power semiconductor, and the lead frame including the heat sink 16 is called a lead frame. However, as the performance of semiconductors increases, various technical problems arise as described above when it is required to use them under severer operating conditions. Since it is necessary to take individual measures, the lead frame of the present invention does not include a heat sink.

JP-A-5-243358 JP2007-44764

  The packaging of SiC and GaN power semiconductors, which can be expected to operate at high temperature and high power, has various technical problems due to its severe operating conditions, but due to its merit, much research and development has been promoted. Yes. Highly reliable and low-cost packaging technology is an issue.

  In order to solve the above problems, in the present invention, a source lead having a joined body to a source electrode of a vertical FET mounted on a heat sink, a gate lead having a joined body to a gate electrode, and a joint to the heat sink A drain lead having a body is connected in parallel by a tie bar, and each lead extends from the tie bar and bends downward in the order of a drain lead, a source lead, and a gate lead. In the lead frame having a structure arranged at the extended tip, the joined body of the drain lead is a rectangle, the joined body of the source lead is a rectangle having a rectangular opening at the center, and the joined body of the gate lead Is an elongated rectangle, and the joined body of the gate lead is located in the rectangular opening of the source lead.

  An object of the present invention is to use metal nanoparticles as a bonding material, to mount a vertical FET on a heat sink, and to join a lead to an FET and a heat sink at the same time.

The figure which shows the lead frame of this invention External view of vertical FET (A) (B) Figure of the lead frame of the present invention joined to a vertical FET and a heat sink The figure which shows an example of an assembly using the lead frame of this invention The figure which shows an example of an assembly using the lead frame of this invention Diagram of resin-encapsulated FET The figure which shows the lead frame which implements this invention Figure showing a conventional lead frame Conventional resin-encapsulated semiconductor devices

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a lead frame 1 of the present invention. As a structure of the lead frame 1, a source lead 2, a drain lead 3, and a gate lead 4 are connected and held by a tie bar 5. After the source lead 2 extends to an appropriate length, the source lead 2 is appropriately bent to approach the size of the semiconductor chip, and bent downward to attach the joined body 10. The extension, bending, and bending of the lead must be adjusted so that the joint 11 of the gate lead 4 comes near the center of the joint 10 of the source lead. Since the joined body 9 of the drain lead 3 is used for joining to a heat radiating plate (18 in FIG. 3) having a large area, it may be attached to the bent end, and the height position of the joined body 9 is the joined body of the source lead. The position is determined downward with respect to the joined body 11 of 10 and the gate lead. The source lead joined body 10 and the gate lead joined body are at the same height. The arrangement of the source lead, drain lead, and gate lead is not particularly limited.

  Two typical electrode patterns of a vertical FET are shown in FIG. There are only two types, a rectangular gate electrode 13 positioned at the end of the source electrode 14 or placed at the center. The back surface of the chip becomes the drain electrode 15. Therefore, as shown in FIG. 3, the shape and the positional relationship between the source lead joined body 10 and the gate lead joined body 11 joined to the source electrode and the gate electrode of the vertical FET are determined. That is, the source lead joined body 10 may be a rectangle having a rectangular opening at the center, and the gate lead joined body 11 may be an elongated rectangle so as to be within the rectangular opening of the source lead. FIG. 3 shows a case where the present invention is applied to the vertical FET shown in FIG. Similarly, FIG. 5 shows a state of junction with respect to the vertical FET shown in FIG. Although there is some shape change, if the shape and positional relationship are almost the same, the junction to the vertical FET is possible. The bonding materials 17 and 18 are obtained by forming a slurry by dispersing metal nanoparticles in a solvent and forming a slurry on a heat sink. Although a thin film is also formed on the back surfaces of the source lead joined body 10 and the gate lead joined body 11, they are not shown. In the case of FIG. 4, since the gate lead assembly 11 comes on the source electrode of the vertical FETFET, it is safe to previously form an insulating film such as polyimide resin in the contact region of the source electrode in order to avoid contact. It is. The metal particles include Au, Ag, and Cu, but are not particularly limited.

  An image of assembly using the lead frame of the present invention is shown in FIG. As shown in the figure, by pressing with a heating / pressurizing jig 19, the joined body of the source lead and the gate lead is joined to the electrode of the vertical FET, and at the same time, the vertical FET is joined (mounted) to the heat sink. At the same time, the drain lead joined body 9 is joined to the heat sink 16. The metal nanoparticles are said to be bulked when the metal particles begin to bond to each other by heating and pressing. The temperature at this time is characterized by a low temperature of 300 ° C. or less, but the time required for the assembly process is low because it takes 5 to 10 minutes. The shape of the joint of the source lead and gate lead of the present invention is devised so that the heating / pressurization conditions of the vertical FET / lead joint and the mount part are not significantly different. It was devised so that the low throughput is not reflected in the cost by carrying out collectively. Since the drain lead is joined using spring property, there is a possibility that the pressure condition for the semiconductor may be changed. However, the spring property can be designed to bring the condition closer.

  After the assembly of the lead frame, the heat sink, and the vertical FET is completed, a resin mold 20 is formed as shown in FIG. 6 to complete a semiconductor mold package. FIG. 7 shows a multiple lead frame that has been described as a unit for convenience of description. Since multiple lead frames are used in manufacturing, the coating film of the bonding material is formed at the required location, the positioning and temporary fixing (Pick & Place) of the MOS FET to the lead bonded body, and precise treatment for heating and pressing. It is necessary to examine the tools (devices).

  A Cu—Fe alloy is used for the material of the lead frame and the heat sink, but is not particularly limited. As described above, since the drain lead is joined to the heat radiating plate using the spring property, a highly elastic Cu—Sn alloy can also be used. In order to make the effect of the present invention more effective, it is also necessary to change the material between the lead frame and the heat sink. The lead frame and the heat radiating plate are usually plated with metal, but the plated metal needs to be matched to the metal nanoparticles used. For example, when Au nanoparticles are used as the bonding material, the lead frame and the heat sink form an Au film by plating.

  When the lead frame of the present invention is used, a low-cost and highly reliable packaging technology for a power semiconductor using a high-performance crystal such as SiC or GaN can be realized.

DESCRIPTION OF SYMBOLS 1 Lead frame 2 Source lead 3 Drain lead 4 Gate lead 5 Tie bar 6 Source bent part 7 Drain bent part 8 Gate bent part 9 Drain lead joined body 10 Source lead joined body 11 Gate lead joined body 12 Vertical type FET
13 Gate electrode 14 Source electrode 15 Drain electrode 16 Heat radiation plate 17, 18 Metal nanoparticle bonding material 19 Pressure / heating jig 20 Mold resin 21 Lead 22 Bonding wire 23 Semiconductor

Claims (1)

  A source lead having a junction to the source electrode of a vertical FET mounted on the heat sink, a gate lead having a junction to the gate electrode, and a drain lead having a junction to the heat sink are connected in parallel by a tie bar. Each lead extends from the tie bar and bends downward in the order of the rear drain lead, source lead, and gate lead, and each joined body has a structure that is disposed at the tip extending downward. In the lead frame, the drain lead joined body is a rectangle, the source lead joined body is a rectangle having a rectangular opening in the center, the gate lead joined body is an elongated rectangle, and the gate lead joined A lead frame, wherein the body is located within a rectangular opening of the source lead.

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