CN116013891A - Packaging structure, packaging method and electronic equipment - Google Patents

Abstract

The application provides a packaging structure, a packaging method and electronic equipment. The package structure in the embodiment of the application comprises a substrate and a chip arranged on the substrate; the first RDL bonding pad is arranged on one side of the chip far away from the substrate; at least one first bonding wire, a first end of the first bonding wire is welded with the first RDL pad, and a second end of the first bonding wire is welded with at least one pin on the substrate.

Description

Packaging structure, packaging method and electronic equipment

Technical Field

The application belongs to the technical field of semiconductors, and particularly relates to a packaging structure, a packaging method and electronic equipment.

Background

The chip is one of core components in the electronic device, and with the gradual increase of functions of the electronic device, the integration level of the chip is also higher, and in related technology, the chip is mainly packaged by a Quad Flat No-leads Package (QFN) technology.

In a conventional chip package structure, a pad is provided at an edge of a chip, and the pad is electrically connected to a lead of a substrate through a bonding wire. However, the material of the bonding pad is usually aluminum, and the area of the bonding pad is limited by the wafer size of the chip, which can compress the effective space utilization of the chip wafer if the area of the bonding pad is too large; and because of the small area of the bonding pad, only one bonding wire with small size can be welded on one bonding pad.

In summary, in the conventional chip packaging technology, the pad area of the pad is limited by the wafer size of the chip, and one pad can only be soldered with one bonding wire.

Disclosure of Invention

An object of the embodiment of the present application is to provide a packaging structure, a packaging method, and an electronic device, where a pad area of an RDL pad in the packaging structure is not limited to a wafer size of a chip, and the RDL pad may be soldered with a plurality of bonding wires.

In order to solve the technical problems, the application is realized as follows:

in a first aspect, an embodiment of the present application provides a package structure, including:

a substrate, and a chip disposed on the substrate;

the first RDL bonding pad is arranged on one side of the chip far away from the substrate;

and the first end of the first bonding wire is welded with the first RDL bonding pad, and the second end of the first bonding wire is welded with at least one pin on the substrate.

In a second aspect, embodiments of the present application provide an electronic device, which includes the package structure as described in the first aspect.

In a third aspect, an embodiment of the present application provides a packaging method, including:

arranging a chip on a substrate;

a first RDL bonding pad is arranged on one side of the chip far away from the substrate;

and arranging a first end of a first bonding wire to be welded with the first RDL bonding pad, and arranging a second end of the first bonding wire to be welded with at least one pin on the substrate.

The package structure in the embodiment of the application comprises a substrate and a chip arranged on the substrate; the first RDL bonding pad is arranged on one side of the chip far away from the substrate; at least one first bonding wire, a first end of the first bonding wire is welded with the first RDL pad, and a second end of the first bonding wire is welded with at least one pin on the substrate. The package structure provided in the embodiment of the present application only defines the position of the RDL pad, that is, the RDL pad is disposed on the side of the chip far away from the substrate, and the size relationship between the area of the RDL pad and the wafer size of the chip is not limited, that is, the pad area of the RDL pad in the package structure is not limited by the wafer size of the chip. In the embodiment of the application, the RDL bonding pad is used for replacing the traditional aluminum bonding pad, so that the spring pit effect caused by overlarge bonding force between the bonding pad and the bonding wire is avoided, and the bonding property between the bonding pad and the bonding wire is prevented from being deteriorated; and the RDL bonding pad can be welded with a plurality of bonding wires on the basis of effective space utilization without compressing the area of the wafer.

Drawings

FIG. 1 is a cross-sectional view of a package structure provided by some embodiments of the present application;

FIG. 2 is a top view of a package structure provided by some embodiments of the present application;

FIG. 3 is a partial cross-sectional view of a package structure provided by some embodiments of the present application;

FIG. 4 is a partial cross-sectional view of a package structure provided by some embodiments of the present application;

FIG. 5 is a partial cross-sectional view of a package structure provided by some embodiments of the present application;

fig. 6 is a flow chart of a packaging method provided by some embodiments of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

Referring to fig. 1 and 2, fig. 1 is a cross-sectional view of a package structure provided in some embodiments of the present application, and fig. 2 is a top view of the package structure provided in embodiments of the present application. The package structure shown in fig. 1 and 2 includes a substrate 10, and a chip 20 disposed on the substrate 10;

a first RDL pad 30, the first RDL pad 30 being disposed on a side of the chip 20 remote from the substrate 10;

at least one first bonding wire 40, a first end of the first bonding wire 40 is soldered to the first RDL pad 30, and a second end of the first bonding wire 40 is soldered to at least one lead on the substrate 10.

In some embodiments of the present application, the chip 20 is disposed on the substrate 10, and a side of the chip 20 away from the substrate 10 is provided with the first RDL pad 30. Alternatively, a plurality of first RDL pads 30 may be provided on a side of the chip 20 remote from the substrate 10. Alternatively, a redistribution layer (Redistribution Layer, RDL) structure may be disposed on the surface of the chip 20 by using an electroplating process to form the first RDL pad 30, and it should be understood that a copper pillar connection function commonly used in a semiconductor packaging (bumping) process may be implemented by disposing the RDL structure, and in addition, the RDL structure may also implement a pad function. The pad area of the first RDL pad 30 may be flexibly set, not limited by the wafer size of the chip 20, and the position of the first RDL pad 30 on the chip 20 may also be flexibly set.

Some embodiments of the present application provide a package structure further including at least one first bonding wire 40, where a first end of the first bonding wire 40 is disposed to be soldered to the first RDL pad, and optionally, wire bonding may be performed on each first RDL pad 30 disposed on the surface of the chip 20, and each first RDL pad 30 is disposed to be soldered to at least one first bonding wire 40. And the at least one first bonding wire 40 is further soldered to the at least one lead 11 on the substrate 10, so as to electrically connect the chip 20 and the substrate 10.

For ease of understanding, referring to fig. 2, as can be seen from a top view of the package structure, a first RDL pad 30 may be soldered with a first bond wire 40; one first RDL pad 30 may also be soldered with three first bond wires 40, and the three first bond wires 40 are soldered with one lead 11 on the substrate 10; one first RDL pad 30 may also be soldered with four first bond wires 40, and the four first bond wires 40 are soldered with two leads 11 on the substrate 10.

The package structure provided in this embodiment of the present application only defines the position of the RDL pad, that is, the RDL pad is disposed on the side of the chip 20 away from the substrate 10, and does not limit the size relationship between the area of the RDL pad and the wafer size of the chip 20, that is, the pad area of the RDL pad in the above package structure is not limited to the wafer size of the chip. The traditional chip bonding pad is usually an aluminum bonding pad, the bonding wire is usually a copper wire or a gold wire, when the bonding wire is a copper wire, the bonding wire can be bonded due to the fact that the copper wire is hard and easy to oxidize, but the aluminum bonding pad is softer, and a 'spring pit' effect can be formed due to improper parameter control (namely, damage occurs to metal in the inner layer of the chip due to overlarge bonding force); when the bonding wire is a gold wire, since aluminum atoms easily react with gold atoms to form brittle intermetallic compounds (InterMetalliC, IMC), IMC becomes thicker and thicker with increasing temperature and bonding time, and solder joint bondability becomes poor. In the embodiment of the application, the RDL bonding pad is used for replacing a traditional aluminum bonding pad, so that the spring pit effect caused by overlarge bonding force between the bonding pad and the bonding wire is avoided, and the bonding property between the bonding pad and the bonding wire is prevented from being deteriorated. Conventional aluminum bonding pads can only be used for bonding a plurality of bonding wires, if the effective space utilization rate of the wafer area is reduced by increasing the size of the bonding pad, the RDL bonding pad in the embodiment of the application can be bonded with a plurality of bonding wires on the basis of the effective space utilization rate without reducing the wafer area.

Optionally, a side of the chip 20 away from the substrate 10 includes a chip pad 21 and a passivation layer 22, and the package structure further includes a buffer layer 60; the buffer layer 60 is disposed on the passivation layer 22, and the buffer layer 60 is disposed between the first RDL pad 30 and the passivation layer 22. In some embodiments of the present application, a buffer layer 60 may be disposed between the chip 20 and the RDL pad, and optionally, the material of the buffer layer 60 is Polyimide (PI), and the buffer layer 60 may be referred to as a PI layer.

Referring to fig. 3, as shown in fig. 3, a side of the chip 20 away from the substrate 10 includes a chip pad 21 and a passivation layer 22, and optionally, the chip pad 21 is an aluminum pad. The buffer layer 60 is disposed on the surface of the passivation layer 22 to expose the chip pad 21, and the first RDL pad 30 is disposed on a side of the buffer layer 60 away from the substrate 10 and a side of the chip pad 21 away from the substrate 10 through an electroplating process.

In some embodiments of the present application, by providing a buffer layer 60 between the chip 20 and the RDL pad, a stress buffering effect is achieved, avoiding damage to the chip 20 during the packaging process.

Alternatively, the thickness of the buffer layer 60 is greater than or equal to 5 μm and less than or equal to 10 μm.

In some embodiments of the present application, the thickness of the buffer layer 60 is greater than or equal to 5 μm and less than or equal to 10 μm, and the buffer layer 60 can play a role of stress buffering, so as to avoid the chip 20 from being damaged in the packaging process.

Optionally, the package structure further includes a metal layer 70; the metal layer 70 is disposed on a side of the first RDL pad 30 away from the substrate 10, and a bonding portion for bonding the first bonding wire 40 and the first RDL pad 30 is disposed on the metal layer 70.

Referring to fig. 4, in some embodiments of the present application, a metal layer 70 may be disposed on a side of the first RDL pad 30 away from the substrate 10 by electroplating, chemical plating or sputtering, and a bonding portion between the first bonding wire 40 and the first RDL pad 30 is disposed on the metal layer 70, that is, the bonding between the first bonding wire 40 and the first RDL pad 30 is achieved by bonding the bonding portion.

In some embodiments of the present application, by providing the metal layer 70 on the side of the RDL pad remote from the substrate 10, the metal layer 70 serves to increase the bonding force between the bond wire and the RDL pad.

Alternatively, the thickness of the metal layer 70 is greater than or equal to 0.5 μm and less than or equal to 3 μm.

Alternatively, the material of the metal layer 70 may be nickel (Ni), palladium (Pd) or gold (Au). If the material of the metal layer 70 is Ni, the thickness of the metal layer 70 may be set to a value ranging from 1.0 μm to 3.0 μm; if the material of the metal layer 70 is Pd, the thickness of the metal layer 70 may be set to a value ranging from 0.5 μm to 1.0 μm; if the metal layer 70 is made of Au, the thickness of the metal layer 70 may be set to a value ranging from 0.5 μm to 1.0 μm.

In some embodiments of the present application, the thickness of the metal layer 70 is greater than or equal to 0.5 μm and less than or equal to 3 μm, which can play a role of stress buffering, so as to avoid the chip 20 from being damaged during the packaging process.

Optionally, the package structure further includes a plastic package 50; the substrate 10, the chip 20, the first RDL pad 30, and the at least one first bonding wire 40 are all encapsulated within the encapsulation 50.

Referring to fig. 1 and 2, in some embodiments of the present application, the substrate 10, the chip 20, the first RDL pad 30 and the first bonding wire 40 are encapsulated, so that the substrate 10, the chip 20, the first RDL pad 30 and the first bonding wire 40 are encapsulated in the encapsulation 50, thereby forming the encapsulation structure of the chip 20.

Optionally, the package structure further includes a second RDL pad 80 and at least one second bond wire 90;

the second RDL pad 80 is disposed on a side of the chip 20 remote from the substrate 10, and the second RDL pad 80 is soldered to a first end of the second bond wire 90.

In some embodiments of the present application, the package structure further includes a second RDL pad 80 and a second bond wire 90. Alternatively, a layer of RDL structure may be disposed on the surface of the chip 20 by using an electroplating process to form the second RDL pad 80, where the pad area and position of the second RDL pad 80 may be flexibly adjusted.

In some embodiments of the present application, the second RDL pad 80 disposed on the surface of the chip 20 may be bonded by a vertical wire bonding process to provide for the second RDL pad 80 to be soldered to a first end of at least one second bond wire 90.

For ease of understanding, referring to fig. 2, the second RDL pad 80 is soldered with 9 second bond wires 90 from a top view of the package structure.

In some embodiments of the present application, the second RDL pad 80 is disposed on a side of the chip 20 away from the substrate 10, and the second RDL pad 80 is welded with the second bonding wire 90, so that the second bonding wire 90 is used as a heat conducting structure to radiate heat of the chip 20 to the outer surface of the package structure, thereby improving the heat dissipation effect.

Optionally, the diameter of the second bond wire 90 is greater than the diameter of the first bond wire 40.

Referring to fig. 1, 2 and 5, the diameter of the second bonding wire 90 is larger than that of the first bonding wire 40, so as to dissipate heat from the chip 20. Generally, after bonding between the second RDL pad 80 and the second bonding wire 90 is completed through a vertical wire bonding process, bonding between the first RDL pad 30 and the first bonding wire 40 is completed through a wire bonding process.

As described above, the first bond wire 40 is soldered 30 to the first RDL pad by a conventional wire bonding process and the second bond wire 90 is soldered 80 to the second RDL pad by a perpendicular wire bonding process. The traditional packaging structure mainly dissipates heat through a frame at the bottom of the chip 20, and has limited heat dissipation effect; in some embodiments of the present application, the second RDL pad 80 and the second bonding wire 90 are welded through a vertical wire bonding process, and the diameter of the second bonding wire 90 applying the vertical wire bonding process is set to be larger than that of the first bonding wire 40 applying the conventional wire bonding process, and the heat on the surface of the chip 20 is directly transferred to the surface of the chip 20 through the second bonding wire 90, so that heat dissipation is increased, a manner that the conventional package structure dissipates heat by relying on the bottom frame of the chip 20 is improved, and heat dissipation efficiency is improved.

In addition, the gap between adjacent bonding wires in the packaging structure is larger than or equal to the diameter of any bonding wire in the adjacent bonding wires, so that short circuit is avoided.

Optionally, the second RDL pad 80 is disposed in a central area of the chip 20, and the first RDL pad 30 is disposed in an edge area of the chip 20.

It should be understood that the central region is symmetrical about the center point of the chip 20, and if the chip 20 is rectangular, the central region of the chip 20 is symmetrical about the center point of the rectangle. And the area of the central region of the die 20 does not exceed the area of the wafer comprised by the die 20.

The edge region includes the edge of the chip 20, and there is no overlap between the edge region of the chip 20 and the center region of the chip 20. If the chip 20 is rectangular, the edge regions of the chip 20 include rectangular sides.

Illustratively, as shown in FIG. 2, the second RDL pad 80 may be disposed at a center location of the chip 20, i.e., a center region of the chip 20; the first RDL pad 30 is disposed at an edge location of the chip 20, i.e., an edge area of the chip 20. Thereby reducing the length of the first bond wire 40 and the length of the second bond wire 90.

Alternatively, the thickness of the first RDL pad 30 and the thickness of the second RDL pad 80 are both greater than or equal to 5 μm and less than or equal to 20 μm.

In some embodiments of the present application, the RDL pad is configured to have a thickness greater than or equal to 5 μm and less than or equal to 20 μm, resulting in optimal conductive performance of the RDL pad.

Optionally, the package structure further includes a heat sink 100; the heat sink 100 is disposed at the second end of the second bonding wire 90, and the plane of the heat sink 90 is parallel to the plane of the substrate 10.

Referring to fig. 1, some embodiments of the present application provide a package structure further including a heat sink 100, where the heat sink 100 is disposed at the second end of the second bonding wire 90, and a plane of the heat sink 100 is parallel to a plane of the substrate 10. Alternatively, the heat sink 100 includes a high heat conductive metal alloy such as copper (Cu), ni, and iron (Fe).

In some embodiments of the present application, the heat-conducting structure formed by the second bonding wires 90 conducts the heat emitted by the chip 20 to the heat sink 100, and increases the heat dissipation area of the chip 20 through the heat sink 100, thereby improving the heat dissipation efficiency of the chip 20.

Optionally, the heat sink 100 and the second end of the second bonding wire 90 are fixed by a thermally conductive adhesive.

In some embodiments of the present application, the heat sink 100 is adhered to the second bonding wire 90 by using a heat conductive adhesive or a heat conductive tape, so that the heat sink 100 is more firmly connected to the second bonding wire 90.

Optionally, the substrate 10 is bonded to the chip 20.

In some embodiments of the present application, a Die Attach Film (DAF), a silver paste, or other adhesive materials may be used to bond the substrate 10 and the Die 20, and fix the Die 20 and the substrate 10 through a curing process, so as to ensure that the Die 20 and the substrate 10 are firmly connected.

Referring to fig. 6, an embodiment of the present application further provides a packaging method applied to the packaging structure described in the above embodiment, where the packaging method includes:

in step 601, a chip is disposed on a substrate.

In this step, the substrate and the chip may be bonded using a chip bonding film, a silver paste, or other bonding materials, and the chip and the substrate may be fixed by a curing process.

In step 602, a first RDL pad is disposed on a side of the chip away from the substrate.

In this step, a layer of RDL structure may be disposed on the surface of the chip by using an electroplating process to form a first RDL pad, where the area of the pad of the first RDL pad may be flexibly disposed, and the position of the first RDL pad on the chip may also be flexibly disposed.

In step 603, a first end of a first bonding wire is welded to the first RDL pad, and a second end of the first bonding wire is welded to at least one lead on the substrate.

In this step, wire bonding may be performed on each first RDL pad disposed on the surface of the chip, where each first RDL pad is disposed to be welded with at least one first bonding wire, and the at least one first bonding wire is further welded with at least one pin on the substrate, so as to implement electrical connection between the chip and the substrate.

In this embodiment of the present application, the RDL pad is disposed on a side of the chip far from the substrate, and the RDL pad may be soldered with a plurality of bonding wires, so that the pad area of the RDL pad is not limited by the wafer size of the chip. In the embodiment of the application, the RDL bonding pad is used for replacing the traditional aluminum bonding pad, so that the spring pit effect caused by overlarge bonding force between the bonding pad and the bonding wire is avoided, and the bonding property between the bonding pad and the bonding wire is prevented from being deteriorated; and the RDL bonding pad can be welded with a plurality of bonding wires on the basis of not compressing the effective space utilization rate of the wafer area, so that the bonding wire bonding mode is more flexible.

Optionally, the substrate, the chip, the first RDL pad and the first bonding wire may be further encapsulated, so that the substrate, the chip, the first RDL pad and the first bonding wire are encapsulated in the plastic package to form a package structure of the chip.

The embodiment of the application also provides electronic equipment, which comprises a chip, wherein the chip comprises the packaging structure.

In this embodiment of the present application, the electronic Device may be a Computer (Computer), a mobile phone, a tablet (Tablet Personal Computer), a Laptop (Laptop Computer), a personal digital assistant (personal digital assistant, PDA), a mobile internet electronic Device (Mobile Internet Device, MID), a Wearable Device (e-reader, navigator, digital camera, etc.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.

Claims (15)

1. A package structure, comprising:

a substrate, and a chip disposed on the substrate;

the first RDL bonding pad is arranged on one side of the chip far away from the substrate;

and the first end of the first bonding wire is welded with the first RDL bonding pad, and the second end of the first bonding wire is welded with at least one pin on the substrate.

2. The package structure of claim 1, wherein a side of the chip remote from the substrate includes a chip pad and a passivation layer, the package structure further including a buffer layer;

the buffer layer is disposed on the passivation layer, and the buffer layer is disposed between the first RDL pad and the passivation layer.

3. The package structure of claim 2, wherein the thickness of the buffer layer is greater than or equal to 5 μιη and less than or equal to 10 μιη.

4. The package structure of claim 1, further comprising a metal layer;

the metal layer is arranged on one side of the first RDL bonding pad far away from the substrate, and a welding part for welding the first bonding wire and the first RDL bonding pad is arranged on the metal layer.

5. The package structure of claim 4, wherein the thickness of the metal layer is greater than or equal to 0.5 μm and less than or equal to 3 μm.

6. The package structure of claim 1, further comprising a plastic package:

the substrate, the chip, the first RDL pad, and the at least one first bonding wire are all encapsulated in the encapsulation.

7. The package structure of claim 1, further comprising a second RDL pad and at least one second bond wire;

the second RDL pad is arranged on one side of the chip far away from the substrate, and the second RDL pad is welded with the first end of the second bonding wire.

8. The package structure of claim 7, wherein a diameter of the second bond wire is greater than a diameter of the first bond wire.

9. The package structure of claim 7, wherein the second RDL pad is disposed in a center area of the chip and the first RDL pad is disposed in an edge area of the chip.

10. The package structure of claim 7, wherein the thickness of the first RDL pad and the thickness of the second RDL pad are each greater than or equal to 5 μιη and less than or equal to 20 μιη.

11. The package structure of claim 7, further comprising a heat sink;

the radiating fin is arranged at the second end of the second bonding wire, and the plane where the radiating fin is positioned is parallel to the plane where the substrate is positioned.

12. The package of claim 11, wherein the heat spreader is bonded to the second end of the second bond wire by a thermally conductive adhesive.

13. The package structure according to any one of claims 1 to 12, wherein the substrate is bonded to the chip.

14. An electronic device, characterized in that the electronic device comprises a package structure as claimed in any of claims 1 to 13.

15. A method of packaging, comprising:

arranging a chip on a substrate;

a first RDL bonding pad is arranged on one side of the chip far away from the substrate;

and arranging a first end of a first bonding wire to be welded with the first RDL bonding pad, and arranging a second end of the first bonding wire to be welded with at least one pin on the substrate.

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