JP2015097237A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing high-frequency noise.SOLUTION: A semiconductor device 100 comprises: a semiconductor chip 1; a die pad 3 on which the semiconductor chip 1 is mounted; a lead 7 that is electrically connected to a gate electrode pad 11 formed in the semiconductor chip 1; and a pad 20 that is arranged in parallel with the semiconductor chip 1. One main surface of the pad 20 is electrically connected to the gate electrode pad 11 by a wiring member 15, and the other main surface is bonded to the lead 7.

Description

  The present invention relates to a semiconductor device, and more particularly to a technique for attenuating high-frequency noise generated during a switching operation of a semiconductor chip in a semiconductor device.

  2. Description of the Related Art Conventionally, in a power module using a power semiconductor chip, a resin sealing structure has been widely adopted for the purpose of improving the reliability of electronic components and improving the productivity of the module.

  For example, Japanese Patent No. 3675603 (Patent Document 1) discloses a power transistor including a three-terminal radial lead type resin-sealed package. The power transistor includes a semiconductor pellet in which an electronic circuit element is formed and a source electrode pad and a gate electrode pad, a tab connected to a surface opposite to the surface in which the electronic circuit element of the semiconductor pellet is formed, A plurality of inner leads formed separately from the tab and electrically connected to the source electrode pad and gate electrode pad of the semiconductor pellet by wires, a plurality of outer leads coupled to each of the plurality of inner leads, and a semiconductor And a resin sealing body in which a pellet, a tab, a plurality of inner leads, and a plurality of outer leads are sealed with a resin.

Japanese Patent No. 3675603

  As a switching element in a power semiconductor chip, a gate insulating transistor (Insulated Gate Bipolar Transistor), a power MOS (Metal Oxide Semiconductor) transistor, and the like that can be switched at a relatively high speed are mainly applied. Conventionally, in this type of semiconductor chip, a silicon (Si) substrate has been widely used.

  Furthermore, in recent years, the use of wide band gap semiconductors having a larger band gap than silicon is being promoted. Typical examples of the wide band gap semiconductor include silicon carbide (SiC) crystal, gallium nitride (GaN), and diamond. Since the wide band gap semiconductor element has a higher electron saturation speed than the silicon semiconductor element, a higher speed switching operation is possible. In addition, wide bandgap semiconductor elements are characterized by high breakdown voltage, low on-resistance, and stable operation in high temperature environments as compared to silicon, so, for example, mounting of a semiconductor chip compared to silicon semiconductor elements having the same current drive capability The area can be reduced. Thereby, size reduction of a power module is realizable.

  On the other hand, in the power module employing the above-described resin sealing structure, ringing occurs in the gate signal due to the influence of the parasitic inductance of the wiring that supplies the gate signal to the gate of the power semiconductor chip. For this reason, when the power semiconductor chip performs a switching operation at a high speed, a large spike voltage is generated in a transient state of on / off switching, resulting in a high-frequency voltage fluctuation. The high frequency noise caused by the high frequency voltage fluctuation can cause a failure of the power semiconductor chip. Therefore, in order to apply a wide band gap semiconductor to a power semiconductor chip, it is important to take measures against such high frequency noise.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of reducing high-frequency noise.

  A semiconductor device according to the present invention includes a semiconductor chip, a die pad on which the semiconductor chip is mounted, a lead electrically connected to a gate electrode pad formed on the semiconductor chip, and one side of the semiconductor chip. The main surface is electrically connected to the gate electrode pad by a wiring member, and the other main surface is provided with a conductive pad joined to the lead.

  According to the present invention, since the parasitic inductance of the wiring for supplying the gate signal to the semiconductor chip can be reduced, the ringing of the gate signal can be reduced. As a result, a semiconductor device capable of reducing high frequency noise can be realized.

It is a top view which shows a general semiconductor device roughly. FIG. 2 is a cross-sectional view of the semiconductor device taken along line II-II in FIG. 1. 1 is a plan view schematically showing a semiconductor device according to a first embodiment. FIG. 4 is a cross-sectional view of the semiconductor device taken along line IV-IV in FIG. 3. FIG. 5 is a cross-sectional view of the semiconductor device taken along line VV in FIG. 3. It is a top view which shows roughly the semiconductor device which concerns on 2nd Embodiment. FIG. 7 is a cross-sectional view of the semiconductor device taken along line VII-VII in FIG. 6. FIG. 7 is a cross-sectional view of the semiconductor device along the line VIII-VIII in FIG. 6.

[Description of Embodiment of Present Invention]
First, embodiments of the present invention will be listed and described.

  (1) A semiconductor device according to the present invention is provided in parallel with a semiconductor chip, a die pad on which the semiconductor chip is mounted, a lead electrically connected to a gate electrode pad formed on the semiconductor chip, and the semiconductor chip. One main surface is electrically connected to the gate electrode pad by a wiring member, and the other main surface is provided with a conductive pad joined to the lead.

  According to this configuration, the length of the gate electrode pad and the wiring member that electrically connects the pads can be shortened, so that the parasitic inductance of the gate signal wiring supplied to the semiconductor chip can be reduced. Thereby, ringing of the gate signal is suppressed, so that high frequency noise generated during the switching operation of the semiconductor chip can be reduced.

  (2) In the semiconductor device, the pad is disposed adjacent to the gate electrode pad.

  According to this configuration, since the gate electrode pad can be electrically connected to the pad with a shorter wiring member, the parasitic inductance of the gate signal wiring can be effectively reduced.

  (3) In the semiconductor device, the lead extends adjacent to the gate electrode pad. The pad is bonded to a position adjacent to the gate electrode pad of the lead.

  According to this configuration, by extending the lead so as to be adjacent to the gate electrode pad, the pad can be disposed adjacent to the gate electrode pad. As a result, the gate electrode pad and the pad can be electrically connected with a shorter wiring member.

  (4) In the semiconductor device described above, the pad is formed on one main surface of the first conductive portion, and on a part of the other main surface, and the second electrically connected to the first conductive portion. Conductive parts. The first conductive portion is disposed adjacent to the gate electrode pad. The second conductive portion is bonded to the lead. The remaining portion of the other major surface of the pad is bonded to the die pad.

  According to this configuration, the pad can be disposed adjacent to the gate electrode pad while being electrically insulated from the die pad. Accordingly, the gate electrode pad and the pad can be electrically connected with a shorter wiring member without changing the shapes of the die pad and the lead.

  (5) In the semiconductor device, the surface height of the pad is equal to the surface height of the gate electrode pad.

  According to this configuration, the gate electrode pad and the pad can be electrically connected with the shortest wiring member.

  (6) In the semiconductor device, the wiring member includes wire bonding or ribbon bonding.

  According to this structure, since the length of a wire or a ribbon can be shortened, the parasitic inductance which a wire and a ribbon have can be reduced.

  (7) In the semiconductor device, the semiconductor chip includes a wide band gap semiconductor.

  According to this configuration, even when the semiconductor chip is made of a wide gap semiconductor capable of high-speed switching operation, high-frequency noise generated during the semiconductor chip switching operation can be reduced.

  (8) In the semiconductor device, a gate resistance is formed on one main surface of the pad.

  According to this configuration, since the gate resistance conventionally provided outside the semiconductor device is mounted on the semiconductor device, the length of the wiring of the gate signal can be shortened, so that the parasitic inductance of the wiring can be reduced. . Further, since an external gate resistor is not required, the external substrate on which the semiconductor device is mounted can be reduced in size.

[Details of the embodiment of the present invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference numerals, and detailed description thereof will not be repeated.

<Embodiment 1>
First, a configuration of a general semiconductor device 1000 that is conventionally applied to a power module or the like will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a plan view schematically showing a general semiconductor device 1000. FIG. 2 is a cross-sectional view of the semiconductor device 1000 taken along line II-II in FIG.

  Referring to FIGS. 1 and 2, semiconductor device 1000 has, for example, a three-terminal radial lead type resin sealing structure. The semiconductor device 1000 includes a semiconductor chip 1, a die pad 3, a resin sealing body 4, three leads 5, 6, and 7, and wire wirings 15 and 16.

  The semiconductor chip 1 is a power semiconductor chip, for example, a power MOSFET. The MOSFET has a drain, a source, and a gate. The drain is formed on the back surface of the semiconductor chip 1. The gate and the source are electrically connected to the gate electrode pad 11 and the source electrode pad 12, respectively. Gate electrode pad 11 and source electrode pad 12 are formed of, for example, aluminum or an aluminum alloy.

  A semiconductor chip 1 is disposed on one main surface of the die pad 3, that is, on the main surface on the front side, with a conductive material 2 such as solder interposed therebetween. The die pad 3 supports and fixes the semiconductor chip 1 and also radiates heat generated by driving the semiconductor chip 1 to the main surface of the die pad 3 opposite to the side in contact with the semiconductor chip 1, that is, the main surface on the back side. have. Note that a heat radiating member (not shown) for releasing the heat transferred to the die pad 3 to the outside of the semiconductor device 1000 may be provided on the main surface on the back side of the die pad 3.

  Leads 6 and 7 are electrically connected to the semiconductor chip 1 via wire wirings 15 and 16, respectively. Specifically, as shown in FIG. 2, the gate electrode pad 11 formed on the surface of the semiconductor chip 1 and a part of the surface of the lead 7 are electrically connected by wire wiring 15 by so-called bonding wire technology. It is connected.

  Similarly, the source electrode pad 12 formed on the surface of the semiconductor chip 1 and a part of the surface of the lead 6 are electrically connected by the wire wiring 16. As shown in FIG. 1, by connecting a plurality of (for example, three) wire wirings 16 between the source electrode pad 12 through which a large current flows and the leads 6, the electrical resistance in the wire wiring is greatly reduced. be able to.

  The die pad 3 is integrally connected to one end of the lead 5. The leads 5, 6, and 7 are conductive members that mediate input / output of electrical signals between the semiconductor chip 1 and the outside of the semiconductor device 1000. The die pad 3 and the leads 5, 6, and 7 are formed of a conductive material having high thermal conductivity, for example, copper or a copper alloy. The wire wirings 15 and 16 are made of, for example, aluminum, gold or copper.

  At least a part of the semiconductor chip 1, the die pad 3, the wire wirings 15, 16 and the leads 5, 6, 7 are sealed with a resin sealing body 4. The resin sealing body 4 has electrical insulation and is made of, for example, an epoxy resin. The resin sealing body 4 protects the semiconductor device 1000 from the environment such as light, heat, and moisture, and from contamination sources such as particles. Note that the other ends of the leads 5, 6, and 7 protrude in parallel from the lower end surface of the resin sealing body 4.

  The semiconductor chip 1 is turned on / off in response to a gate signal supplied from a gate drive circuit (not shown) arranged outside the semiconductor device 1000. The gate drive circuit generates a gate signal in response to a signal from a control device (not shown), and outputs the generated gate signal to the semiconductor chip 1. Specifically, the gate drive circuit is electrically connected to the lead 7 and supplies the generated gate signal to the gate electrode pad 11 through the lead 7 and the wire wiring 15.

  Parasitic inductance exists in the wiring of the gate signal between the gate drive circuit and the gate electrode pad 11. This parasitic inductance increases as the wiring length increases. When ringing occurs in the gate signal due to the influence of the parasitic inductance, the ringing is transmitted to the gate electrode pad 11 of the semiconductor chip 1. As a result, a spike voltage is generated when the semiconductor chip 1 is switched. This spike voltage increases especially when the semiconductor chip is turned off. When the spike voltage increases, a large overshoot in the output voltage of the semiconductor chip 1 and subsequent voltage oscillation are generated. Such vibration of the output voltage becomes high-frequency noise and may cause malfunction or failure of the semiconductor device 1000. Further, high frequency noise may affect the operation of other components such as a control IC.

  In particular, when the semiconductor chip 1 is made of a wide band gap semiconductor, the mounting area of the semiconductor chip 1 can be reduced as compared with a silicon semiconductor having the same current drive capability. On the other hand, wide band gap semiconductors have a faster switching operation than silicon semiconductors, and thus the above-described problem of high frequency noise can be significant.

  In order to suppress the ringing of the gate signal described above, it is necessary to reduce the parasitic inductance of the wiring by shortening the length of the wiring to which the gate signal is supplied. However, in the conventional semiconductor device 1000, as shown in FIG. 2, since the length of the wire wiring 15 is determined by the positional relationship between the gate electrode pad 11 and the lead 7, the parasitic inductance generated by the length of the wire wiring 15 is reduced. There was a problem that it was difficult to do.

  In addition, a gate resistor that is inserted in the gate signal wiring and controls the switching speed of the semiconductor chip 1 is usually provided outside the semiconductor device 1000 together with the gate drive circuit. For this reason, there is a limit to the length of the gate signal wiring that can be shortened.

  The semiconductor device 100 according to the first embodiment of the present invention will be described below with reference to FIGS. FIG. 3 is a plan view schematically showing the semiconductor device 100 according to the first embodiment. FIG. 4 is a cross-sectional view of the semiconductor device 100 taken along line IV-IV in FIG. FIG. 5 is a cross-sectional view of the semiconductor device 100 taken along line VV in FIG.

  Referring to FIG. 3, the semiconductor device 100 according to the first embodiment differs from the conventional semiconductor device 1000 in the gate signal wiring from the lead 7 to the gate electrode pad 11. The schematic configuration of the semiconductor device 100 is the same as that of the conventional semiconductor device 1000 except for the wiring of the gate signal, and thus detailed description will not be repeated.

  In this embodiment, the semiconductor chip 1 includes a wide band gap semiconductor. The wide bandgap semiconductor can be SiC, GaN or diamond. The semiconductor chip 1 is a power semiconductor chip formed of, for example, SiC. In one embodiment, the power semiconductor chip is a power MOSFET. The MOSFET formed of SiC is mounted on one main surface of the die pad 3 and joined to the die pad 3 by a conductive material 2 such as solder. The die pad 3 has a substantially rectangular shape on a plane, and is formed so that one side parallel to the direction in which the gate electrode pad 11 extends is close to the gate electrode pad 11.

  A part of the lead 7 extends along the one side of the die pad 3. In this way, the gate electrode pad 11 and a part of the lead 7 are arranged adjacent to each other.

  Referring to FIGS. 4 and 5, conductive pad 20 is mounted on one main surface of lead 7, that is, the main surface on the front side, and is joined to lead 7 by a conductive bonding material. The pad 20 may be a block 24 made of, for example, alumina or ceramic. Conductive films 23 and 24 made of, for example, gold or silver are formed on the front and back surfaces of the block 24 by a metallization process, for example.

  The conductive film 23 formed on the surface of the block 24 and the conductive film 25 formed on the back surface of the block 24 are electrically connected by a via 22. The via 22 has a sufficiently large diameter compared to the wire wiring 15, thereby realizing a low resistance value. A plurality of small diameter vias may be provided in parallel between the conductive film 23 and the conductive film 25. Alternatively, the conductive film 23 and the conductive film 25 may be electrically connected by metallizing the side surface of the block 24 instead of the via 22. In this way, the main surface on the front side of the lead 7 and the main surface on the front side of the pad 20 are electrically connected.

  The gate electrode pad 11 formed on the semiconductor chip 1 and a part of the main surface on the front side of the pad 20 are electrically connected by the wire wiring 15. At this time, the wire wiring 15 is preferably bonded so as to connect the gate electrode pad 11 and the pad 20 arranged adjacent to each other with the shortest distance. For example, as shown in FIG. 3, the wire wiring 15 is bonded so as to be substantially perpendicular to the extending direction of the gate electrode pad 11 and the pad 20.

  Instead of the wire wiring 15, the gate electrode pad 11 and the pad 20 may be bonded with a wide ribbon (ribbon bonding).

  In this way, the pad 20 is arranged in parallel with the gate electrode pad 11, and the wire wiring 15 is bonded to the main surface of the pad 20, whereby the gate electrode pad 11 and the main surface on the front side of the lead 7 are electrically connected by the wire wiring 15. Compared with the conventional semiconductor device 1000 (see FIG. 2) connected to the wire, the length of the wire wiring 15 can be shortened. Furthermore, by arranging the pad 20 adjacent to the gate electrode pad 11, the length of the wire wiring 15 can be greatly reduced. As a result, the parasitic inductance of the gate signal wiring can be reduced.

  In this embodiment, as shown in FIG. 5, the surface height of the semiconductor chip 1 (surface height of the gate electrode pad 11) and the surface height of the pad 20 are made equal. Thereby, the length of the wire wiring 15 can be made the shortest. The surface height of the semiconductor chip 1 and the surface height of the pad 20 are equal to each other. The surface height of the pad 20 does not necessarily match the surface height of the semiconductor chip 1. It may be somewhat higher than the height or may be somewhat lower. Note that the surface height of the pad 20 can be easily adjusted by setting the thickness of the pad 20 in accordance with the thickness of the semiconductor chip 1.

  Further, a resistance pattern 21 is formed on the conductive film 23 on the surface of the pad 20. The resistance pattern 21 is made of tantalum nitride, for example, and is formed so as to cover a part of the conductive film 23 by vapor deposition or the like. At the time of vapor deposition, a mask may be used so that a predetermined shape (a shape corresponding to the resistance pattern 21) is exposed on the conductive film 23. The resistance pattern 21 is not limited to vapor deposition, and may be formed by attaching a sheet member made of tantalum nitride or the like to the conductive film 23.

  The resistance pattern 21 constitutes a gate resistance for controlling the switching speed of the semiconductor chip 1. By mounting the gate resistance on the semiconductor device 100 in this manner, the gate resistance can be disposed closer to the semiconductor chip 1 than the conventional semiconductor device 1000 in which the gate resistance is provided outside. In addition, since the length of the gate signal wiring can be shortened, the ringing of the gate signal can be effectively suppressed. Furthermore, since an external gate resistor is not necessary, the external substrate on which the semiconductor device 100 is mounted can be downsized.

  As described above, according to the first embodiment of the present invention, since the length of the gate signal wiring can be shortened, the parasitic inductance of the wiring can be reduced. Accordingly, even in a power semiconductor chip (wide gap semiconductor) that performs switching operation at high speed, ringing of the gate signal is suppressed, and thus high-frequency noise generated during the switching operation can be reduced.

<Embodiment 2>
A semiconductor device 110 according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a plan view schematically showing the semiconductor device 110 according to the second embodiment. FIG. 7 is a cross-sectional view of the semiconductor device 110 taken along line VII-VII in FIG. FIG. 8 is a cross-sectional view of the semiconductor device 110 taken along line VIII-VIII in FIG.

  The semiconductor device 110 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment described above in the gate signal wiring from the lead 7 to the gate electrode pad 11. The schematic configuration of the semiconductor device 110 is the same as that of the semiconductor device 100 except for the gate signal wiring, and therefore, detailed description thereof will not be repeated.

  Referring to FIG. 6, in semiconductor device 110, semiconductor chip 1 is mounted on one main surface of die pad 3 and joined to die pad 3 by conductive material 2 such as solder. The die pad 3 has substantially the same shape as the die pad 3 of the conventional semiconductor device 1000.

  Pads 20 are mounted on the front main surface of the die pad 3 and the front main surface of the lead 7. The pad 20 is disposed adjacent to the gate electrode pad 11 of the semiconductor chip 1. As shown in FIG. 7, the pad 20 may be a block 24 formed of, for example, alumina or ceramic. A conductive film 23 is formed on the surface of the block 24 by a metallization process. A conductive film 25 is formed on a part of the back surface of the block 24 by a metallization process. The portion of the back surface of the pad 20 where the conductive film 25 is disposed is bonded to the front main surface of the lead 7. The portion of the back surface of the pad 20 where the conductive film 25 is not disposed is bonded to the front main surface of the die pad 3. That is, the back surface of the pad 20 is electrically connected to the lead 7 while being insulated from the die pad 3.

  The conductive film 23 formed on the surface of the block 24 and the conductive film 25 formed on a part of the back surface of the block 24 are electrically connected by a via 22. The via 22 has a sufficiently large diameter and a low resistance value compared to the wire wiring 15. A plurality of small diameter vias may be provided in parallel between the conductive film 23 and the conductive film 25. Alternatively, the conductive film 23 and the conductive film 25 may be electrically connected by metallizing the side surface of the block 24 instead of the via 22. In this way, the main surface on the front side of the lead 7 and the main surface on the front side of the pad 20 are electrically connected.

  The gate electrode pad 11 formed on the semiconductor chip 1 and a part of the main surface on the front side of the pad 20 are electrically connected by the wire wiring 15. The wire wiring 15 is preferably bonded so as to connect the gate electrode pad 11 and the pad 20 arranged adjacent to each other with the shortest distance. For example, as shown in FIG. 6, the wire wiring 15 is bonded so as to be substantially perpendicular to the extending direction of the gate electrode pad 11 and the pad 20.

  Also in the second embodiment, similarly to the first embodiment described above, the pad 20 is juxtaposed with the gate electrode pad 11, and the wire wiring 15 is bonded to the main surface of the pad 20, thereby making it possible to perform the conventional method. Compared with the semiconductor device 1000 (see FIG. 2), the length of the wire wiring 15 can be shortened. Thereby, the parasitic inductance of the wiring of the gate signal can be reduced.

  Further, as shown in FIG. 7, the length of the wire wiring 15 is minimized by making the surface height of the semiconductor chip 1 (the surface height of the gate electrode pad 11) equal to the surface height of the die pad 20. Can do.

  In the second embodiment, the pad 20 can be juxtaposed with the gate electrode pad 11 without changing the shape of the die pad 3 of the conventional semiconductor device 1000.

  Also in this embodiment, the resistance pattern 21 constituting the gate resistance is formed on the conductive film 23 of the pad 20. By mounting the gate resistance on the semiconductor device 100 in this way, the gate resistance can be arranged closer to the semiconductor chip 1 as compared with the conventional semiconductor device 1000 in which the gate resistance is provided outside, and the wiring of the gate signal is also increased. Since the length can be shortened, the ringing of the gate signal can be effectively suppressed. Furthermore, since an external gate resistor is not necessary, the external substrate on which the semiconductor device 110 is mounted can be downsized.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is advantageously applied to a power module on which a power semiconductor chip is mounted.

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Conductive material 3 Die pad 4 Resin sealing body 5, 6, 7 Lead 11 Gate electrode pad 12 Source electrode pad 15, 16 Wire wiring 20 Pad 21 Resistance pattern 22 Via 23, 25 Conductive film 24 Block 100, 110 Semiconductor apparatus

Claims (8)

A semiconductor chip;
A die pad on which the semiconductor chip is mounted;
A lead electrically connected to a gate electrode pad formed on the semiconductor chip;
A semiconductor device comprising: a conductive pad arranged in parallel to the semiconductor chip, wherein one main surface is electrically connected to the gate electrode pad by a wiring member, and the other main surface is bonded to the lead.   The semiconductor device according to claim 1, wherein the pad is disposed adjacent to the gate electrode pad. The lead extends adjacent to the gate electrode pad,
The semiconductor device according to claim 2, wherein the pad is bonded to a position of the lead adjacent to the gate electrode pad. The pad
A first conductive portion formed on the one main surface;
A second conductive portion formed on a portion of the other main surface and electrically connected to the first conductive portion;
The first conductive portion is disposed adjacent to the gate electrode pad;
The second conductive portion is bonded to the lead;
The semiconductor device according to claim 2, wherein a remaining portion of the other main surface is bonded to the die pad.   The semiconductor device according to claim 1, wherein a surface height of the pad is equal to a surface height of the gate electrode pad.   The semiconductor device according to claim 1, wherein the wiring member includes wire bonding or ribbon bonding.   The semiconductor device according to claim 1, wherein the semiconductor chip includes a wide band gap semiconductor.   The semiconductor device according to claim 1, wherein a gate resistance is formed on the one main surface of the pad.

Images