JP5257096B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a lead frame that are capable of reducing the variations, associated with thermal interference, in the output characteristics of semiconductor elements and circuits, while attaining size reduction and higher operation speed. <P>SOLUTION: The semiconductor device 1 includes a first semiconductor element 31 and a second semiconductor element 32 arranged so as to be spaced from each other in a first direction X; a first die pad 21, extending in the first direction X and including a first surface 21A on which the first semiconductor element 31 and the second semiconductor element 32 are mounted; and a first cutout 211 which extends from a first side surface 21C1 to between the first semiconductor element 31 and the second semiconductor element 32, in a second direction Y crossing the first direction X; and a first lead 23(D) connected to a second side surface 21C2 opposite to the first side surface 21C1 of the first die pad 21. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

The present invention relates to semiconductor equipment, about the particular semiconductor equipment having a plurality of semiconductor devices on the die pad.

  The load driving device disclosed in the prior art document includes a plurality of output power transistors for driving a load and a control IC for driving and controlling the output power transistors. The plurality of output power transistors and the driving IC are all mounted on the same electrode substrate, and the electrode substrate, the output power transistor, and the driving IC are integrally sealed with a mold resin. The output power transistor and the driving IC are electrically connected using a wire.

  In the load driving device configured as described above, since the output power transistor and the driving IC are mounted on the same electrode substrate, the size of the electrode substrate is smaller than when the electrode substrate is individually manufactured. Become. Further, the separation distance between the output power transistor and the driving IC is reduced. Therefore, the load driving device can be downsized.

  Further, in the load driving device, the length of the wire for electrically connecting the output power transistor and the driving IC is shortened. That is, the transmission speed of the drive control signal from the drive IC to the output power transistor can be increased.

JP 2008-16822 A

  However, in the load driving device disclosed in the above prior art document, the following points have not been considered.

  A large current flows through the plurality of output power transistors during operation, and the output power transistors generate heat and cause a temperature rise. Since the plurality of output power transistors are mounted on the same electrode substrate, the heat generated from one output power transistor is transferred to the other output power transistors through the electrode substrate. In other output power transistors, the temperature rises due to the transmitted unnecessary heat, and the output characteristics vary.

  Also, the output characteristic variation due to thermal interference does not occur only between the output power transistors, but the heat generated during the operation of the output power transistors is also applied to the driving IC mounted on the same electrode substrate. affect. That is, the output characteristics of the driving IC vary.

  The present invention has been made to solve the above problems. Accordingly, the present invention is to provide a semiconductor device capable of reducing variations in output characteristics of at least one of a semiconductor element and a circuit due to thermal interference while realizing a reduction in size and an increase in operation speed. .

In order to solve the above problems, according to a first feature of an embodiment of the present invention, in a semiconductor device, a first semiconductor element and a second semiconductor element that are spaced apart from each other in a first direction, The first semiconductor element extends from the first side surface in the second direction that extends in the first direction, has the first semiconductor element and the second semiconductor element mounted on the first surface, and intersects the first direction. A first die pad having a notch reaching between the first die pad and a second semiconductor element; and a lead connected to a second side surface different from the first side surface of the first die pad; The thickness from the first surface to the second surface opposite to the first surface is larger than the thickness of the lead.

In addition, in the semiconductor device, the first semiconductor element and the second semiconductor element that are arranged apart from each other in the first direction, the first semiconductor element that extends in the first direction, and is formed on the first surface, A first die pad on which a second semiconductor element is mounted and has a notch that reaches between the first semiconductor element and the second semiconductor element from the first side surface in a second direction intersecting the first direction When, also comprise a second die pad that is disposed separately on a first side of the first die pad, and mounting electronic parts in a region facing the cutout portion on the surface of the second die pad Good .
In this case, the thickness of the first die pad is preferably thicker than the thickness of the second die pad.

In the semiconductor device according to a first feature, covering the first semiconductor element, a second semiconductor element, the first surface of the first die pad, a second surface opposite the first surface, notch And a thickness of the resin sealing body on the second surface of the first die pad is a thickness from the first surface to the second surface of the first die pad. It is preferable that the thickness of the first die pad of the resin sealing body is thinner than that of the first die pad.

In the semiconductor device according to a first feature, a second side surface of the first die pad is constituted by a second tapered surface at an acute angle relative to the first surface, the first side surface, the first surface On the other hand, it may be constituted by a first tapered surface which is set to an angle which is larger than an acute angle of the second side surface and is equal to or smaller than an angle perpendicular to the first surface.

In the semiconductor device, the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element that are sequentially arranged apart from each other in the first direction are extended in the first direction. The first semiconductor element to the fourth semiconductor element are mounted on the first surface, and the first semiconductor element and the second semiconductor from the first side surface in the second direction intersecting the first direction. A first notch reaching between the first side, a second notch reaching between the third semiconductor element and the fourth semiconductor element from the first side, and a second semiconductor element from the first side A first die pad having a third notch that is between the first and second semiconductor elements and is longer than the lengths of the first notch and the second notch, and the first die pad first A lead connected to a second side different from the side may be provided.

In this case, it is preferable that the lead is integrally formed on the second side surface of the first die pad in a region facing the third notch.

Further, in this case, the first cutout portion and the second cutout portion are the side surfaces where the first semiconductor element and the second semiconductor element face each other in the second direction, and the third semiconductor element and the fourth cutout section. The length is set to be 50% or more and 100% or less with respect to the side surface facing the semiconductor element, and the third cutout portion includes the second semiconductor element and the third semiconductor element in the second direction. Is preferably set to a length exceeding 100% with respect to the opposite side surfaces.

Further, the lead frame, the first die pad and the lead of the semiconductor device according to a first feature, or the first die pad, the second die pad and the lead or may be configured integrally.

  According to the present invention, it is possible to provide a semiconductor device capable of reducing variations in output characteristics of at least one of a semiconductor element and a circuit due to thermal interference while realizing miniaturization and an increase in operation speed. .

It is the principal part top view which removed some resin sealing bodies of the semiconductor device which concerns on one Example of this invention. FIG. 2 is an enlarged cross-sectional view of the entire semiconductor device shown in FIG. 1. FIG. 2 is an overall plan view of the semiconductor device shown in FIG. 1. (A) is a perspective view of the 1st sample used for experiment, in order to explain the semiconductor device concerning one example, (B) is a perspective view of the 2nd sample. (A) is a perspective view of a third sample, and (B) is a perspective view of a fourth sample. It is a graph which shows the relationship between the length of a notch part, and the temperature between semiconductor elements in the semiconductor device which concerns on one Example. It is a graph which shows the relationship between the length of a notch part, and the thermal resistance between semiconductor elements in the semiconductor device which concerns on one Example. It is a graph which shows the transient temperature change of a semiconductor element in the semiconductor device concerning one example. It is a graph which shows the relationship between the width | variety of a notch part, and the temperature of a semiconductor element in the semiconductor device which concerns on one Example. It is a graph which shows the relationship between the thermal resistance of a thermal radiation path | route, and the width | variety of a notch part in the semiconductor device which concerns on one Example. It is a graph which shows the transient temperature change of a semiconductor element in the semiconductor device concerning one example. FIG. 4 is a plan view of a lead frame used for manufacturing the semiconductor device shown in FIGS. 1 to 3.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. In addition, there may be a case where the dimensional relationships and ratios are different between the drawings.

  Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention specifies the arrangement of each component as follows. It is not what you do. The technical idea of the present invention can be variously modified within the scope of the claims.

  In this embodiment, an example in which the present invention is applied to a semiconductor device in which a power transistor and a control circuit for controlling driving thereof are sealed with a resin sealing body will be described.

[Overall structure of semiconductor device]
As shown in FIGS. 1 to 3, the semiconductor device 1 according to the present embodiment includes a first semiconductor element 31, a second semiconductor element 32, and a third semiconductor element that are sequentially spaced apart in the first direction X. The first semiconductor element 31 and the fourth semiconductor element 34 are extended in the first direction X, the first semiconductor element 31 to the fourth semiconductor element 34 are mounted on the first surface 21A, and the first direction X In the second direction Y intersecting with the first semiconductor element 31 and the second semiconductor element 32 from the first side surface 21C1, and from the first side surface 21C1 to the third direction The second notch 212 reaching between the semiconductor element 33 and the fourth semiconductor element 34 and the first side surface 21C1 between the second semiconductor element 32 and the third semiconductor element 33 are reached. A third notch that is longer than the length of the notch 211 and the second notch 212. The first die pad 21 having the portion 213 and the second side surface 21C2 opposed to the first side surface 21C1 of the first die pad 21 are connected to the first semiconductor element 31 to the fourth semiconductor element 34. First leads 23 (D1), 23 (D2), and 23 (D3) are provided.

  Furthermore, the semiconductor device 1 according to the present embodiment has the second die pad 22 that is separated from and separated from the first side surface 21C1 of the first die pad 21 and the second notch 213 in the second region. And a control circuit 35 as an electronic component that is mounted on the first surface 22A of the die pad 22 and controls the operation of the first semiconductor element 31 to the fourth semiconductor element 34.

  The semiconductor device 1 includes a first semiconductor element 31 to a fourth semiconductor element 34, a first surface 21A of the first die pad 21, a second surface 21B opposite to the first surface 21A, and leads. 23, and includes a resin sealing body 5 embedded in the first notch 211, the second notch 212, and the third notch 213. The resin sealing body 5 is formed on the control circuit 35, the first surface 22A of the second die pad 22, the second surface 22B opposite to the first surface 22A, and the first side surface 22C1 of the second die pad 22. Similarly, the inner portions of the second leads 24 arranged along the opposing second side surface 22C2 are covered.

  Here, the first direction X is the same direction as the X-axis direction of the coordinate system, and the second direction is the same direction as the Y-axis direction. The Z-axis direction is a direction perpendicular to a plane including the first direction X and the second direction Y, and will be described as the third direction Z. For example, in the present embodiment, the first direction X is set at right angles to the second direction Y and the third direction Z.

[Configuration of First Semiconductor Element 31 to Fourth Semiconductor Element 34]
In the semiconductor device 1 according to the embodiment shown in FIGS. 1 and 2, the first semiconductor element 31 to the fourth semiconductor element 34 are, for example, the same semiconductor element, and are silicon (Si), silicon carbide ( SiC) or a nitride semiconductor. Here, the first semiconductor element 31 to the fourth semiconductor element 34 include, for example, a switching element or a diode having a vertical structure. In the present embodiment, the first semiconductor element 31 to the fourth semiconductor element 34 may include a horizontal structure, or a switching element or a diode in which a vertical structure and a horizontal structure are mixed. For example, when a semiconductor element having a switching element having a lateral structure is used, an insulator can be interposed between the first die pad 21 and the semiconductor element. The switching element includes at least one of a metal oxide semiconductor field effect transistor (MOSFET) and a metal insulated semiconductor field effect transistor (MISFET).

  A first main electrode pad (here, source electrode pad) 301 and a control electrode pad (here, gate electrode pad) 302 are disposed on the respective surfaces of the first semiconductor element 31 to the fourth semiconductor element 34. Yes. Furthermore, in this embodiment, a temperature sensing pad 303, a voltage sensing pad 304, and a current sensing pad 305 are disposed on the respective surfaces of the first semiconductor element 31 to the fourth semiconductor element 34. . These first main electrode pads 301 and the like are made of, for example, aluminum (Al) or an Al alloy containing an additive. Although not shown, a second main electrode pad (here, a drain electrode pad) is disposed over the entire area of the back surface facing the front surface of each of the first semiconductor element 31 to the fourth semiconductor element 34.

  Each of the first semiconductor element 31 to the fourth semiconductor element 34 is not necessarily limited to this value. For example, the length in the first direction X is 3.2 mm to 3.6 mm, and the second It has a planar shape in which the length in the direction Y is 3.4 mm to 3.8 mm. Further, the thickness in the third direction Z is set to 0.3 mm-0.5 mm. In the present embodiment, each of the first semiconductor element 31 to the fourth semiconductor element 34 is arranged on a straight line in the first direction X. The arrangement interval (pitch) is, for example, 6.1 mm to 6.5 mm.

  In addition, each of the first semiconductor element 31 to the fourth semiconductor element 34 is electrically and mechanically connected via a conductive adhesive (not shown) on the first surface 21A of the first die pad 21. ing. For example, a silver (Ag) paste or the like can be used as the conductive adhesive.

  The first semiconductor element 31 to the fourth semiconductor element 34 may be a composite semiconductor element in which a temperature detection diode and a switching element are mounted in combination. Moreover, for example, an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor, or the like can be used as the switching element.

  In the present embodiment, a total of four semiconductor elements of the first semiconductor element 31 to the fourth semiconductor element 34 are mounted (mounted) on the first surface 21A of the first die pad 21. The number is not limited. For example, a total of two semiconductor elements of the second semiconductor element 32 and the third semiconductor element 33 on the first surface 21A of the first die pad 21, or the first semiconductor element 31 to the fourth semiconductor element 34. In addition, a total of six semiconductor elements may be mounted on the left side of the first semiconductor element 31 and the right side of the fourth semiconductor element 34 in FIG. Here, a maximum of six semiconductor elements can be mounted on the first surface 21A of the first die pad 21. Further, although it is necessary to change the shape of the first die pad 21, eight, twelve, etc. semiconductor elements can be mounted on the first surface 21 </ b> A of the first die pad 21.

  In addition, in the present embodiment, the first semiconductor element 31 to the fourth semiconductor element 34 are sequentially arranged in a straight line in the first direction X when viewed from the third direction Z. There is no need to arrange them in the top row. For example, the first semiconductor element 31 to the fourth semiconductor element 34 are sequentially arranged in the first direction X, and the second semiconductor element 32 to the fourth semiconductor element 34 are compared with the first semiconductor element 31. At least one of them may be shifted in the second direction Y. Specifically, when the third semiconductor element 33 and the fourth semiconductor element 34 are shifted in the second direction Y with respect to the first semiconductor element 31 and the second semiconductor element 32, When the second semiconductor element 32 and the fourth semiconductor element 34 are displaced in the second direction Y with respect to the semiconductor element 31 and the third semiconductor element 33, the first semiconductor element 31 and the fourth semiconductor element 34 are arranged. This includes a case where the second semiconductor element 32 and the third semiconductor element 33 are shifted in the second direction Y with respect to the semiconductor element 34. In this embodiment, these arrangement forms are also used in the sense of sequential arrangement in the first direction X.

[Configuration of Control Circuit 35]
In this embodiment, the control circuit 35 as an electronic component is a control monolithic IC (MIC) that performs drive control of each of the first semiconductor element 31 to the fourth semiconductor element 34. The control circuit 35 is made of Si, SiC, or a nitride semiconductor in the same manner as each of the first semiconductor element 31 to the fourth semiconductor element 34, and elements such as transistors, capacitors, resistors, etc. are integrated on this semiconductor chip. Is building. The control circuit 35 is not necessarily limited to this value. For example, the length in the first direction X is 6.4 mm-6.8 mm, and the length in the second direction Y is 4.0 mm-4. It has a planar shape of 4 mm. Further, the thickness in the third direction Z is set to 0.3 mm-0.5 mm.

  The control circuit 35 is mechanically connected to the first surface 22A of the second die pad 22 in an electrically separated state with an insulator (not shown) interposed therebetween. For this insulator, for example, an epoxy adhesive, an epoxy resin substrate, a ceramic substrate, or the like can be used.

  Each of the control electrode pad 302, the temperature sensing pad 303, the voltage sensing pad 304, and the current sensing pad 305 of the first semiconductor element 31 is a wiring board 36 disposed on the left side of the control circuit 35 in FIG. And indirectly connected to the electrode pad 351 of the control circuit 35. For example, the second wire 42 is used for electrical connection between the control electrode pad 302 and the like of the first semiconductor element 31 and the wiring board 36 and electrical connection between the wiring board 36 and the electrode pad 351 of the control circuit 35. Has been.

  The control electrode pad 302 and the like of the second semiconductor element 32 are electrically connected directly to the electrode pad 351 of the control circuit 35 without going through the wiring board 36. Similarly, for example, the second wire 42 is used for both electrical connections.

  The control electrode pad 302 and the like of the third semiconductor element 33 are electrically connected directly to the electrode pad 351 of the control circuit 35, similarly to the connection structure between the second semiconductor element 32 and the control circuit 35. . Similarly, for example, the second wire 42 is used for both electrical connections.

  The control electrode pads 302 and the like of the fourth semiconductor element 34 are passed through the wiring substrate 36 disposed on the right side of the control circuit 35 in FIG. 1 as in the connection structure between the first semiconductor element 31 and the control circuit 35. It is electrically connected to the electrode pad 351 of the control circuit 35 indirectly. For example, the second wire 42 is used for the electrical connection between the control electrode pad 302 and the like of the fourth semiconductor element 34 and the wiring board 36 and the electrical connection between the wiring board 36 and the electrode pad 351 of the control circuit 35. Has been.

  In the present embodiment, for example, a thin gold (Au) wire is used for the second wire 42. For the bonding of the second wire 42, a wire bonding method using ultrasonic vibration in combination with thermocompression bonding is used.

  On the other hand, the first main electrode pad 301 of the first semiconductor element 31 is electrically connected to the first lead 23 (S 1) through the first wire 41, and the first main electrode of the second semiconductor element 32. The pad 301 is electrically connected to the first lead 23 (S2) through the first wire 41. Similarly, the first main electrode pad 301 of the third semiconductor element 33 is electrically connected to the first lead 23 (S3) through the first wire 41, and the first main electrode pad 301 of the fourth semiconductor element 34 is connected. The electrode pad 301 is electrically connected to the first lead 23 (S4) through the first wire 41.

  In the present embodiment, for example, a thicker Al wire is used for the first wire 41 as compared with the second wire 42. For the bonding of the first wire 41, a wire bonding method using both ultrasonic vibration and thermocompression bonding is used in the same manner as the wire bonding method of the second wire.

[Configuration of Wiring Board 36]
The wiring board 36 is disposed on each of the left and right sides of the control circuit 35 in FIG. 1 on the first surface 22A of the second die pad 22. In this embodiment, the wiring board 36 includes an insulating substrate 361 and wiring 362 disposed on the surface thereof. A plurality of wirings 362 on the wiring board 36 extend in the first direction X and are arranged in the second direction Y at regular intervals.

  In FIG. 1, the wiring board 36 disposed on the left side of the control circuit 35 has a layout in which the wiring 362 is drawn from the left end of the control circuit 35 to a region facing the first semiconductor element 31. It has a function of relaxing a wire bonding rule required for electrical connection with the first semiconductor element 31. That is, when each of the first semiconductor element 31 and the second semiconductor element 32 and the control circuit 35 are directly connected through the second wire 42, the bonding density of the second wire 42 is increased. Since the length of the second wire 42 is increased and a short circuit between the adjacent second wires 42 is induced, the connection between the first semiconductor element 31 and the control circuit 35 is bypassed through the wiring board 36.

  Similarly, the wiring board 36 disposed on the right side of the control circuit 35 has a layout in which the wiring 362 is drawn from the right end of the control circuit 35 to a region facing the fourth semiconductor element 34. 4 has a function of relaxing the wire bonding rule required for electrical connection with the semiconductor element 34. That is, when each of the third semiconductor element 33 and the fourth semiconductor element 34 and the control circuit 35 are directly connected through the second wire 42, the bonding density of the second wire 42 is increased. Since the length of the second wire 42 is increased and a short circuit between the adjacent second wires 42 is induced, the connection between the fourth semiconductor element 34 and the control circuit 35 is bypassed through the wiring board 36.

  The wiring board 36 not only has a function of relaxing the wire bonding rule required for connection to each of the first semiconductor element 31 and the fourth semiconductor element 34, but also electrically connected to the second lead 24. It also has a function of relaxing wire bonding rules required for connection. The electrode pad 351 of the control circuit 35 and the second lead 24 arranged in the central portion along the second side surface 22C2 of the second die pad 22 are directly electrically connected through the second wire 42. Yes. Further, the electrode pad 351 of the control circuit 35 and the second lead 24 arranged in the peripheral portion along the second side surface 22C2 of the second die pad 22 indirectly through the second wire 42 and the wiring board 36. Electrically connected. In either case, the length of the second wire 42 can be shortened. Since the cross-sectional area of the second wire 42 is smaller than the cross-sectional area of the wiring 362 of the wiring board 36, the signal transmission speed can be increased by shortening the length of the second wire 42. .

  In the present embodiment, the insulating substrate 361 of the wiring substrate 36 is made of, for example, glass epoxy resin. The wiring 362 is not limited to this structure. For example, the wiring 362 is formed of a composite film in which a nickel (Ni) -phosphorus (P) alloy layer and an Au layer are stacked on a copper (Cu) layer. Although not shown, a solder resist film may be disposed on the wiring 362 as a protective film.

  Note that, according to the function required for the semiconductor device 1 according to the present embodiment, a region of the second die pad 22 where the wiring board 36 is mounted is replaced with a semiconductor element (semiconductor chip), instead of the wiring board 36. Electronic components other than the control circuit 35 such as a resistor, a capacitor, an inductor, and a transformer can be mounted.

[Configuration of the first die pad 21]
As shown in FIG. 1, the planar shape of the first die pad 21 is elongated in the first direction X, and the portion on which each of the first semiconductor element 31 to the fourth semiconductor element 34 is mounted is the first. The side surface 21C1 projects in the second direction Y, and conversely, the first cutout portion 211, the second cutout portion 212, and the third cutout portion 213 are directed from the first side surface 21C1 toward the second side surface 21C2. The second side surface 21 </ b> C <b> 2 is configured to have a comb shape that is retreated halfway and continues in the first direction X.

  Although not necessarily limited to this numerical value, the length of the first die pad 21 in the first direction X is set to, for example, 38.5 mm-39.5 mm, and the width in the second direction Y is set to, for example, 7. It is set to 2 mm-7.6 mm. A thickness t1 from the first surface 21A of the first die pad 21 to the second surface (back surface) 21B facing the first surface 21A is set to 1.8 mm-2.2 mm, for example. Here, the thickness t2 of each of the second die pad 22, the first lead 23, and the second lead 24 is set to, for example, 0.3 mm to 0.7 mm. The die pad 21 has a thickness more than double.

  As shown in FIG. 2, the second side surface 21C2 of the first die pad 21 is configured by a second tapered surface that forms an acute angle α2 with respect to the first surface 21A. The first side surface 21C1 forms a first acute angle α1 with respect to the first surface 21A that is larger than the acute angle α2 of the second side surface 21C2 and perpendicular to the first surface 21A, preferably smaller than that. It is constituted by a tapered surface. The acute angle α1 can be the same as the acute angle α2, or the acute angle α1 can be smaller than the acute angle α2.

  The first side surface 21C1 of the first die pad 21 has a function of increasing the cross-sectional area of the heat radiation path in the thickness direction from the first surface 21A to the second surface 21B as much as possible and reducing the thermal resistance in the heat radiation path. It has. In addition, the first side surface 21C1 is configured by a first tapered surface in order to create a draft when the first die pad 21 is manufactured by a mold. In the present embodiment, the acute angle α1 is set to, for example, 80 degrees to 84 degrees.

  On the other hand, on the second side surface 21C2 of the first die pad 21, a plurality of first leads 23 are arranged along the second side surface 21C2, and the flowable resin wraps around the resin sealing body 5 using the transfer molding method. Has the ability to improve. That is, if the acute angle α2 is small, the inclination angle of the second tapered surface of the second side surface 21C2 becomes loose, and the flow path of the fluid resin can be expanded. In addition, as with the first side surface 21C1, the second side surface 21C2 needs to increase the cross-sectional area of the heat dissipation path in the thickness direction of the first die pad 21 as much as possible. Therefore, in the present embodiment, the acute angle α2 is set to 55 ° -65 °, for example.

  The most distal portion 216 closest to the second die pad 22 on the first side surface 21C1 of the first die pad 21 is thinner than the other portions. Here, the second die pad 22, The lead 23 and the second lead 24 are configured to have the same thickness as the thickness t2. The length of the forefront portion 216 in the second direction Y is set to 0.1 mm-0.3 mm, for example. The most advanced portion 216 has a function of reducing the cross-sectional area of the heat radiation path from the first die pad 21 to the second die pad 22 by increasing the thickness and increasing the thermal resistance in the heat radiation path. Yes. That is, the heat generated by the operation of each of the first semiconductor element 31 to the fourth semiconductor element 34 becomes difficult to be transferred from the first die pad 21 to the second die pad 22 because the most advanced portion 216 becomes a thermal resistance. It has become.

  The first notch 211 to the third notch 213 are provided on the first side surface 21C1. The first notch 211 to the third notch 213 suppress the temperature interference between the first semiconductor element 31 to the fourth semiconductor element 34 adjacent in the first direction X, as will be described later. In addition, the first die pad 21 has a shape in which the first side surface 21C1 of the first die pad 21 is partially removed (notched) at a portion closest to the second die pad 22, and the first die pad 21 to the second die pad. 22 has the effect of suppressing the propagation of heat toward 22.

  The first die pad 21 and the first lead 23 are manufactured as the same lead frame, and are cut from the lead frame. In this embodiment, the first die pad 21 and the first lead 23 use, for example, a Cu plate or a Cu alloy plate having excellent electrical conductivity and excellent thermal conductivity, and etching or punching these metal plates. Formed by processing.

[Configuration of First Notch 211 to Third Notch 213]
The first notch 211 arranged in the first die pad 21 has a length L1 that is 50% or more and 100% or less with respect to the side surface where the first semiconductor element 31 and the second semiconductor element 32 face each other. Is set to Further, the first notch 211 is set to have a width W1 of 50% or more and 100% or less with respect to the thickness of the first die pad 21. Here, the length L1 of the first notch 211 is the length of the first notch 211 in the second direction Y, and the width W1 of the first notch 211 is the first notch 211. In the first direction X.

  Similarly, the second notch portion 212 disposed in the first die pad 21 is applied to 50% or more and 100% or less with respect to the side surface where the third semiconductor element 33 and the fourth semiconductor element 34 face each other. The length is set to L1. Similarly, the second notch 212 is set to have a width W1 of 50% or more and 100% or less with respect to the thickness of the first die pad 21.

  On the other hand, the third cutout portion 213 disposed in the first die pad 21 is longer than the length L1 with respect to the side surface where the second semiconductor element 32 and the third semiconductor element 33 face each other. The length L2 is set to be long and exceeds 100%. Further, the third notch 213 has a width of 50% or more and 100% or less with respect to the thickness of the first die pad 21, similarly to the width W 1 of the first notch 211 and the second notch 212. W2 is set.

  The relationship between the respective sizes of the first to third notches 211 to 213 and the temperature interference between adjacent ones of the first to fourth semiconductor elements 31 to 34 is as follows. . This relationship has been derived based on the experimental results of the present inventors.

  FIG. 4A shows a basic configuration of a sample corresponding to a main part of the semiconductor device 1 used in the experiment. Here, for easy understanding, the first semiconductor element 31 and the second semiconductor element 32 which are adjacent to each other in the first direction X in correspondence with the components of the semiconductor device 1 shown in FIGS. A basic sample having a first notch 211 disposed in the first die pad 21 between them was used.

  In this basic sample, the size of the first die pad 21 is such that the length L in the first direction X is 10.6 mm, the width W in the second direction Y is 7.0 mm, and the thickness t in the third direction Z. Was set to 2.0 mm. The length of the region in which the first semiconductor element 31 of the first die pad 21 is mounted in the first direction X and the length of the region in which the second semiconductor element 32 is mounted in the first direction X are both 4. The width W1 of 3 mm and the first cutout portion 211 was set to 2.0 mm. The second side surface 2C of the first die pad 21 has a position of 1.4 mm from the side surface on the first semiconductor element 31 side of the first die pad 21 and 7.2 mm from the side surface on the second semiconductor element 32 side. A first lead 23 (D) having a length of 9.0 mm, a width of 2.0 mm, and a thickness of 0.5 mm is integrally connected to the position.

  The sizes of the first semiconductor element 31 and the second semiconductor element 32 are 3.4 mm in length in the first direction X, 3.6 mm in width in the second direction Y, and thickness in the third direction Z. Was set to 0.4 mm, respectively. Each of the first semiconductor element 31 and the second semiconductor element 32 has a separation dimension of 0.45 mm in the first direction X between the first notch 211 and the first side surface 21C1 to 1.. It was mounted with a 5 mm spacing. One first semiconductor element 31 was used as a heating element, and the central portion of the other second semiconductor element 32 was used as a measurement point for heat generated from the first semiconductor element 31.

  The size of the resin sealing body 5 was set such that the length in the first direction X was 12.6 mm, the width in the second direction Y was 9.0 mm, and the thickness in the third direction Z was 4.4 mm. . The thickness of the first side surface 21C1, the second side surface 21C2, and other side surfaces of the first die pad 21 of the resin sealing body 5 is 1.0 mm. The thickness of the back surface (the second surface 21B side of the first die pad 21) of the first lead 23 (D) of the resin sealing body 5 is 2.0 mm, and the second surface 21B side of the first die pad 21 The thickness of was set to 0.5 mm. Here, an epoxy resin is used as the resin sealing body 5.

  The experimental conditions were that the initial temperature was 25 ° C., and the amount of heat generated on the surface (chip surface) of the first semiconductor element 31 was 30 W. Furthermore, the surface temperature on the second surface 21B side of the first die pad 21 of the resin sealing body 5 serving as a main heat dissipation path was maintained at 25 ° C., and the heat dissipation condition was set to 9000 W / m · k. In addition, the surface temperature of the other surfaces of the resin sealing body 5 and the first lead 23 (D) in contact with the outside air is similarly maintained at 25 ° C., and this natural heat dissipation condition is set to 10 W / m · k. did. The temperature analysis time was set in the range of 0 seconds to 1 second, and the temperature measurement sampling time was set to 0.05 seconds.

FIGS. 4B, 5A, and 5B all show the basic configuration of the sample. The width W1 of the first notch 211 is constant, but the length L1 is different. The sample shown in FIG. 4B has a first notch 211 that extends from the first side surface 21C1 of the first die pad 21 to the opposing surface of the first semiconductor element 31 and the second semiconductor element 32. the first notch 211 is referred to as the length L1 _0. The sample shown in FIG. 5 (A) has a first notch 211 that takes 50% from the first side surface 21C1 of the first die pad 21 to the opposing surface of the first semiconductor element 31 and the second semiconductor element 32. and, the first notch 211 is referred to as the length L1 _50. The sample shown in FIG. 5B has a first notch 211 that is 100% extending from the first side surface 21C1 of the first die pad 21 to the opposing surface of the first semiconductor element 31 and the second semiconductor element 32. and, the first notch 211 is referred to as the length L1 _100.

  FIG. 6 shows the relationship between the length L1 of the first notch 211 and the temperature between the semiconductor elements. In FIG. 6, the horizontal axis represents the ratio of the length of the first notch 211 to the length in the second direction Y of the facing surfaces of the first semiconductor element 31 and the second semiconductor element 32. The vertical axis represents the temperature (° C.) measured in the second semiconductor element 32 after 1 second has caused the first semiconductor element 31 to generate heat.

As is apparent from FIG. 6, the length L1 ₀ (corresponding to the sample shown in FIG. 4B) in which the first notch 211 is just applied to the opposing surface of the first semiconductor element 31 and the second semiconductor element 32. ) Until most of the heat generated from the first semiconductor element 31 is propagated to the second semiconductor element 32 through the first die pad 21. The second semiconductor element 32 is affected by the heat propagated from the first semiconductor element 31, and the temperature rises to 56 ° C. to 57 ° C. Exceeds the length L1 ₀ of the first notch 211, the propagation of heat generated from the first semiconductor element 31 is blocked by the first notch 211, the temperature of the second semiconductor element 32 is lowered.

When the length L1 ₅₀ (corresponding to the sample shown in FIG. 5A) where the first notch 211 takes 50% on the opposing surface of the first semiconductor element 31 and the second semiconductor element 32 is exceeded, The effect of blocking the heat propagation generated from the first semiconductor element 31 by the first notch portion 211 appears remarkably, and the temperature of the second semiconductor element 32 rapidly decreases to 52 ° C. to 53 ° C. or lower. When the length L1 ₁₀₀ (corresponding to the sample shown in FIG. 5B) where the first notch 211 is 100% on the opposing surface of the first semiconductor element 31 and the second semiconductor element 32 is equivalent to the first The effect of blocking the propagation of heat generated from the semiconductor element 31 by the first notch 211 appears more remarkably, and the temperature of the second semiconductor element 32 falls to 44 ° C.-45 ° C. or lower.

  FIG. 7 shows the relationship between the length L1 of the first notch 211 and the thermal resistance between the semiconductor elements. In FIG. 7, the horizontal axis represents the ratio of the length of the first notch 211 to the length in the second direction Y of the facing surfaces of the first semiconductor element 31 and the second semiconductor element 32. The vertical axis represents the thermal resistance (° C./W) between the first semiconductor element 31 and the second semiconductor element 32 measured after 1 second with the first semiconductor element 31 generating heat.

As is apparent from FIG. 7, the length L1 ₀ (corresponding to the sample shown in FIG. 4 (B)) in which the first notch 211 just hangs on the opposing surface of the first semiconductor element 31 and the second semiconductor element 32. ), The thermal resistance of the heat dissipation path from the first semiconductor element 31 to the second semiconductor element 32 of the first die pad 21 increases at a constant rate. When the first notch 211 length L1 _0, the thermal resistance is about 2.0 ° C. / W. The rate of the constant increase in the thermal resistance is such that the length L1 ₅₀ at which the first notch 211 takes 50% on the opposing surface of the first semiconductor element 31 and the second semiconductor element 32 (see FIG. 5A). (Equivalent to the sample shown)) When the first notch 211 has a length L1 ₅₀ , the thermal resistance is about 2.1 ° C./W.

Beyond this, especially when the first notch 211 reaches a length that takes 60% or more, the thermal resistance of the heat dissipation path increases rapidly. When the length of the first notch 211 is 60%, the thermal resistance is about 2.15 ° C./W. The thermal resistance rapidly increases until the length L1 ₁₀₀ (corresponding to the sample shown in FIG. 5B) where the first notch 211 is 100% on the opposing surface of the first semiconductor element 31 and the second semiconductor element 32. The increase rate of this thermal resistance becomes constant. When the length of the first notch 211 is 100%, the thermal resistance is about 2.4 ° C./W.

Here, when the first notch 211 is 50% across the length L1 ₅₀ of the take particular 100% greater than the length L1 ₁₀₀ or more in length that is disposed in the first die pad 21, first The thermal resistance of the heat radiation path from the first semiconductor element 31 to the second semiconductor element 32 of the die pad 21 is remarkably increased. Therefore, the first die pad 21 serving as a heating element is connected to the vicinity of the first semiconductor element 31, specifically, the second side surface 21 </ b> C <b> 2 before reaching the first notch 211 of the first die pad 21. If one lead 23 (D) is provided, heat generated from the first semiconductor element 31 can be effectively radiated using the first lead 23 (D) as a heat radiation path.

  FIG. 8 shows a transient temperature change of the semiconductor element. In FIG. 8, the horizontal axis indicates the elapsed time (seconds) from the start of heat generation of the first semiconductor element 31. The vertical axis represents temperature (° C.).

Data summarized with reference numeral 31 is data indicating the temperature measured at every elapse of a predetermined time from the start of heat generation in the first semiconductor element 31 as the heat generating element. Among these, the data 31 n indicates a transient temperature change of the first semiconductor element 31 when the first notch 211 is not provided in the first die pad 21. Data 31a indicates a transient temperature change of the first semiconductor element 31 when the first notch 211 having the length L1 ₀ is provided in the first die pad 21. Data 31b indicates a transient temperature change of the first semiconductor element 31 when the first notch 211 having the length L1 ₅₀ is provided in the first die pad 21. Data 31 c represents a transient temperature change of the first semiconductor element 31 when the first notch 211 having the length L1 ₁₀₀ is provided in the first die pad 21. Data 31av is an average value of data 31a, 31b and 31c.

On the other hand, data bundled with reference numeral 32 is data indicating the temperature measured at every elapse of a predetermined time from the start of heat generation in the second semiconductor element 32 as a measurement body. Among these, data 32n indicates a transient temperature change of the second semiconductor element 32 when the first notch 211 is not provided in the first die pad 21. Data 32a indicates a transient temperature change of the second semiconductor element 32 when the first notch 211 having the length L1 ₀ is provided in the first die pad 21. Data 32b indicates a transient temperature change of the second semiconductor element 32 when the first notch 211 having the length L1 ₅₀ is provided in the first die pad 21. The data 32c indicates a transient temperature change of the second semiconductor element 32 when the first notch 211 having the length L1 ₁₀₀ is provided in the first die pad 21. Data 32av is an average value of data 32a, 32b, and 32c.

  In FIG. 8, when the first notch 211 is not provided in the first die pad 31, the transient temperature of the first semiconductor element 31 is the lowest as shown in the data 31n, but conversely shown in the data 32n. As described above, the transient temperature of the second semiconductor element 32 becomes the highest. That is, the influence of the heat generated from the first semiconductor element 31 on the second semiconductor element 32 is the largest.

  On the other hand, when the first notch 211 is disposed in the first die pad 31, the transient temperature of the first semiconductor element 31 increases as shown in the data 31av, but conversely shown in the data 32av. Thus, the transient temperature of the second semiconductor element 32 is lowered. That is, the influence of the heat generated from the first semiconductor element 31 on the second semiconductor element 32 can be reduced. Further, as shown in the data 31a, 31b and 31c, although the transient temperature of the first semiconductor element 31 gradually increases as the length L1 of the first notch 211 increases, the data 32a, 32b And as shown to 32c, the transient temperature of the 2nd semiconductor element 32 becomes low gradually.

According to the experimental results shown in FIG. 6 to FIG. 8 described above, the first notch 211 having a length that does not reach the opposing surface of the first semiconductor element 31 and the second semiconductor element 32 is simply the first notch 211. If it is disposed on the die pad 21, thermal interference from the first semiconductor element 31 to the second semiconductor element 32 cannot be suppressed. In order to suppress the thermal interference, the first cutout portion 211 having the length L1 that is applied to the facing surfaces of the first semiconductor element 31 and the second semiconductor element 32 is necessary. Furthermore, by providing the first notch 211 that exceeds the length L1 ₅₀ that takes 50%, in the second semiconductor element 32, the influence of heat from the first semiconductor element 31 can be drastically reduced. . The second semiconductor element 32 can reduce the influence of heat from the first semiconductor element 31 as much as possible by providing the first notch 211 that exceeds the length L1 ₁₀₀ that is 100%.

  Next, in the basic sample shown in FIG. 4A, adjacent semiconductors when the length L1 of the first notch 211 provided in the first die pad 21 is constant and the width W1 is changed. The experimental results of temperature interference between elements are as follows. Here, the length L1 of the first notch 211 is 4.0 mm from the first side surface 21C1 of the first die pad 21 (approximately about the opposing surface of the first semiconductor element 31 and the second semiconductor element 32). 69% -70% length). The other sizes and experimental conditions of the first die pad 21 are the same as described above.

  FIG. 9 shows the relationship between the width W 1 of the first notch 211 and the temperature of the second semiconductor element 32. In FIG. 9, the horizontal axis represents the width W1 (mm) of the first notch 211 in the first direction X. Here, on the horizontal axis, the width W1 of 0 mm means a case where the first notch 211 itself is not provided. The vertical axis represents the temperature (° C.) measured in the second semiconductor element 32 after 1 second has caused the first semiconductor element 31 to generate heat.

  As is clear from FIG. 9, if the first notch 211 is disposed between the first semiconductor element 31 and the second semiconductor element 32 of the first die pad 21, the first semiconductor element 31. Propagation of heat generated from the second semiconductor element 32 decreases rapidly, and the temperature of the second semiconductor element 32 decreases. This decrease in temperature proceeds at a constant rate until the width W1 of the first notch 211 is about 1.0 mm. When the width W1 exceeds about 1.0 mm, the temperature of the second semiconductor element 32 does not change, and the saturated state continues. Then, when the width W1 of the first notch 211 is about 2.0 mm, the temperature of the second semiconductor element 32 tends to increase although it is very small. This is because the area of the first surface 21A of the first die pad 21 decreases as the width W1 of the first notch 211 increases, and the first surface 21A to the second surface of the first die pad 21 decreases. (Back side) This is because the cross-sectional area of the heat radiation path toward 2B decreases and the thermal resistance increases.

  According to the experimental results shown in FIG. 9, the width W1 of the first notch 211 is set to 1.0 mm or more, which is a boundary between a rapid temperature drop and a saturated state, and an extremely slight temperature rise is observed. Since there is no large difference from the temperature at the boundary of the product, it is set to 3.0 mm or less. Further, preferably, the width W1 of the first notch 211 is set to 2.0 mm or less in consideration of a decrease in the thermal resistance of the heat radiation path to the second surface 21B side of the first die pad 21.

  Here, since the thickness of the first die pad 21 is set to 2.0 mm, the most preferable width W1 of the first notch 211 can be expressed by the following relational expression.

0.5mm ≤ W1 ≤ 1.0mm
FIG. 10 shows the heat resistance of the heat radiation path from the first surface 21A of the first die pad 21 to the back surface of the resin sealing body 5 through the second surface (back surface) 2B, and the width W1 of the first notch 211. The relationship is shown. In FIG. 10, the horizontal axis represents the width W1 (mm) of the first notch 211 disposed on the first die pad 21. The vertical axis shows the heat of the heat dissipation path (first surface 21A of the first die pad 21-back surface of the resin sealing body 5) measured on the back surface of the resin sealing body 5 after 1 second by causing the first semiconductor element 31 to generate heat. Resistance (° C./W).

  As is apparent from FIG. 10, when the first notch 211 is disposed in the first die pad 21, the thermal resistance rapidly increases in the heat dissipation path. When the width W1 of the first notch 211 is 0 mm, that is, when the first notch 211 is not provided, the thermal resistance is about 2.0 ° C./W. The rapid increase in thermal resistance proceeds at a constant rate until the width W1 of the first notch 211 is 1.0 mm. The thermal resistance at this time is about 2.06 ° C./W−2.08° C./W.

  When the width W1 of the first notch 211 exceeds 1.0 mm, the rate of increase in thermal resistance decreases. This rate of increase is constant. The thermal resistance when the width W1 of the first notch 211 is 2.0 mm is about 2.15 ° C./W, and the thermal resistance when the width W1 of the first notch 211 is 3.0 mm is about 2 24 ° C / W.

  In other words, when the width W1 of the first notch 211 is less than 1.0 mm, the first die pad 21 is disposed with the first notch 211, so that heat is rapidly released from the back surface of the resin sealing body 5. Efficiency is reduced. On the other hand, if the width W1 of the first notch 211 exceeds 1.0 mm, the rate of increase in thermal resistance can be reduced, so that the reduction in heat dissipation efficiency from the back surface of the resin sealing body 5 is suppressed. can do. Rather, by setting the width W1 of the first notch 211 to 1.0 mm or more, the influence of the heat from the first semiconductor element 31 on the second semiconductor element 32 can be suppressed, and further the resin The heat dissipation efficiency from the back surface of the sealing body 5 can be increased.

  FIG. 11 shows a transient temperature change of the semiconductor element. In FIG. 11, the horizontal axis indicates the elapsed time (seconds) from the start of heat generation of the first semiconductor element 31. The vertical axis represents temperature (° C.).

  Similarly to the description in FIG. 8 described above, the data enclosed with reference numeral 31 is data indicating the temperature measured at every elapse of a predetermined time from the start of heat generation in the first semiconductor element 31 as the heating element. Among these, the data 31 n indicates a transient temperature change of the first semiconductor element 31 when the first notch 211 is not provided in the first die pad 21. Data 31d represents a transient temperature change of the first semiconductor element 31 when the first notch 211 having the width W1 set to 1.0 mm is disposed on the first die pad 21. Data 31e indicates a transient temperature change of the first semiconductor element 31 when the first notch 211 having the width W1 set to 2.0 mm is provided on the first die pad 21. Data 31f indicates a transient temperature change of the first semiconductor element 31 when the first notch 211 having the width W1 set to 3.0 mm is provided on the first die pad 21. Data 31av is an average value of data 31d, 31e, and 31f.

  On the other hand, data bundled with reference numeral 32 is data indicating the temperature measured at every elapse of a predetermined time from the start of heat generation in the second semiconductor element 32 as a measurement body. Among these, data 32n indicates a transient temperature change of the second semiconductor element 32 when the first notch 211 is not provided in the first die pad 21. Data 32d indicates a transient temperature change of the second semiconductor element 32 when the first notch 211 having the width W1 set to 1.0 mm is disposed on the first die pad 21. Data 32e indicates a transient temperature change of the second semiconductor element 32 when the first notch 211 having the width W1 set to 2.0 mm is provided on the first die pad 21. Data 31f indicates a transient temperature change of the second semiconductor element 32 when the first notch 211 having the width W1 set to 3.0 mm is disposed on the first die pad 21. Data 32av is an average value of data 32d, 32e, and 32f.

  In FIG. 11, when the first notch 211 is not provided in the first die pad 31, the transient temperature of the first semiconductor element 31 is the lowest as shown in the data 31n, but conversely in the data 32n. As shown, the transient temperature of the second semiconductor element 32 is highest. That is, the influence of the heat generated from the first semiconductor element 31 on the second semiconductor element 32 is the largest, as in the above-described trend of the transient temperature change shown in FIG.

  On the other hand, when the first notch 211 is disposed in the first die pad 31, the transient temperature of the first semiconductor element 31 increases as shown in the data 31av, but conversely in the data 32av. As shown, the transient temperature of the second semiconductor element 32 decreases. That is, the influence of the heat generated from the first semiconductor element 31 on the second semiconductor element 32 can be reduced. Further, as shown in data 31d, 31e, and 31f, although the transient temperature of the first semiconductor element 31 gradually increases as the width W1 of the first notch 211 increases, the data As indicated by 32d, 32e, and 32f, the transient temperature of the second semiconductor element 32 is low without much difference.

  Based on the above experimental results, in the semiconductor device 1 according to this example, the first notch 211 is arranged between the first semiconductor element 31 and the second semiconductor element 32 of the first die pad 21. The second notch 212 having the same structure (the same size) as the first notch 211 is disposed between the third semiconductor element 33 and the fourth semiconductor element 34. The length L1 of each of the first notch 211 and the second notch 212 is such that the opposing surfaces of the first semiconductor element 31 and the second semiconductor element 32, the third semiconductor element 33 and the fourth semiconductor, respectively. The length is set to 50% or more on the surface facing the element 34 to reduce the temperature interference between adjacent ones, and the heat dissipation path extends from the first surface 21A of the first die pad 21 to the second surface 21B. In order to avoid an increase in thermal resistance, the length is set so as not to exceed 100%. The width W1 of each of the first notch 211 and the second notch 212 is such that the first semiconductor element 31 and the second semiconductor element 32 are adjacent to each other, the third semiconductor element 33 and the fourth semiconductor. In order to reduce the temperature interference between the adjacent elements 34 and to avoid an increase in the thermal resistance of the heat dissipation path from the first surface 21A to the second surface 21B of the first die pad 21, It is set within a range of 0.5 to 1.0 with respect to the thickness t1 of one die pad 21.

  Furthermore, in the semiconductor device 1 according to the present embodiment, as shown in FIG. 1, the second semiconductor element 32 and the third semiconductor element 33 located in the central portion of the first die pad 21 are arranged between the second semiconductor element 32 and the third semiconductor element 33. A third cutout 213 having a length L2 that is longer in the second direction Y than the length L1 of the first cutout 211 and the second cutout 212 is provided. The center portion of the first die pad 21 corresponds to the center portion of the resin sealing body 5, and the heat generated from each of the second semiconductor element 32 and the third semiconductor element 33 is easily trapped compared to the peripheral portion, Mutual temperature interference is likely to occur.

  The third cutout 213 is set to a length L3 that is 100% or more on both opposing surfaces so as not to cause temperature interference between the second semiconductor element 32 and the third semiconductor element 33 as much as possible. ing. In the present embodiment, the length L2 of the third notch 213 is set to, for example, 7.6 mm to 7.8 mm from the first side surface 21C of the first die pad 21 in the second direction Y.

  Further, the width W2 of the third notch 213 decreases the thermal resistance around the third notch 213 in the heat dissipation path from the first surface 21A to the second surface 21B of the first die pad 21. In order to increase the cross-sectional area of the heat dissipation path, the width W2 is set to be slightly smaller than the width W1 of the first notch 211 and the second notch 212. Here, the width W2 of the third notch 213 is within the range of 0.5 to 1.0 with respect to the thickness t1 of the first die pad 21, and is, for example, 1.5 mm to 1.7 mm. Is set.

  Further, on the first surface 21A side of the first die pad 21, a groove 202 is formed between the first side surface 21C1 of the first die pad 21 and each of the first semiconductor element 31 to the fourth semiconductor element 34. It is arranged. The groove 202 is disposed for the purpose of allowing the resin sealing body 5 to bite and firmly attaching the first lead 23 to the resin sealing body 5. Further, the groove 202 reduces the cross-sectional area of the heat dissipation path in the second direction Y of the first die pad 21 and increases the thermal resistance. That is, the heat generated from each of the first semiconductor element 31 to the fourth semiconductor element 34 can be reduced by the groove 202 from being transmitted to the second die pad 22 side (control circuit 35 side).

  In the semiconductor device 1 according to the present embodiment, a total of four semiconductor elements of the first semiconductor element 31 to the fourth semiconductor element 34 are mounted on the first surface 21A of the first die pad 21. However, a total of six semiconductor elements including two more can be mounted on the first die pad 21. In FIG. 1, on the left side of the first semiconductor element 31, a fourth notch 214 is provided in the first die pad 21, and on the right side of the fourth semiconductor element 34, the first die pad 21 has a first notch. Five notches 215 are provided. The fourth notch 214 and the fifth notch 215 are set to have the same length L1 and width W1 as the length L1 and the width W1 of the first notch 211 and the second notch 212 described above. ing.

[Configuration of the first lead 23]
As shown in FIGS. 1 to 3, the first lead 23 faces the second side surface 21 </ b> C <b> 2 of the first die pad 21, and a plurality of the first leads 23 are arranged along the second side surface 21 </ b> C <b> 2. In FIG. 1, the first lead 23 (N1) arranged at the leftmost end, then the first lead 23 (S1), the first lead 23 (S2), the first arranged sequentially in the first direction X, The inner portions of the lead 23 (S3), the first lead 23 (S4), and the first lead 23 (N2) arranged on the rightmost side are fixed from the second side surface 21C2 of the first die pad 21. The first die pad 21 is electrically insulated from the first die pad 21.

  Here, the inner portion is a portion covered with the resin sealing body 5 of the first lead 23. The outer portion is a portion protruding from the resin sealing body 5 of the first lead 23. The most distal end portion of the outer portion is used as a terminal when mounted on a mounting board or other electronic device.

  The first leads 23 (N1) and 23 (N2) are used as empty terminals (empty pins). The first lead 23 (S 1) is used as a terminal for supplying a source current to the first semiconductor element 31. The second lead 23 (S 2) is used as a terminal for supplying a source current to the second semiconductor element 32. The third lead 23 (S3) is used as a terminal for supplying a source current to the third semiconductor element 33. The fourth lead 23 (S4) is used as a terminal for supplying a source current to the fourth semiconductor element 34.

  In FIG. 1, the first lead 23 (D1) disposed between the first leads 23 (N1) and 23 (S1) on the left side is integrally formed on the left side of the first die pad 21. They are connected and electrically connected. On the right side, the first lead 23 (D3) disposed between the first leads 23 (S4) and 23 (N2) is integrally formed on the right side of the first die pad 21, connected and electrically connected. Connected. Similarly, the first lead 23 (D2) disposed between the first leads 23 (S2) and 23 (S3) at the center is integrally formed at the center of the first die pad 21 and connected. And are electrically connected. These first leads 23 (D 1), 23 (D 2), and 23 (D 3) are all used as a common terminal for supplying a drain current to the first semiconductor element 31 to the fourth semiconductor element 34. .

  The first lead 23 has a thickness of 0.5 mm, for example, and has a lead width of 2.0 mm, for example, excluding the bonding region on the first die pad 21 side of the inner part. The first lead 23 is cut from the same lead frame connected together with the first die pad 21 in the manufacturing process, and is made of the same material as the first die pad 21.

  In the inner portion of the first lead 23 on the first surface 21A side of the first die pad 21, a groove 201 is disposed at the boundary portion of the bonding region. The groove 201 is mainly disposed for the purpose of allowing the resin sealing body 5 to bite and firmly attaching the first lead 23 to the resin sealing body 5.

  The region of the first die pad 21 where the first semiconductor element 31 is mounted and the first lead 23 (D1) connected to the second side surface 21C2 of the first die pad generate the first heat dissipation path R1. . As described above with reference to FIG. 7, the first notch 211 is disposed between the first semiconductor element 31 and the second semiconductor element 32 of the first die pad 21. Heat generated from the semiconductor element 31 is not easily propagated to the second semiconductor element 32 through the first die pad 21. The heat generated from the first semiconductor element 31 is released through a heat dissipation path from the first surface 21A of the first die pad 21 to the back surface of the resin sealing body 5 through the second surface 21B, and The first heat dissipation including the first lead 23 (D1) disposed in the direction opposite to the first notch 211 with the first semiconductor element 31 as the center and disposed in the vicinity of the first semiconductor element 31. Released through route R1.

  Similarly, the region where the fourth semiconductor element 34 of the first die pad 21 is mounted and the first lead 23 (D3) connected to the second side surface 21C2 of the first die pad are connected to the second heat dissipation path R2. Is generated. A second notch 212 is disposed between the third semiconductor element 33 and the fourth semiconductor element 34 of the first die pad 21, and heat generated from the fourth semiconductor element 34 is generated by the first semiconductor element 34. Propagation through the die pad 21 to the third semiconductor element 33 is difficult. The heat generated from the fourth semiconductor element 34 is released through a heat dissipation path from the first surface 21A of the first die pad 21 to the back surface of the resin sealing body 5 through the second surface 21B, and The second heat dissipation including the first lead 23 (D3) disposed in the direction opposite to the second notch 212 with the fourth semiconductor element 34 as the center and disposed in the vicinity of the fourth semiconductor element 34. Released through route R2.

  Further, the first lead 23 (D2) connected to the region of the first die pad 21 where the second semiconductor element 32 and the third semiconductor element 33 are mounted and the second side surface 21C2 of the first die pad is provided. A third heat dissipation path R3 is generated. A first notch 211 is disposed between the first semiconductor element 31 and the second semiconductor element 32 of the first die pad 21, and heat generated from the second semiconductor element 32 is generated by the first semiconductor element 31. Propagation through the die pad 21 to the first semiconductor element 31 is difficult. Similarly, a second notch 212 is disposed between the third semiconductor element 33 and the fourth semiconductor element 34 of the first die pad 21, and the heat generated from the third semiconductor element 33 is Propagation through the first die pad 21 to the fourth semiconductor element 34 is difficult. The heat generated from the second semiconductor element 32 is released through a heat dissipation path from the first surface 21A of the first die pad 21 to the back surface of the resin sealing body 5 through the second surface 21B, and The third heat radiation including the first lead 23 (D2) disposed in the direction opposite to the first notch 211 with the second semiconductor element 32 as the center and disposed in the vicinity of the second semiconductor element 32. Released through route R3. In addition, heat generated from the third semiconductor element 33 is released through a heat dissipation path from the first surface 21A of the first die pad 21 to the back surface of the resin sealing body 5 through the second surface 21B. A third lead including a first lead 23 (D3) disposed in the direction opposite to the second notch 212 with the third semiconductor element 33 as a center and disposed in the vicinity of the third semiconductor element 33. It is discharged through the heat dissipation path R3.

  In the third heat dissipation path R3, the heat generated from the second semiconductor element 32 does not affect the third semiconductor element 33, or the heat generated from the third semiconductor element 33 is the second semiconductor. In order not to affect the element 32, the first die pad 21 is provided with a third notch 213 having a length L2 extending from the first side surface 21C1 to the second side surface 21C2.

[Configuration of Second Die Pad 22]
As shown in FIGS. 1 and 2, the second die pad 22 is disposed with the first side surface 22C1 facing the first side surface 21C1 of the first die pad 21 and spaced apart. In this embodiment, the separation dimension between the first side surface 21C1 of the first die pad 21 and the first side surface 22C1 of the second die pad is set to 0.3 mm-0.5 mm, for example. The length of the second die pad 22 in the first direction X is set to, for example, 26.0 mm-30.0 mm, and the width in the second direction Y, that is, from the first side surface 22C1 to the second side surface 22C2 facing it. Is set to 4.2 mm to 4.4 mm, for example. The thickness of the second die pad 22 in the third direction Z is the same as the thickness of the first lead 23.

  The control circuit 35 is disposed at the center of the first surface 22A of the second die pad 22. In the region where the control circuit 35 is mounted, the first side surface 22C1 of the second die pad 22 is opposed to the third notch portion 213 provided in the first die pad 21. That is, by disposing the third notch 213, the facing area between the first side surface 21C1 of the first die pad 21 and the first side surface 22C1 of the second die pad 22 can be reduced. In particular, the heat resistance of the heat transfer path from the second semiconductor element 32 and the third semiconductor element 33 to the second die pad 22 through the first die pad 21 can be increased. Therefore, the influence of the heat generated from the second semiconductor element 32 and the third semiconductor element 33 on the control circuit 35 can be reduced.

  In the second die pad 22, a slit 203 penetrating from the first surface 22 </ b> A to the second surface 22 </ b> B facing it is disposed between the control circuit 35 and the wiring board 36. The slit 203 allows the bonding between the resin sealing body 5 on the first surface 22A side of the second die pad 22 and the resin sealing body 5 on the second surface 22B side, and allows the second die pad 22 and the resin sealing to be bonded. Adhesiveness with the stationary body 5 can be improved. Further, the slit 203 is formed from the heat transfer path of the heat generated from the first semiconductor element 31 to the control circuit 35 through each of the first die pad 21 and the second die pad 22, and from the fourth semiconductor element 34. It is possible to increase the thermal resistance of the heat transfer path through the first die pad 21 and the second die pad 22 to the control circuit 35 by the generated heat, and to reduce the influence of the heat on the control circuit 35. it can.

  The second die pad 22 is cut from the same lead frame connected together with the first die pad 21 in the manufacturing process, and is made of the same material as the first die pad 21.

[Configuration of Second Lead 24]
As shown in FIGS. 1 to 3, the second leads 24 face the second side surface 22C2 of the second die pad 22, and a plurality of second leads 24 are arranged along the second side surface 21C2. In FIG. 1, the second lead 24 arranged at the leftmost end, the second lead 24 arranged at the left central portion, the second lead 24 arranged at the right central portion, and the second lead 24 arranged at the rightmost portion. Each of the leads 24 is formed integrally with the second die pad 22 and is connected and electrically connected. These second leads 24 function as suspension leads. The other second leads 24 are used as signal terminals, power supply terminals, or empty terminals.

  The second lead 24 is cut from the same lead frame connected together with the first die pad 21 in the manufacturing process, and is made of the same material as the first die pad 21. The second lead 24 is set to the same thickness as the first lead 23, but has a small current capacity, and is set to a lead width of 0.5 mm to 0.7 mm, for example.

  In the inner portion of the second lead 24, a groove 204 is disposed at the boundary portion of the bonding region. Similar to the groove 201 of the first lead 23, the groove 204 is disposed mainly for the purpose of allowing the resin sealing body 5 to bite and firmly attaching the second lead 24 to the resin sealing body 5. ing.

[Lead frame configuration]
Here, the lead frame 2 shown in FIG. 12 is used in the manufacturing process (assembly process) of the semiconductor device 1 according to the present embodiment. In the lead frame 2, the first die pad 21, the second die pad 22, the first lead 23, and the second lead 24 are connected to the outer frames 25 and 26, and they are integrally configured. . Here, in this embodiment, a multiple lead frame 2 capable of simultaneously manufacturing a plurality of semiconductor devices 1 in the first direction X is used.

  The outer frame 25 and the outer frame 26 are opposed to each other in the second direction Y, and extend in the first direction X. A first lead 23 is connected to the outer frame 25, and a second lead 24 is connected to the outer frame 26. The outer frame 25 is provided with positioning holes 251 that are used in the manufacturing process, and the outer frame 26 is provided with positioning holes 261, 262, and 263 that are similarly used.

  The first leads 23 adjacent to each other in the first direction X are connected to each other via a connecting portion 28. Similarly, the second leads 24 adjacent in the first direction X are connected to each other via a connecting portion 29. Each of the connecting portions 28 and 29 has a function as a dam for blocking outflow of the resin when the resin sealing body 5 is molded, and is cut and removed after the resin sealing body 5 is molded.

  A region in which one semiconductor device 1 is manufactured and a region in which another semiconductor device 1 adjacent in the first direction X is formed are connected to each other by an inner frame 27. Similarly, the connecting portion is cut and removed after the resin sealing body 5 is molded.

[Configuration of Resin Encapsulant 5]
As shown in FIGS. 1 to 3, the resin sealing body 5 is mounted on the first die pad 21, the first semiconductor element 31 to the fourth semiconductor element 34 mounted on the first die pad 21, the second die pad 22, and the second die pad 22. The control circuit 35, the wiring board 36, the inner part of the first lead 23, and the inner part of the second lead 24 are covered. A transfer mold method is used for manufacturing the resin sealing body 5. For the resin sealing body 5, for example, a thermosetting epoxy resin is used.

  The length of the resin sealing body 5 in the first direction X is set to 47.2 mm to 47.6 mm, for example, and the width in the second direction Y is set to 19.0 mm to 19.4 mm, for example. The thickness of the resin sealing body 5 is set to 4.3 mm-4.5 mm, for example. The thickness on the first surface 21A of the first die pad 21 of the resin sealing body 5 is set to 1.8 mm-2.0 mm, for example. The thickness on the second surface (back surface) 21B of the resin sealing body 5 is thinner than the thickness on the first surface 21A and is thinner than the thickness of the first die pad 21, for example, 0. .4mm-0.6mm.

[Features of semiconductor devices]
As described above, in the semiconductor device 1 according to the present embodiment, since the plurality of first semiconductor elements 31 to the fourth semiconductor elements 34 are mounted on one common first die pad 21, each semiconductor element Compared with the case where the die pad is divided, the overall size can be reduced. Furthermore, in the semiconductor device 1 according to the present embodiment, the wire lengths of the first wire 41 and the second wire 42 can be shortened by realizing the miniaturization, and the signal propagation speed can be increased. As a result, the operation speed can be increased.

  Further, in the semiconductor device 1 according to the present embodiment, the first die pad 21 includes the first notch 211, the second notch 212, and the third notch 213, so that the first semiconductor element 31 is provided. That is, the temperature interference between the adjacent fourth semiconductor elements 34 can be reduced. In addition, in the semiconductor device 1 according to the present embodiment, the first die pad 21 is thickened, the thickness of the first die pad 21 of the resin sealing body 5 on the second surface 21B side is thinned, and the resin sealing is performed. The first heat dissipation path R1-the third heat dissipation path using the first leads 23 (D1), 23 (D2), and 23 (D3) while securing the heat dissipation path to the rear surface side of the stationary body 5 Since R3 is provided, temperature interference between adjacent first to fourth semiconductor elements 31 to 34 can be reduced. In particular, in the semiconductor device 1 according to the present embodiment, the length L2 of the third notch 213 in the central portion of the resin sealing body 5 is set to the length L2 of the first notch 211 and the second notches in the peripheral portion of the resin sealing body 5. Since the length L <b> 1 of the second notch 212 is set to be long, temperature interference between the second semiconductor element 32 and the third semiconductor element 33 can be reduced. Accordingly, variations in output characteristics of the first semiconductor element 31 to the fourth semiconductor element 34 due to temperature interference between adjacent ones can be reduced.

  Further, in the semiconductor device 1 according to the present embodiment, the control circuit 35 is disposed in the region facing the third notch 213 of the first die pad 21, so that the second semiconductor element 32, the second The influence of heat generated from each of the three semiconductor elements 33 can be reduced. Therefore, variations in the output characteristics of the control circuit can be reduced.

  Furthermore, in the semiconductor device 1 according to the present embodiment, a part of the first side surface 21C1 of the first die pad 21 that is closest to the region where the control circuit 35 of the second die pad 22 is mounted is cut out. Since the three cutout portions 213 are provided, the propagation of heat from the first die pad 21 to the second die pad 22 can be suppressed.

  Then, by using the lead frame 2 according to the present embodiment, the semiconductor device 1 having such an effect can be manufactured.

[Other Examples]
Although the present invention has been described by way of example as described above, the discussion and drawings that form part of this disclosure do not limit the invention. The present invention can be applied to various alternative embodiments, examples, and operational technologies. For example, although the final lead shape of the semiconductor device 1 has not been described in the above-described embodiment, the shape of the outer portion of each of the first lead 23 and the second lead 24 is a pin insertion type, surface mount Any type.

  In addition, the semiconductor device 1 according to the above-described embodiment includes the first lead 23 and the second lead 24 arranged in two directions on the two opposing side surfaces of the resin sealing body 5. The present invention can be applied to a semiconductor device in which leads are arranged in one direction on one side surface of the stationary body 5 and a semiconductor device in which leads are arranged in four directions on four side surfaces of the resin sealing body 5. Further, in the semiconductor device 1 according to the above-described embodiment, the first lead 23 (D1) to the first lead 23 that construct the first heat dissipation path R1 to the third heat dissipation path R3 of the first die pad 21. (D3) is not limited to the second side surface 21C2 facing the first side surface 21C1 of the first die pad 21, but is disposed on a side surface different from the first side surface 21C1 adjacent to the first side surface 21C1. Also good.

The present invention, while realizing a high-speed compact and operating speed, the semiconductor element due to thermal interference can be widely applied to semiconductor equipment capable of reducing variations in at least one of the output characteristics of the circuit .

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Lead frame 21 ... 1st die pad 22 ... 2nd die pad 23 ... 1st lead 24 ... 2nd lead 211 ... 1st notch part 212 ... 2nd notch part 213 ... 3rd Notch 31 ... first semiconductor element 32 ... second semiconductor element 33 ... third semiconductor element 34 ... fourth semiconductor element 35 ... control circuit 36 ... wiring substrate 41 ... first wire 42 ... second Wire 5 ... Resin sealing body

Claims (2)

A first semiconductor element and a second semiconductor element that are spaced apart in a first direction;
Extending in the first direction, mounting the first semiconductor element and the second semiconductor element on a first surface, and from a first side surface in a second direction intersecting the first direction A first die pad having a notch reaching between the first semiconductor element and the second semiconductor element;
A lead connected to a second side surface different from the first side surface of the first die pad;
Equipped with a,
A thickness of the first die pad from the first surface to a second surface opposite to the first surface is larger than a thickness of the lead . A resin seal embedded in the notch, covering the first semiconductor element, the second semiconductor element, the first surface of the first die pad, and the second surface opposite to the first surface. A further stop,
The thickness of the resin sealing body on the second surface of the first die pad is smaller than the thickness from the first surface of the first die pad to the second surface; The semiconductor device according to claim 1 , wherein a thickness of the resin sealing body is smaller than a thickness on the first surface of the first die pad.