JP3159246B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a refresh device for refreshing a DRAM included in a semiconductor memory device.

[0002]

2. Description of the Related Art Some recent semiconductor memory devices access data stored in a memory in block units. In the semiconductor memory device, the inside of the memory is divided into two or more banks and activated separately, so that data can be transferred seamlessly over a bus for a long time.

FIG. 8 shows an example of a DRAM system which is one of such semiconductor memory devices, and FIG. 9 shows a timing chart of data transfer. Since the banks A and B are alternately activated and data can be transferred without interruption via the input / output buffer, the bus is effectively used. In such a system, it is effective to include the start address and the number of consecutive accesses in the memory access request command as shown in FIG. By doing so, the command issuance can be minimized.

Now, it is necessary to refresh the DRAM within a certain period. As a method of controlling refresh, there is an auto refresh function. A DRAM having this auto-refresh function has an address counter and a timer inside, and when a certain period required for refresh is detected based on the timer, the DRAM refreshes the address whose value of the address counter is incremented and requests an access request. Returns a busy signal. FIG. 11 shows a timing chart in such a case.

[0005] Arbitration of refresh and access requests involves
Although the busy signal is often used as described above, since the memory controller is made to wait until the refresh is completed, the bus use efficiency is reduced.

A method for solving this problem at the system level is described in Japanese Patent Application Laid-Open No. Hei 4-362593. This will be briefly described with reference to FIG. 12. In a multiprocessor system, a memory controller of a shared memory unit monitors a state of a shared bus, detects that communication is performed between processor elements, and performs a shared memory The DRAM constituting the unit is refreshed. This reduces the probability of collision with refresh when the shared memory is actually accessed.

[0007]

As described in the prior art, if the refresh and access arbitration of the DRAM are performed by a busy signal, the bus use efficiency is reduced. In the case of a DRAM having a plurality of banks and issuing an access request by designating a start address and the number of repetitions, the DRAM may be accessed from one device for a long time, and the probability of collision between access and refresh is high. Had become.

On the other hand, the method in which the memory controller determines the state of the shared bus has no problem when the entire memory system can be controlled singly, such as in a shared memory of a multiprocessor system. However, if the individual DRAMs are directly connected to the bus line, each DR
Since it is necessary to apply separate control signals to the AM, there is a problem that the number of system wirings increases. In the case of a DRAM including a defective address, address conversion is performed internally, and it is difficult to externally control the refresh address.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to reduce collision between refresh and access requests in a semiconductor memory device having an auto-refresh mechanism, having a plurality of banks inside, and being connected to a bus line. is there.

[0010]

According to the present invention, in a semiconductor memory device which has an auto-refresh mechanism, is connected to a bus line, and is used according to a protocol, an access request is prioritized and a self-refresh request generated internally during the request is given. And a refresh controller that outputs the refresh mode signal during the next minimum access time to itself when an access to another chip on the same bus occurs. In addition, a semiconductor memory device characterized in that the count value of the refresh flag counter is reduced by the refresh mode signal.

The lower limit value of the count value of the first circuit means can be set externally.

Preferably, a plurality of banks are provided inside.

According to the present invention, a protocol decoder for generating a continuous access count signal of another device indicating the value of the continuous access count of another device, a timer for generating a pulse signal at a constant interval, and a first indicating the average interval time of refreshing.
A first reference value register for generating a reference value signal, a refresh flag counter for counting the pulse signal with reference to the first reference value signal and generating a count value signal, the other device continuous access number signal, A semiconductor memory, comprising: a refresh controller that generates a refresh mode signal in accordance with a first reference value signal and the count value signal; and a DRAM central unit that performs refresh by referring to a state of the refresh mode signal. A device is obtained.

According to the present invention, in a refresh method for a semiconductor memory device which has an auto-refresh mechanism and is connected to a bus line and used according to a protocol, an access request is prioritized and a self-refresh request generated internally during the access request is prioritized. The flag is counted, and when an access to another chip on the same bus occurs, a next minimum access time to itself is obtained, a refresh mode signal is output during that time, and the refresh flag counter is used by the refresh mode signal. , The refresh method is characterized in that the count value is reduced.

According to the present invention, the other device consecutive access number signal indicating the value of the continuous access number of the other device is generated, the pulse signal is generated at a constant interval, and the first refresh time interval representing the average refresh time. Generating a reference value signal; counting the pulse signal with reference to the first reference value signal to generate a count value signal; the other device continuous access count signal, the first reference value signal, Generating a refresh mode signal in response to a count value signal; and refreshing a central portion of the DRAM with reference to a state of the refresh mode signal. can get.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a semiconductor memory device having a refresh device according to an embodiment of the present invention will be described.

This refresh device is for performing a known refresh operation on the DRAM 107 included in the semiconductor memory device.
A self-refresh timer 101 for generating I,
And a self-refresh timer 101 and a first reference value register 102 which constantly generate a 10-bit wide first reference value signal UPL representing a refresh average interval time which is a reference value of Connected
A refresh flag counter 103 which counts the pulse signal FLGI and generates a count value. The refresh flag counter 103 has an arithmetic function, and receives a pulse signal FLGDI and a first signal in response to a refresh completion signal FLGD indicating that refresh has been performed once.
Is subtracted from the count value on the basis of the reference value signal UPL to generate a 10-bit width count value signal FLGS representing the count value. The first reference value is determined by the holding characteristics of each device, and is adjusted at the time of manufacture by cutting a fuse in the first reference value register 102.

This semiconductor device has a protocol decoder 1
04 and the refresh controller 105. The protocol decoder 104 is connected to the bus DQi, and outputs various signals according to signals obtained through the bus DQi and indicating that another device has been accessed, that is,
Generate RWM, ADD, LEN, and CONTSET. Here, ADD is an address signal, LEN is a 4-bit other device continuous access count signal indicating the value of the continuous access count of another device, and CONTSET is a trigger signal for capturing the signal LEN.

The refresh controller 105 includes a first reference value register 102, a refresh flag counter 1
03, a protocol decoder 104, and a DRAM central unit 107, and as will become clear later, a count value signal FLGS, a first reference value signal UPL, an address signal ADD, another device continuous access count signal LEN, and a trigger. In response to signal CONTSET, refresh mode signal RFM is generated in addition to refresh completion signal FLGD described above. With reference to the state of the refresh mode signal RFM, the DRAM central unit 107 performs refresh. The data buffer 106 is connected to the buses DQi and DRA.
It is located between the M center 107 and contributes to data exchange.

The refresh controller 105 will be described with reference to FIGS. 2 and 3 in addition to FIG.

The refresh controller 105 includes a continuous refresh counter 201, a determiner 202, a first comparator 203, a second comparator, and a second reference value register 20.
5, flip-flop 206, rising edge detector 2
07, and a pulse generator 208. The continuous refresh counter 201 is the protocol decoder 104
And the other device continuous access count signal LEN, the trigger signal CONTSET, and the pulse signal CNTDE generated by the pulse generator 208.
According to C, a 4-bit continuous refresh counter value signal RFCS representing the value of the continuous refresh counter is generated. Continuous refresh counter value signal RFC
Until S becomes 0, the refresh mode signal RFM is in the active state. The determiner 202 is connected to the continuous refresh counter 201, determines whether the continuous refresh counter value signal RFCS becomes 0, and generates a determination result signal.

The second reference value register 205 is connected to the protocol decoder 104, and in a register value setting operation mode, the signal RGSET is activated to enable the address signal AD.
A part of D is taken in as a second reference value. This second reference value is calculated with the above-mentioned first reference value, and is converted into a negative relative value such as minus five times the first reference value. The second reference value register 205 generates a second reference value signal. The first comparator 203 is connected to the first reference value register 102 and the refresh flag counter 103, and outputs the first reference value signal UPL and the count value signal FLG.
And S to generate a first comparison result signal. The second comparator 204 is connected to the refresh flag counter 103 and the second reference value register 205, compares the second reference value signal with the count value signal FLGS, and generates a second comparison result signal. The determination result signal and the second comparison result signal are supplied to an AND circuit 209. AND circuit 20
9 and the first comparison result signal are supplied to the flip-flop 206 through the OR circuit 210.

In this way, the second reference value and the count value are compared by the second comparator 204 according to the second reference value signal and the count value signal FLGS, and if the count value falls below the second reference value, 202 to flip-flop 206
Invalidate the route to. In a system that may perform continuous access for a long time, the absolute value of the second reference value needs to be set large. However, if the value is set too large, unnecessary refresh is performed, and the second reference value has an optimum value depending on the system.

The rising edge detector 207 is connected to the flip-flop 206 and receives the refresh mode signal R
The rising edge of FM is detected, and a refresh completion signal FLGD is generated. The DRAM central unit 107 performs refresh while the refresh mode signal RFM is being output. A signal for resetting the flip-flop 206 in which the refresh mode signal RFM is latched every refresh cycle, that is, the pulse generator 2
The pulse signal CNTDEC generated at 08 is output at intervals of the time required for the refresh cycle operation, and decrements the continuous refresh counter value signal RFCS.

Referring to FIG. 4, count value signal FLGS
The relationship between the count value represented by and the time will be described. While the other device is performing the read operation, the own device performs refresh within a range where the count value does not fall below the second reference value. The count value is reduced by the first reference value by the pulse of the refresh completion signal FLGD.

On the other hand, no refresh is performed while the device is being accessed for a read operation or the like.

FIG. 5 shows a case where continuous access to the own device takes a long time and the count value exceeds the first reference value. Once the access is cut off, the refresh is compulsorily performed until the value falls below the first reference value. The comparison between the first reference value and the count value is performed by the first comparator 203. The output of the first comparator 203 has an activation level of “HIGH”, and thus sets the flip-flop 206 regardless of the values of the decision unit 202 and the second comparator 204.

Naturally, a long-term continuous access that exceeds the data holding time of the cell even if the refresh operation is forcibly performed is prohibited on the specifications.

Referring to FIG. 6, the overall operation of the refresh device will be described.

When a command is input in step SA1,
In step SA2, it is determined whether or not the command is its own device number. If it is not its own device number, the operation analysis of another device is started in step SA3. Subsequent operations will be described in the next sentence.

If it is determined in step SA2 that the command is its own device number, the flow shifts to step SA4 to determine whether or not refresh is being performed. During the refresh, a busy signal is output in step SA5, and the process returns to step SA4.

If refresh is not being performed in step SA4, the flow advances to step SA6 to perform a read / write operation and end the operation.

Referring to FIG. 7 together with FIG. 1 and FIG. 2, a case where the operation analysis of another device is started will be described. In step SB1, the number of times that refreshing is possible is set in the continuous refresh counter 201. Moving to Step SB2, the count value of the continuous refresh counter 201 becomes 0
It is determined whether or not. When the count value is 0, the operation ends.

When the count value of the continuous refresh counter 103 is not 0, the process proceeds to step SB3, where the continuous refresh counter 103 is decremented. Further, the process proceeds to step SB4, and when the count value of the refresh flag counter 103 is equal to or smaller than the second reference value, the process returns to step SB2 after waiting for a time corresponding to the refresh operation in step SB5.

If the count value of the refresh flag counter 103 is not equal to or smaller than the second reference value, step S
The refresh operation is started in B6, and further in step SB
At 7, the refresh operation ends, and the process returns to step SB2.

[0036]

As described above, the present invention relates to a DRAM.
Since the probability of occurrence of a collision between the refresh and the access occurs, the bus use efficiency increases. In particular, in a multi-bank system, an access request is issued by designating a start address and the number of repetitions, so that a single device may be accessed for a long time. Thus, it is possible to avoid being in a busy state for a long time after a long access.

Further, since the present invention performs these controls on the DRAM, there is an advantage that it is not necessary to provide separate control signal lines for each DRAM, and the number of system wirings is not increased.

Further, according to the present invention, since the second reference value can be arbitrarily changed from the outside, unnecessary refresh operations can be prevented. Further, since the second reference value is a relative value from a value determined based on the holding characteristics of each device, an unnecessary margin is not generated, so that unnecessary refresh operation can be prevented. As a result, Current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a refresh device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a refresh controller included in the refresh device of FIG. 1;

FIG. 3 is a time chart illustrating signals of respective units of the refresh controller of FIG. 2;

FIG. 4 is a graph illustrating a relationship between a count value of a refresh flag counter included in the refresh device of FIG. 1 and time.

FIG. 5 is a graph showing a case where continuous access to the device takes a long time and the count value exceeds a first reference value.

FIG. 6 is a flowchart for explaining the overall operation of the refresh device in FIG. 1;

FIG. 7 is a flowchart for explaining an operation when an operation analysis of another device is started in the refresh device of FIG. 1;

FIG. 8 is a layout diagram of a memory in a conventional system.

FIG. 9 is a timing chart at the time of a read operation of a conventional example.

FIG. 10 shows a conventional example of command input bit allocation.

FIG. 11 is a timing chart when BUSY is output in a conventional example.

FIG. 12 is an example of a multiprocessor system.

[Explanation of symbols]

 Reference Signs List 101 self-refresh timer 102 first reference value register 103 refresh flag counter 104 protocol decoder 105 refresh controller 106 data buffer 107 DRAM central part 201 continuous refresh counter 202 determiner 203 first comparator 204 second comparator 205 second Reference value register 206 flip-flop 207 rising edge detector 208 pulse generator

Claims (6)

(57) [Claims] 1. A semiconductor memory device having an auto-refresh mechanism connected to a bus line and used according to a protocol, wherein a refresh flag counter for giving priority to an access request and counting a self-refresh request flag generated internally during the access request; A refresh controller for determining the next minimum access time to itself when another chip on the same bus is accessed, and outputting a refresh mode signal during that time; A semiconductor memory device for reducing a count value of a counter. 2. The semiconductor memory device according to claim 1, wherein a lower limit value of a count value of said refresh flag counter can be externally set. 3. The semiconductor memory device according to claim 1, further comprising a plurality of banks. 4. A protocol decoder for generating a continuous access count signal of another device indicating a value of the continuous access count of another device, a timer for generating a pulse signal at a constant interval,
A first reference value register that generates a first reference value signal representing an average interval time of refresh, a refresh flag counter that counts the pulse signal with reference to the first reference value signal and generates a count value signal, A refresh controller that generates a refresh mode signal according to the other device continuous access number signal, the first reference value signal, and the count value signal; and a DR that performs refresh by referring to a state of the refresh mode signal.
A semiconductor memory device comprising an AM center. 5. A refresh method for a semiconductor memory device having an auto-refresh mechanism connected to a bus line and used according to a protocol, wherein an access request is prioritized and a flag of a self-refresh request generated during the access request is counted. When an access to another chip on the same bus occurs, the next minimum access time to itself is determined, a refresh mode signal is output during that time, and the count value of the refresh flag counter is calculated by the refresh mode signal. A refresh method characterized in that it is reduced. 6. A method of generating a continuous access count signal of another device indicating a value of the continuous access count of another device, generating a pulse signal at a constant interval, and generating a first reference value signal indicating an average refresh interval time. Generating, counting the pulse signal with reference to the first reference value signal to generate a count value signal, the other device continuous access count signal, the first reference value signal, the count value signal, A refresh method for a semiconductor memory device, comprising: generating a refresh mode signal in response to a refresh mode; and refreshing a central portion of the DRAM with reference to the state of the refresh mode signal.