JP3146452B2 - Surface mount type LED element and method of manufacturing the same - Google Patents
Surface mount type LED element and method of manufacturing the sameInfo
- Publication number
- JP3146452B2 JP3146452B2 JP22611395A JP22611395A JP3146452B2 JP 3146452 B2 JP3146452 B2 JP 3146452B2 JP 22611395 A JP22611395 A JP 22611395A JP 22611395 A JP22611395 A JP 22611395A JP 3146452 B2 JP3146452 B2 JP 3146452B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- led chip
- insulating
- element substrate
- plate material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Description
【０００１】[0001]
【発明の属する技術分野】本発明はチップマウントとも
称され、例えばプリント回路基板などに取付穴を設ける
ことなく面で実装することを可能とした構成のＬＥＤ
（発光ダイオード）素子に関するものであり、詳細には
製造方法に係るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is also referred to as a chip mount, for example, an LED having a configuration which enables mounting on a surface without providing mounting holes in a printed circuit board or the like.
The present invention relates to a (light emitting diode) element, and more specifically to a manufacturing method.
【０００２】[0002]
【従来の技術】従来のこの種の面実装型ＬＥＤ素子９０
の製造方法を工程の順に示すものが図９〜図１５であ
り、先ず最初の工程としては、図９に示すように、例え
ばガラスエポキシなど絶縁性基材の表裏の両面に銅箔８
１が貼着されたプリント回路基板などによる素子基板母
材８０に、適宜の間隔で表裏面に貫通するスロット８２
をプレス加工などにより形成する。2. Description of the Related Art A conventional surface mount type LED element 90 of this kind
9 to 15 show the manufacturing method in the order of steps. First, as shown in FIG. 9, as shown in FIG.
Slots 82 penetrating the front and back surfaces at appropriate intervals in an element substrate base material 80 such as a printed circuit board on which
Is formed by press working or the like.
【０００３】この状態では、素子基板母材８０の側面及
び上記で形成されたスロット８２の内面には導電性皮膜
が形成されていないので、無電解メッキなどの手段で前
記側面及びスロット８２の内面に銅などによる導電膜８
３を形成し、図１０に示すように、前記素子基板母材８
０の外面の全てが導電性皮膜で覆われるものとして表裏
面を電気的に接続する。In this state, since a conductive film is not formed on the side surface of the element substrate base material 80 and the inner surface of the slot 82 formed above, the inner surface of the side surface and the slot 82 is formed by means such as electroless plating. Conductive film 8 of copper or the like
3 is formed, and as shown in FIG.
The front and back surfaces are electrically connected assuming that the entire outer surface of the “0” is covered with the conductive film.
【０００４】次いで、図１１に示すように前記素子基板
母材８０の表面側のスロット８２間には、エッチングな
どの手段で前記銅箔８１を除去することで、パット部８
４と配線部８５とを形成し、同時に裏面側においてもス
ロット８２間で略長方形に銅箔８１を除去することで絶
縁部８６を形成し、これにより、素子基板母材８０が完
成する。Next, as shown in FIG. 11, the copper foil 81 is removed between the slots 82 on the front surface side of the element substrate base material 80 by means of etching or the like, so that the pad portion 8 is formed.
4 and the wiring portion 85 are formed, and at the same time, the insulating portion 86 is formed by removing the copper foil 81 in a substantially rectangular shape between the slots 82 also on the back surface side, whereby the element substrate base material 80 is completed.
【０００５】続いて、図１２に示すように前記パット部
８４にＬＥＤチップ９１を一方の極で例えば導電性接着
剤などによりマウントし、このＬＥＤチップ９１の他方
の極と前記配線部８５との配線を金線などワイヤ９２で
行い、更に、図１３に示すように前記ＬＥＤチップ９１
とワイヤ９２とを透明樹脂で覆いモールド部９３を形成
する。[0005] Subsequently, as shown in FIG. 12, an LED chip 91 is mounted on the pad portion 84 at one pole by, for example, a conductive adhesive, and the other pole of the LED chip 91 and the wiring section 85 are connected to each other. Wiring is performed by a wire 92 such as a gold wire, and further, as shown in FIG.
And the wire 92 are covered with a transparent resin to form a molded portion 93.
【０００６】そして、図１４に示すように前記素子基板
母材８０を夫々のＬＥＤチップ９１の中間の位置となる
切断線Ｄ切断を行えば、素子基板母材８０はスロット８
２の部分で個々の素子基板９４に分割され、図１５に示
す面実装型ＬＥＤ素子９０の複数が得られるものとな
る。Then, as shown in FIG. 14, the element substrate base material 80 is cut along a cutting line D at an intermediate position between the respective LED chips 91, so that the element substrate base material 80
The portion 2 is divided into individual element substrates 94, and a plurality of surface mount LED elements 90 shown in FIG. 15 are obtained.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、前記し
た従来の面実装型ＬＥＤ素子９０では、先ず、製造工程
においては前記スロット８２の内面などに導電膜８３を
形成するための無電解メッキなどの手段が加工コストが
高価で且つ加工時間も長いものであるので、前記素子基
板母材８０の生産性が低下し、結果として面実装型ＬＥ
Ｄ素子９０全体がコストアップする問題点を生じてい
る。However, in the above-mentioned conventional surface mount type LED element 90, first, in the manufacturing process, means such as electroless plating for forming a conductive film 83 on the inner surface of the slot 82 or the like is used. However, since the processing cost is high and the processing time is long, the productivity of the element substrate base material 80 is reduced, and as a result, the surface-mount LE
There is a problem that the cost of the entire D element 90 increases.
【０００８】また、前記素子基板９４は、有機部材であ
るガラスエポキシを基材とするプリント回路基板を利用
した素子基板母材８０から形成されるものであるので熱
伝導率が低く、この素子基板９４上にマウントされたＬ
ＥＤチップ９１に対しての放熱効果が不十分となり、面
実装型ＬＥＤ素子９０としての連続定格電流が減格さ
れ、暗い面実装型ＬＥＤ素子９０となる問題点も生じ、
これらの点の解決が課題とされるものとなっていた。Further, since the element substrate 94 is formed from an element substrate base material 80 using a printed circuit board having glass epoxy as an organic material as a base material, the element substrate 94 has a low thermal conductivity. L mounted on 94
The heat dissipation effect on the ED chip 91 becomes insufficient, the continuous rated current of the surface-mounted LED element 90 is reduced, and a problem that the surface-mounted LED element 90 becomes dark occurs.
The solution of these points has been an issue.
【０００９】[0009]
【課題を解決するための手段】本発明は前記した従来の
課題を解決するための具体的な手段として、夫々が所定
の板厚とされた導電性板材と絶縁性板材とを面方向に交
互に接合して得られたブロック体を前記面方向に直交す
る方向で適宜板厚と成るようにスライスして前記導電性
板材による導電部と絶縁性板材による絶縁部とが交互の
平行の帯状となる素子基板母材を形成し、この素子基板
母材の前記導電部には帯状の一方の縁寄りに所定ピッチ
として複数のＬＥＤチップをマウントすると共にこのＬ
ＥＤチップと、当該ＬＥＤチップがマウントされた導電
部の一方の縁と絶縁部を挾んで対峙する導電部の他の一
方の縁寄りとをワイヤで配線し、前記ＬＥＤチップとワ
イヤとを透明樹脂で覆い、その後に夫々のＬＥＤチップ
の所定ピッチ間と、導電部のＬＥＤチップとワイヤとの
間とで縦横に切断して成ることを特徴とする面実装型Ｌ
ＥＤ素子の製造方法、及び、上記の製造方法による面実
装型ＬＥＤ素子を提供することで課題を解決するもので
ある。According to the present invention, as a specific means for solving the above-mentioned conventional problems, a conductive plate and an insulating plate each having a predetermined thickness are alternately arranged in a plane direction. The block obtained by bonding to the surface is sliced so as to have an appropriate thickness in a direction orthogonal to the plane direction, and a conductive portion made of the conductive plate material and an insulating portion made of an insulating plate material are alternately in a parallel strip shape. A plurality of LED chips are mounted on the conductive portion of the element substrate base material at a predetermined pitch near one edge of the strip, and a plurality of LED chips are formed.
An ED chip and one edge of the conductive portion on which the LED chip is mounted and another edge of the conductive portion opposed to each other across the insulating portion are wired with a wire, and the LED chip and the wire are connected with a transparent resin. , And then cut vertically and horizontally between a predetermined pitch of each LED chip and between the LED chip and the wire of the conductive part.
An object of the present invention is to solve the problem by providing a method for manufacturing an ED element and a surface-mounted LED element according to the above-described manufacturing method.
【００１０】[0010]
【発明の実施の形態】つぎに、本発明に係る面実装型Ｌ
ＥＤ素子の製造方法を図に示す実施形態に基づいて詳細
に説明する。先ず、図１に示すものは素子基板母材１０
の形成方法であり、本発明では夫々が所定の板厚とされ
た、例えば銅などの導電性部材１１と、例えばガラスエ
ポキシなどの絶縁性部材１２とを面方向で交互に接合し
ブロック体１３（図２参照）を形成する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a surface mount type L according to the present invention will be described.
A method for manufacturing an ED element will be described in detail based on an embodiment shown in the drawings. First, the one shown in FIG.
According to the present invention, a conductive member 11 made of, for example, copper and an insulating member 12 made of, for example, glass epoxy, each having a predetermined thickness, are alternately joined in the plane direction to form a block body 13. (See FIG. 2).
【００１１】尚、このときに前記導電性部材１１は、後
に面実装型ＬＥＤ素子として形成された際に配線基板に
取付けるための端子部となるので溶融したハンダに対す
る親和性（濡れ性）に優れる部材であることが必要であ
る。また、前記導電性部材１１と絶縁性部材１２との接
合は接着材で行っても良く、或いは、熱圧着など他の方
法でも良い。At this time, since the conductive member 11 becomes a terminal portion to be attached to a wiring board when it is later formed as a surface mount type LED element, it has an excellent affinity (wetting property) to molten solder. It must be a member. Further, the bonding between the conductive member 11 and the insulating member 12 may be performed with an adhesive, or another method such as thermocompression bonding.
【００１２】続いて、図２に示すように、前記ブロック
体１３を上記導電性部材１１（絶縁性部材１２）の面と
直交する方向に適宜板厚と成るようにスライスを行え
ば、図３に示す導電部１０ａと絶縁部１０ｂとが交互に
平行の帯状として配置された形状の素子基板母材１０が
得られるものとなる。Subsequently, as shown in FIG. 2, the block 13 is sliced so as to have an appropriate thickness in a direction orthogonal to the surface of the conductive member 11 (insulating member 12). As a result, the element substrate base material 10 in which the conductive portions 10a and the insulating portions 10b are alternately arranged as parallel bands is obtained.
【００１３】尚、上記ブロック体１３を形成するに当て
っては、前記導電性部材１１の枚数を奇数とし、前記絶
縁性部材１２はその全てが導電性部材１１で挟まれるも
の、即ち、素子基板母材１０として形成されたときに、
両端が導電部１０ａで終るものとしておくことが、材料
の歩留りの面から好ましい。In forming the block 13, the number of the conductive members 11 is odd, and the insulating member 12 is entirely sandwiched between the conductive members 11, that is, an element. When formed as the substrate base material 10,
It is preferable that both ends end with the conductive portion 10a from the viewpoint of the yield of the material.
【００１４】図４は上記の説明のようにして得られた素
子基板母材１０を用いて面実装型ＬＥＤ素子１を形成す
るときの、最初の工程を示すものであり、前記導電部１
０ａの最も外側となる導電部１０ａ―には複数のＬＥ
Ｄチップ２が所定のピッチＰとしてマウントが行われ、
このＬＥＤチップ２と第二番目と成る導電部１０ａ―
との間でワイヤ３による配線が行われる。FIG. 4 shows an initial step of forming a surface-mount type LED element 1 using the element substrate base material 10 obtained as described above.
A plurality of LEs are provided on the outermost conductive portion 10a
D chip 2 is mounted at a predetermined pitch P,
The LED chip 2 and the second conductive portion 10a
And the wiring by the wire 3 is performed.
【００１５】このときに、前記ＬＥＤチップ２の導電部
１０ａ―へのマウントは、導電部１０ａ―とで挾む
第一番目の絶縁部１０ｂ―の側の縁部に寄せて行われ
るものとされ、導電部１０ａ―へのワイヤ３の接続も
前記絶縁部１０ｂ―の側の縁部に寄せて行われるもの
とされている。At this time, the mounting of the LED chip 2 on the conductive portion 10a- is performed by approaching the edge of the first insulating portion 10b- sandwiched by the conductive portion 10a-. The connection of the wire 3 to the conductive portion 10a- is also performed by approaching the edge on the insulating portion 10b- side.
【００１６】そして、前記導電部１０ａ―の第二番目
の絶縁部１０ｂ―側の縁部に寄せてはＬＥＤチップ２
の複数がマウントされ、このＬＥＤチップ２はワイヤ３
で第三番目の導電部１０ａ―とで上記と同様にして配
線が行われている。このときに、前記導電部１０ａ―
にマウントされるＬＥＤチップ２も導電部１０ａ―に
マウントされたＬＥＤチップ２と同一のピッチＰとさ
れ、直角の行列方向に整列するものとされている。The LED chip 2 is located near the edge of the conductive portion 10a- on the side of the second insulating portion 10b-.
Are mounted, and this LED chip 2 has a wire 3
The wiring is performed in the same manner as described above with the third conductive portion 10a-. At this time, the conductive portion 10a-
The LED chip 2 mounted on the LED chip 2 has the same pitch P as that of the LED chip 2 mounted on the conductive portion 10a, and is arranged in a right-angle matrix direction.
【００１７】以下同様にして、全ての導電部１０ａには
ＬＥＤチップ２のマウントが行われ、奇数番目の導電部
１０ａとこれに続く偶数番目の導電部１０ａとの間には
ワイヤ３による配線が行われるものとなる。ここで、例
えば第二番目の導電部１０ａ―のように、ＬＥＤチッ
プ２のマウントとワイヤ３による配線とが行われている
場合には、ＬＥＤチップ２とワイヤ３とには後にも説明
する切断シロ（切断代）として必要充分な間隔が設けら
れている。In the same manner, the LED chip 2 is mounted on all the conductive parts 10a, and a wire 3 is connected between the odd-numbered conductive part 10a and the even-numbered conductive part 10a that follows. Will be done. Here, when the mounting of the LED chip 2 and the wiring by the wire 3 are performed as in the second conductive portion 10a-, for example, the cutting of the LED chip 2 and the wire 3 described later is performed. A necessary and sufficient interval is provided as a shiro (cutting allowance).
【００１８】続いて、前記素子基板母材１０の、上記の
ようにマウントと配線とが行われた側の面は前記ＬＥＤ
チップ２とワイヤ３とを覆い、図５に示すように透明樹
脂によるモールド部４が形成される。その後に、前記素
子基板母材１０は前記モールド部４を含みホイルカッタ
ーなどで切断が行われる。Subsequently, the surface of the element substrate preform 10 on which the mounting and wiring are performed as described above is the LED.
A mold portion 4 made of a transparent resin is formed so as to cover the chip 2 and the wires 3 as shown in FIG. Thereafter, the element substrate preform 10 including the mold portion 4 is cut by a foil cutter or the like.
【００１９】前記した切断は、図６に示すように直角の
二方向となる切断線Ｄに対して行われ、一方向には前記
ＬＥＤチップ２間のピッチＰの中間で行われ、他の一方
向には前記ＬＥＤチップ２とワイヤ３との間隙で行わ
れ、これにより図７に示す面実装型ＬＥＤ素子１が得ら
れるものとなる。As shown in FIG. 6, the above-described cutting is performed on a cutting line D which is made in two directions perpendicular to each other. In one direction, the cutting is performed at the middle of the pitch P between the LED chips 2 and in the other direction. The direction is determined by the gap between the LED chip 2 and the wire 3, whereby the surface-mounted LED element 1 shown in FIG. 7 is obtained.
【００２０】従って、前記ピッチＰは完成時の面実装型
ＬＥＤ素子１の寸法に対し、前記ホイルカッターによる
切断シロだけ広く設定することが必要となる。同様に同
一の導電部１０ａ上にマウント及び配線が行われている
ＬＥＤチップ２とワイヤ３との間にも上記の切断シロが
必要となるものであり、逆に言えば前記導電部１０ａの
寸法、即ち、ブロック体１３を形成するときの導電性部
材１１の板厚はＬＥＤチップ２がマウントされ、ワイヤ
３の配線が行われた後に、尚且つ、切断シロを得るのに
充分な厚みが要求されるものとなる。Therefore, the pitch P needs to be set to be wider than the dimensions of the surface-mounted LED element 1 at the time of completion by the cutting margin by the wheel cutter. Similarly, the above-mentioned cutting white is also required between the LED chip 2 and the wire 3 mounted and wired on the same conductive part 10a, and conversely, the dimensions of the conductive part 10a That is, the plate thickness of the conductive member 11 when forming the block body 13 is required to be sufficiently thick after the LED chip 2 is mounted and the wire 3 is wired and a cutting white is obtained. Will be done.
【００２１】ここで、上記の製造方法により得られた面
実装型ＬＥＤ素子１の構成について説明を行うと、前記
素子基板母材１０は所定寸法に切断されて、一対の導電
部５ａ、５ｂと、前記導電部５ａ、５ｂに挟まれる絶縁
部５ｃとで構成される素子基板５を有するものとなり、
このときに、導電部５ａ、５ｂ、絶縁部５ｃは共に素子
基板５と同じ厚さを有するものとなっている。Here, the structure of the surface mount type LED element 1 obtained by the above-described manufacturing method will be described. The element substrate base material 10 is cut into a predetermined size, and a pair of conductive portions 5a, 5b is formed. And an element substrate 5 composed of an insulating portion 5c sandwiched between the conductive portions 5a and 5b.
At this time, the conductive portions 5a and 5b and the insulating portion 5c all have the same thickness as the element substrate 5.
【００２２】従って、前記導電部５ａにおいては上面が
ＬＥＤチップ２をマウントするための従来例で称するパ
ット部として機能し、底面及び絶縁部５ｃと接続してい
る以外の３面の側面の全てが従来例の端子部として機能
し、同様に導電部５ｂにおいては上面が従来例の配線部
として機能し、底面及び３面の側面が端子部として機能
するものとなる。Therefore, the upper surface of the conductive portion 5a functions as a pad portion, which is referred to in the conventional example for mounting the LED chip 2, and all of the three side surfaces other than the bottom surface and the insulating portion 5c are connected. The upper surface of the conductive portion 5b functions as a wiring portion of the conventional example, and the bottom surface and the three side surfaces function as terminal portions.
【００２３】次いで、上記の製造方法としたことによる
本発明の作用及び効果について説明を行えば、先ず、製
造工程中においては、導電部１０ａと絶縁部１０ｂとが
交互に平行の帯状として配置された素子基板母材１０と
したことで、従来は素子基板母材の上面と底面との電気
的な接続を行うために必要とされていたスロットの加
工、側面及びスロットの内面への無電解メッキなどの工
程が不要となり、生産工程の簡素化が可能となる。Next, the operation and effects of the present invention resulting from the above-described manufacturing method will be described. First, during the manufacturing process, the conductive portions 10a and the insulating portions 10b are alternately arranged as parallel strips. Of the element substrate preform 10, processing of slots conventionally required for electrical connection between the top and bottom surfaces of the element substrate preform, and electroless plating on side surfaces and inner surfaces of the slots. This eliminates the need for such a process, thereby simplifying the production process.
【００２４】また、上記の製造方法により形成される面
実装型ＬＥＤ素子１では、ＬＥＤチップ２は金属など熱
伝導性に優れる部材で上面から底面まで一体として形成
されている導電部５ａにマウントされているので、この
面実装型ＬＥＤ素子１を取付けた回路基板（図示せず）
など外部に対する放熱効率が向上する。Further, in the surface mount type LED element 1 formed by the above-described manufacturing method, the LED chip 2 is mounted on a conductive portion 5a integrally formed from the top surface to the bottom surface with a member having excellent thermal conductivity such as metal. Circuit board (not shown) to which the surface mount type LED element 1 is attached.
For example, the radiation efficiency to the outside is improved.
【００２５】よって、ＬＥＤチップ２の点灯による発熱
は効率良く回路基板など外部に放熱されるものとなり、
同じ上昇温度を許容する場合には流せる電流値が増える
ものとなるので、従来例のものと比較して連続定格電流
値の増加が可能となり、明るい面実装型ＬＥＤ素子１の
提供を可能とする。Therefore, heat generated by the lighting of the LED chip 2 is efficiently radiated to the outside such as a circuit board.
When the same temperature rise is allowed, the current value that can be passed increases, so that the continuous rated current value can be increased as compared with the conventional example, and the bright surface-mounted LED element 1 can be provided. .
【００２６】また、導電部５ａ、５ｂが金属部材などで
一体化されたことで、端子部としては底面と３面の側面
との都合４面が使用可能となり、回路基板に取り付ける
ときの面積が増加して取付強度が向上する。更には、従
来の素子基板は端子部の側面が無電解メッキで形成され
剥離などを生じ易いものであったのに対し、本発明では
導電部１０ａの一体化によりその発生を根絶し信頼性の
向上も可能とする。Also, since the conductive portions 5a and 5b are integrated with a metal member or the like, four terminals, that is, a bottom surface and three side surfaces, can be used as the terminal portions, and the area for mounting to the circuit board is reduced. This increases the mounting strength. Further, in the conventional element substrate, the side surface of the terminal portion is formed by electroless plating and is easily peeled off. In contrast, in the present invention, the generation is eradicated by the integration of the conductive portion 10a and the reliability is improved. Improvements are also possible.
【００２７】図８に示すものは本発明の別の実施形態で
あり、前の実施形態（図１参照）ではブロック体１３は
夫々が板状の導電性部材１１と絶縁性部材１２とを交互
に貼り合わせるものとしていたが、本発明はこれを限定
するものでなく、図示のように板状の導電性部材１１の
複数を容器中などで所定間隔で平行に保持しておき、例
えばエポキシ樹脂など液体状の接着材１４を導電性部材
１１間に注入し、硬化させてブロック体１３を形成して
も良いものである。FIG. 8 shows another embodiment of the present invention. In the previous embodiment (see FIG. 1), the block 13 alternates between a plate-shaped conductive member 11 and an insulating member 12 each. However, the present invention is not limited to this, and a plurality of plate-shaped conductive members 11 are held in parallel at predetermined intervals in a container or the like as shown in the figure, and for example, an epoxy resin Alternatively, the block 13 may be formed by injecting a liquid adhesive 14 between the conductive members 11 and curing the adhesive.
【００２８】[0028]
【発明の効果】以上に説明したように本発明により、夫
々が板状の導電性部材と絶縁性部材とを面方向で接合し
てブロック体とし、このブロック体を前記導電性部材と
絶縁性部材との面に直交する方向にスライスして素子基
板母材を形成し、該素子基板母材上にＬＥＤチップのマ
ウントとワイヤによる配線を行い、モールド部でＬＥＤ
チップとワイヤとを覆った後に所定位置で切断し形成す
る面実装型ＬＥＤ素子の製造方法としたことで、製造工
程においては素子基板母材へのスロット加工、側面及び
スロットの内面への無電解メッキなどの工程を不要と
し、工程の簡素化を可能として生産性を高め、面実装型
ＬＥＤ素子のコストダウンに極めて優れた効果を奏する
ものである。As described above, according to the present invention, a plate-shaped conductive member and an insulating member are joined in the plane direction to form a block, and this block is insulated from the conductive member. An element substrate base material is formed by slicing in a direction orthogonal to the surface of the member, and an LED chip is mounted and wired by wires on the element substrate base material.
The method of manufacturing a surface-mounted LED element, which cuts and forms at a predetermined position after covering the chip and the wire, enables slot processing on the element substrate base material and electroless processing on the side surface and the inner surface of the slot in the manufacturing process. This eliminates the need for steps such as plating, simplifies the steps, increases productivity, and achieves an extremely excellent effect in reducing the cost of surface-mounted LED elements.
【００２９】また、上記の製造方法として形成される面
実装型ＬＥＤ素子１は、ＬＥＤチップが金属など熱伝導
性に優れる部材で上面から底面まで一体として形成され
ている導電部にマウントされるものとなり、これにより
放熱効率が向上して、連続定格電流値の増加が可能とな
り、明るい面実装型ＬＥＤ素子として性能向上に優れた
効果を奏する。The surface mount type LED element 1 formed by the above-described manufacturing method is a member in which the LED chip is a member having excellent thermal conductivity such as metal and is mounted on a conductive portion integrally formed from the top surface to the bottom surface. As a result, the heat radiation efficiency is improved, the continuous rated current value can be increased, and an excellent effect of improving the performance as a bright surface-mounted LED element can be obtained.
【００３０】更に、導電部が一体化されたことで、端子
部としては底面と３面の側面との都合４面が使用可能と
し、回路基板に取り付けるときの面積が増加して取付強
度を向上させると共に、端子部に剥離などを生じないも
のとして面実装型ＬＥＤ素子の信頼性の向上にも優れた
効果を奏する。Further, by integrating the conductive portion, the terminal portion can be used on four sides, that is, the bottom surface and the three side surfaces, and the area for mounting on the circuit board is increased, so that the mounting strength is improved. At the same time, it is possible to prevent the terminal portion from being peeled off, so that the effect of improving the reliability of the surface mount type LED element can be obtained.
【図１】 本発明に係る面実装型ＬＥＤ素子の製造方法
の一実施形態における素子基板母材形成工程中の接合工
程を示す説明図である。FIG. 1 is an explanatory view showing a bonding step in an element substrate base material forming step in one embodiment of a method for manufacturing a surface-mounted LED element according to the present invention.
【図２】 同じく素子基板母材形成工程中のスライス工
程を示す説明図である。FIG. 2 is an explanatory view showing a slicing step in the same element substrate forming step.
【図３】 同じく素子基板母材の完成状態を示す斜視図
である。FIG. 3 is a perspective view showing a completed state of the element substrate base material.
【図４】 同じくＬＥＤチップのマウント工程を示す説
明図である。FIG. 4 is an explanatory view showing a mounting process of the LED chip.
【図５】 同じくモールド工程を示す説明図である。FIG. 5 is an explanatory view showing a molding step.
【図６】 同じく切断工程を示す説明図である。FIG. 6 is an explanatory view showing a cutting step in the same manner.
【図７】 本発明の製造方法により形成される面実装型
ＬＥＤ素子の例を一部を透視した状態で示す斜視図であ
る。FIG. 7 is a perspective view showing an example of a surface mount type LED element formed by the manufacturing method of the present invention in a partially transparent state.
【図８】 同じく本発明に係る面実装型ＬＥＤ素子の製
造方法の別の実施形態におけるブロック体の形成工程を
示す説明図である。FIG. 8 is an explanatory view showing a step of forming a block in another embodiment of the method for manufacturing a surface-mounted LED element according to the present invention.
【図９】 従来例の素子基板母材形成工程中のスロット
形成工程を示す断面図である。FIG. 9 is a cross-sectional view showing a slot forming step in a conventional element substrate base material forming step.
【図１０】 同じ従来例における無電解メッキによる導
電膜形成工程を示す断面図である。FIG. 10 is a sectional view showing a conductive film forming step by electroless plating in the same conventional example.
【図１１】 同じ従来例におけるエッチング工程を示す
説明図である。FIG. 11 is an explanatory view showing an etching step in the same conventional example.
【図１２】 同じ従来例におけるＬＥＤチップのマウン
ト工程を示す説明図である。FIG. 12 is an explanatory view showing a mounting process of an LED chip in the same conventional example.
【図１３】 同じ従来例におけるモールド工程を示す説
明図である。FIG. 13 is an explanatory diagram showing a molding step in the same conventional example.
【図１４】 同じ従来例における切断工程を示す説明図
である。FIG. 14 is an explanatory view showing a cutting step in the same conventional example.
【図１５】 従来例の面実装型ＬＥＤ素子の例を示す断
面図である。FIG. 15 is a cross-sectional view showing an example of a conventional surface mount type LED element.
１……面実装型ＬＥＤ素子 ２……ＬＥＤチップ ３……ワイヤ ４……モール部 ５……素子基板 ５ａ、５ｂ……導電部 ５ｃ……絶縁部 １０……素子基板母材 １０ａ……導電部 １０ｂ……絶縁部 １１……導電性部材 １２……絶縁性部材 １３……ブロック体 DESCRIPTION OF SYMBOLS 1 ... Surface mounting type LED element 2 ... LED chip 3 ... Wire 4 ... Mold part 5 ... Element board 5a, 5b ... Conductive part 5c ... Insulating part 10 ... Element board base material 10a ... Conductivity Part 10b Insulating part 11 Conductive member 12 Insulating member 13 Block body
Claims (2)
絶縁性板材とを面方向に交互に接合して得られたブロッ
ク体を前記面方向に直交する方向で適宜板厚と成るよう
にスライスして前記導電性板材による導電部と絶縁性板
材による絶縁部とが交互の平行の帯状となる素子基板母
材を形成し、この素子基板母材の前記導電部には帯状の
一方の縁寄りに所定ピッチとして複数のＬＥＤチップを
マウントすると共にこのＬＥＤチップと、当該ＬＥＤチ
ップがマウントされた導電部の一方の縁と絶縁部を挾ん
で対峙する導電部の他の一方の縁寄りとをワイヤで配線
し、前記ＬＥＤチップとワイヤとを透明樹脂で覆い、そ
の後に夫々のＬＥＤチップの所定ピッチ間と、導電部の
ＬＥＤチップとワイヤとの間とで縦横に切断して成るこ
とを特徴とする面実装型ＬＥＤ素子の製造方法。1. A block obtained by alternately joining a conductive plate material and an insulating plate material each having a predetermined thickness in a plane direction to have a suitable thickness in a direction orthogonal to the plane direction. In this manner, the conductive portion of the conductive plate material and the insulating portion of the insulating plate material are alternately formed into a parallel-shaped element substrate base material, and the conductive portion of the element substrate base material has one of a band shape. A plurality of LED chips are mounted at a predetermined pitch near the edge of the LED chip, and the LED chip and one other edge of the conductive portion opposed to one edge of the conductive portion on which the LED chip is mounted sandwiching the insulating portion. Are wired with a wire, the LED chip and the wire are covered with a transparent resin, and then cut vertically and horizontally between a predetermined pitch of each LED chip and between the LED chip and the wire of the conductive portion. Features characterized by Manufacturing method of mounted LED element.
部とが設けられ、対峙する二辺の側面及びその近傍の底
面には夫々に端子部が設けられ、前記端子部の一方がマ
ウント部に、他の一方がパット部に接続され、前記マウ
ント部にはＬＥＤチップがマウントされ、前記ＬＥＤチ
ップと前記パット部とがワイヤで配線されて成る面実装
型ＬＥＤ素子において、前記素子基板は、夫々が所定の
板厚とされた導電性板材と絶縁性板材とを面方向に交互
に接合して得られたブロック体を前記面方向と直交する
方向に適宜板厚となるようにスライスして前記導電性板
材による導電部と絶縁性板材による絶縁部とが交互の帯
状となる素子基板母材からなり、該素子基板の厚さを有
する導電性部材により形成された導電部の一対で同じ厚
さを有する絶縁性部材で形成された絶縁部を挟持して接
合して形成され、一方の導電部の上面がマウント部とさ
れ、他の一方の導電部の上面がパット部とされ、夫々の
導電部の底面と前記絶縁部と接合された側面を除く３面
の側面とが端子部とされていることを特徴とする面実装
型ＬＥＤ素子。2. A mounting portion and a pad portion are provided on an upper surface of the element substrate, and terminal portions are provided on two opposing side surfaces and a bottom surface in the vicinity thereof, and one of the terminal portions is mounted on the mounting portion. The other one is connected to a pad portion, an LED chip is mounted on the mount portion, and the LED chip and the pad portion are wired by wires. A block obtained by alternately joining a conductive plate material and an insulating plate material each having a predetermined plate thickness in a plane direction is sliced so as to have an appropriate thickness in a direction orthogonal to the plane direction. The conductive portion made of the conductive plate material and the insulating portion made of the insulating plate material are made of an element substrate base material having an alternate band shape, and a pair of conductive portions formed of a conductive member having a thickness of the element substrate have the same thickness. Insulating part The upper surface of one conductive portion is a mount portion, the upper surface of the other conductive portion is a pad portion, and the bottom surface of each conductive portion is formed by sandwiching and joining an insulating portion formed of a material. A surface-mounted LED device, wherein three side surfaces other than the side surface joined with the insulating portion are terminal portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22611395A JP3146452B2 (en) | 1995-08-11 | 1995-08-11 | Surface mount type LED element and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22611395A JP3146452B2 (en) | 1995-08-11 | 1995-08-11 | Surface mount type LED element and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0955535A JPH0955535A (en) | 1997-02-25 |
| JP3146452B2 true JP3146452B2 (en) | 2001-03-19 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22611395A Expired - Fee Related JP3146452B2 (en) | 1995-08-11 | 1995-08-11 | Surface mount type LED element and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3146452B2 (en) |
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