JP3144898B2 - High efficiency coding / decoding system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency encoding / decoding system suitable for recording and reproduction on a television broadcast and a recording medium.

[0002]

2. Description of the Related Art In recent years, various standardization proposals have been proposed for high-efficiency coding for compressing image data.
The high-efficiency encoding technique encodes image data at a smaller bit rate in order to improve the efficiency of digital transmission and recording. For example, CCITT (In
ternational Telegraph and Telephone Consultative C
ommittee) proposes a standardization recommendation H.264 for videoconferencing / videophone. 261 is proposed. In this recommendation, encoding is performed using a frame I that has been subjected to intra-frame compression (Intra-frame) and a frame P that has been subjected to inter-frame compression (Inter-frame or Predictive frame).

FIG. 16 is an explanatory diagram for explaining the compression method of this recommendation proposal.

[0004] Frame I is DCT (discrete cosine transform)
One frame of image data is encoded by processing. The frame P is obtained by encoding image data by predictive encoding using the frame I or another frame P. Furthermore, the bit rate is further reduced by performing variable length coding on these coded data. Since the frame I is encoded only by the information in the frame, it can be decoded only by the single encoded data. On the other hand, the frame P is encoded by utilizing the correlation with other image data, and cannot be decoded only by single encoded data.

FIG. 17 is a block diagram showing a recording side of a recording / reproducing apparatus employing such a predictive coding.

The luminance signal Y and the color difference signals Cr and Cb are supplied to a multiplexing circuit 11 and multiplexed in units of blocks of 8 pixels × 8 horizontal scanning lines. For the color difference signals Cr and Cb, the sampling rate in the horizontal direction is の of the luminance signal Y.
Therefore, during the period in which two 8 × 8 luminance blocks are sampled, one 8 × 8 block is sampled for the color difference signals Cr and Cb. As shown in FIG. 18, the multiplex processing circuit 11 forms a macro block (MB) by four blocks of two luminance blocks Y and one chrominance block Cr and Cb. Note that two luminance blocks Y
And each one of the color difference blocks Cr and Cb represent the same position on the screen. Also, a GOB (group of block) is configured by a plurality of macroblocks, and one frame is configured by the plurality of GOBs. The output of the multiplex processing circuit 11 is supplied to a DCT circuit 13 via a subtractor 12.

When performing intra-frame compression, as described later, the switch 14 is off, and the output of the multiplex processing circuit 11 is directly input to the DCT circuit 13. DCT circuit 13
The DCT circuit 13 converts an input signal into a frequency component by an 8 × 8 two-dimensional DCT (discrete cosine transform) process. This makes it possible to reduce spatial correlation components.
That is, the output of the DCT circuit 13 is given to the quantization circuit 15,
The quantization circuit 15 reduces the redundancy of the signal of one block by requantizing the DCT output with a predetermined quantization coefficient. Note that the multiplex processing circuit 1 operates in block units.
1. Block pulses are supplied to the DCT circuit 13, the quantization circuit 15, and the like.

The quantized data from the quantizing circuit 15 is supplied to a variable length coding circuit 16 and, for example, Huffman coding is performed based on the result calculated from the statistical code amount of the quantized output. Thereby, short bits are assigned to data with a high appearance probability, and long bits are assigned to data with a low appearance probability.
The amount of transmission is further reduced. The output of the variable length coding circuit 16 is given to an error correction encoder 17 and
Add the parity for error correction and output to the multiplexing circuit 19.

The output of the variable length coding circuit 16 is also supplied to a coding control circuit 18. The data amount of the output data greatly changes depending on the input image. Therefore, the coding control circuit
Reference numeral 18 monitors the amount of output data from the variable length encoding circuit 16 and controls the quantization coefficient of the quantization circuit 15 to adjust the amount of output data. Also, the encoding control circuit 18 may control the variable length encoding circuit 16 to limit the amount of output data.

On the other hand, the synchronization / ID generation circuit 20 generates a frame synchronization (sync) signal, data contents and additional information indicating additional information.
A D signal is generated and output to the multiplexing circuit 19. The multiplexing circuit 19 forms data of one sync block by using the sync signal, the ID signal, the compressed signal data, and the parity, and outputs the data to a recording encoding circuit (not shown). The recording encoding circuit records and encodes the output of the multiplexing circuit 19 according to the characteristics of the recording medium, and then records the output on a recording medium (not shown) via a recording amplifier (not shown).

On the other hand, when the switch 14 is on,
The signal of the current frame from the multiplex processing circuit 11 is subtracted from the data of the previous frame, which has been motion-compensated, which will be described later, in the subtractor 12, and is supplied to the DCT circuit 13. That is, in this case, inter-frame encoding for encoding the difference data using the redundancy of the image between the frames is performed. In the inter-frame coding, if the difference between the previous frame and the current frame is simply obtained, the difference becomes large when the image has motion. Therefore, the motion vector is detected by calculating the position of the previous frame corresponding to the predetermined position of the current frame, and the difference is reduced at the pixel position corresponding to the motion vector to reduce the difference value by performing motion compensation. I have.

That is, the output of the quantization circuit 15 is also supplied to the inverse quantization circuit 21. The quantized output is inversely quantized by an inverse quantization circuit 15 and further inversely DCT-generated by an inverse DCT circuit
T processing to return to the original video signal. In the DCT processing, requantization, inverse quantization, and inverse DCT processing, the original information cannot be completely reproduced, and some information is lost. In this case, since the output of the subtractor 12 is the difference information, the output of the inverse DCT circuit 22 is also the difference information. Inverse DCT
The output of the circuit 22 is provided to an adder 23. The output of the adder 23 is fed back via a variable delay circuit 24 and a motion compensation circuit 25 for delaying the signal for about one frame period, and the adder 23 adds the difference data to the data of the previous frame to obtain the data of the current frame. Is reproduced and output to the variable delay circuit 24.

The data of the previous frame from the variable delay circuit 24 and the data of the current frame from the multiplex processing circuit 11 are applied to a motion detection circuit 26 to detect a motion vector. The motion detection circuit 26 obtains a motion vector by, for example, full search motion detection by matching calculation. In the full search motion detection, the current frame is divided into predetermined blocks, and a search range of, for example, 15 pixels horizontally × 8 pixels vertically is set in each block. For each block, a matching calculation is performed in the corresponding search range of the previous frame to calculate an approximation between patterns. Then, a block of the previous frame which gives the minimum distortion in the search range is calculated, and a vector obtained by the block of the current frame is detected as a motion vector. The motion detection circuit 26 outputs the obtained motion vector to the motion correction circuit 25.

The motion correction circuit 25 extracts the data of the corresponding block from the variable delay circuit 24, corrects the data according to the motion vector, outputs the data to the subtractor 12 via the switch 14, and after the time adjustment. Output to the adder 23. Thus,
The motion-compensated data of the previous frame is supplied from the motion compensation circuit 25 to the subtractor 12 via the switch 14.When the switch 14 is on, the inter-frame compression mode is set. The compression mode is set.

The turning on and off of the switch 14 is performed based on a motion judgment signal. That is, the motion detection circuit 26 creates a motion determination signal based on whether or not the magnitude of the motion vector exceeds a predetermined threshold and outputs the motion determination signal to the logic circuit 27. The logic circuit 27 controls the ON / OFF of the switch 14 based on a logical determination using the motion determination signal and the refresh cycle signal. The refresh cycle signal is a signal indicating the intra-frame compressed frame I in FIG. When the refresh cycle signal indicates that the frame I has been input, the logic circuit 27 turns off the switch 14 regardless of the motion determination signal. Also, when the motion determination signal indicates that the motion is relatively fast and the minimum distortion due to the matching calculation has exceeded the threshold, the logic circuit 27 turns off the switch 14 even when the frame P is input, and turns off the switch 14. To perform intra-frame compression encoding. Table 2 below shows ON / OFF control of the switch 14 by the logic circuit 27.

[0016]

[Table 1] FIG. 19 is an explanatory diagram showing a data stream of a recording signal output from the multiplexing circuit 19.

As shown in FIG. 19, the first of the input image signals
And the sixth frame are the intra-frame compressed frames I1,
I6, and the second through fifth frames are converted into inter-frame compressed frames P1 through P5. The ratio of the data amount of frame I to frame P is (3 to 10): 1. Although the data amount of the frame I is relatively large, the data amount of the frame P is extremely reduced. Note that the data subjected to the inter-frame compression processing cannot be decoded unless other frame data is decoded.

FIG. 20 shows a decoding side (reproducing side) of the recording / reproducing apparatus.
FIG.

The compressed code data recorded on the recording medium is reproduced by a reproducing head (not shown) and supplied to an error correction decoder 31. The error correction decoder 31 corrects an error generated during transmission and recording. The reproduction data from the error correction decoder 31 is supplied to a variable length data decoding circuit 33 via a code buffer memory circuit 32, and is decoded into fixed length data. Note that the code buffer memory circuit 32 may be omitted.

The output of the variable length decoding circuit 33 is an inverse quantization circuit.
Inverse quantization is performed in 34 and inverse DCT circuit 35 performs inverse DCT.
T processing, decoding to the original video signal, and terminal a of switch 36
Give to. On the other hand, the output of the variable length decoding circuit 33 is also supplied to a header signal extraction circuit 37. The header signal extraction circuit 37 searches for a header indicating whether the input data is compressed data within a frame or compressed data between frames, and outputs the header to the switch 36. When a header indicating the compressed data in the frame is given, the switch 36 selects the terminal a and outputs the decoded data from the inverse DCT circuit 35.

The inter-frame compressed data is obtained by adding the output of the inverse DCT circuit 35 and the output of the previous frame from the predictive decoding circuit 39 by the adder 38. That is, the output of the variable length decoding circuit 33 is
To obtain a motion vector. This motion vector is provided to the prediction decoding circuit 39. On the other hand, the decoded output from the switch 36 is delayed by one frame period by the frame memory 41. The predictive decoding circuit 39 performs motion compensation on the decoded data of the previous frame from the frame memory 41 using a motion vector and outputs the result to the adder 38. The adder 38 decodes the inter-frame compressed data by adding the output of the predictive decoding circuit 39 and the output of the inverse DCT circuit 35, and outputs the decoded data to the terminal b of the switch 36. When the inter-frame compressed data is input, the switch 36 selects the terminal b according to the header, and outputs the decoded data from the adder 38. Thus, the compression and decompression operations are performed without delay in both the intra-frame compression and the inter-frame compression.

Various methods are being studied for recording such highly efficient encoded digital image data on a magnetic recording / reproducing apparatus (VCR). FIG. 21 is an explanatory diagram for explaining a recording track created on a recording medium by the VCR.

In FIG. 21, A1, A2,... Indicate recording tracks by a plus azimuth head, and B1, B2
,... Indicate recording tracks by a minus azimuth head. In this case, no particular problem occurs during normal reproduction. However, for example, when triple-speed reproduction is performed, the trace by each head is as shown by the arrow in the figure, and only the hatched portion in the figure where the azimuths of the head and the recording track match are reproduced. Even in this case, one screen can be reproduced by analog recording in which the position on the screen corresponds to the recording position on the recording medium. However, the code amount of the intra-frame compressed frame I is different from that of the inter-frame compressed frame P, and when the data stream shown in FIG. 19 is recorded on the recording medium, one frame is reproduced by the reproduction data at the triple speed reproduction. It is not always possible. Furthermore, since the inter-frame compressed frame P cannot be decoded by a single frame, it cannot be reproduced when a frame that cannot be decoded occurs, as in triple-speed reproduction. Moreover, in this case, the data is reproduced discontinuously, so that a system that decodes the input data sequence continuously, such as a videophone, cannot utilize the data after the interruption.

In order to make each data correspond to a position on the screen, it is conceivable to add block address information. However, unnecessary data other than the image data is added, and the data use efficiency is reduced. It is also conceivable that the receiving side adds address information corresponding to the position of the screen and records it on the recording medium, or performs format conversion suitable for storage and rearranges, for example, intra-frame data. However, data necessary for performing these format conversions has not been transmitted. Further, effective decoding using discontinuous reproduction data is not performed.

[0025]

As described above, in the above-mentioned conventional high-efficiency coding / decoding system, there is a problem that if address information is added on the transmission side, the data use efficiency is reduced. In addition, there is a problem that data necessary for format conversion is not transmitted on the receiving side.Furthermore, when data is transmitted discontinuously, decoding using the transmitted data effectively is performed. There was no problem.

The present invention facilitates format conversion on the receiving side, enables decoding using discontinuous data effectively, and suppresses error propagation without lowering data use efficiency. It is an object of the present invention to provide a high-efficiency encoding / decoding system capable of performing the above.

[0027]

According to the present invention, there is provided a high-efficiency encoding / decoding system comprising: a small block constituted by at least one group of blocks which are encoding units of input data; A macro block having a macro block data length arranged at the beginning of the small block, the input data being a variable length for each block which is a coding unit as a first system. Variable length data constituted by at least one group of data obtained by encoding, header information of the variable length data,
And a small block data length indicating the data length.
Having adjustment bit data and its data length as a system of
Having a modification instruction signal as a third system, and transmitting a coefficient based on a coding characteristic of the variable length data including data for selecting at least one of the first to third systems; Encoding means for performing variable length encoding of input data for each block as an encoding unit and outputting the data; and measuring and outputting the data length from the output of the variable length encoding means. A data length measuring unit, a header information creating unit that creates and outputs header information for the output of the encoding unit, and forms a small block by at least one or more of the blocks, and outputs the encoding unit; The output of the data length measuring means and the output of the header information creating means are packetized as a first system, and the predetermined adjustment bit data and information of the data length are packetized as a second system, A first packet unit for packetizing a modification instruction signal as at least one of the first to third systems; and a macro unit comprising at least one of the small blocks. A second packet unit for forming a block and packetizing the output of the data length measuring unit and the output of the header information creating unit at the output of the first packet unit and outputting the packetized data; Things.

[0028]

In the present invention, when the first system of the small blocks is selected, the size of the data block which can be decoded independently can be indicated by the small block data length for the intra-frame compressed data. Format conversion is easy when recording to a computer. When the second system is selected, an adjustment bit is transmitted instead of the variable-length data, and time adjustment is performed. When the third system is selected, a modification instruction signal is transmitted, and the data can be modified even when the data is reproduced discontinuously.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing one embodiment of a high-efficiency encoding / decoding system according to the present invention. FIG. 1 shows the configuration of the encoded data. FIGS. 2 and 3 are explanatory diagrams for explaining a method of configuring the encoded data in FIG.

First, the configuration of the data format employed in the present embodiment will be described with reference to FIGS.

As shown in FIG. 2A, one frame screen has 768 horizontal pixels × 4 vertical pixels based on the luminance signal Y.
It is assumed that it is composed of 80 pixels. This luminance signal Y
When one block is composed of 8 × 8 pixels, the number of luminance blocks in one frame screen is 96, as shown in FIG.
× 60. Assuming that the luminance signal Y and the color difference signals Cr and Cb are sampled at a sampling frequency of 4: 1: 1, the color difference signals Cr and Cb are
As shown in (c) and (d), one frame screen is 24 ×
There are 60 color difference blocks. In other words, the four luminance blocks Y and the one color difference block Cr and Cb each have the same size on the screen, and these four luminance blocks Y
And a single color difference block Cr, Cb to form a small block (FIG. 3A). Note that the transform coding unit is 1
It is a block.

Further, in this embodiment, as shown in FIG. 3B, one macroblock is constituted by a set of four small blocks (the definition of the macroblock is different from the conventional example). Therefore, as shown in FIG. 3C, one frame screen is composed of 16 small blocks in the horizontal direction × 60 blocks in the vertical direction.
It is composed of small blocks, and when represented by the number of macroblocks, it is composed of 4 macroblocks in the horizontal direction × 60 macroblocks in the vertical direction.

FIG. 4 is an explanatory diagram for explaining the data arrangement of block data.

As described above, the small block is composed of four luminance blocks Y and one chrominance block Cr, Cb. As shown in FIG. 4A, the luminance blocks Y1, Y2, The data are arranged and transmitted in the order of Y3, Y4, and the color difference blocks Cr, Cb. FIG. 4B shows a configuration of each of the luminance block Y and the color difference blocks Cr and Cb in the small block. Each of the blocks Y, Cr and Cb is sequentially described by the variable length data shown in FIG. . An EOB (end of block) signal is added to the end of the variable length data. That is, one small block is constituted by six consecutive data of FIG. 4B. FIG. 4B shows an example in which all pieces of compression-encoded data are sequentially described as variable-length data. However, as shown in FIG. In some cases, the data is transmitted separately from variable-length data.

Each macro block (macro B) composed of four small blocks is transmitted in numerical order of FIG. That is, as shown in FIG. 4D, the data of one frame is arranged with data indicating the beginning of the frame at the beginning,
Next, the data of the first, second,..., N-th macro blocks (n = 240 in FIG. 3) are sequentially arranged. Next, the data at the head of the next frame is arranged.

The configuration of each macro block and each small block will be described with reference to FIG. In FIG. 1, small blocks are shown by dashed lines.

A macro block data length 51 is arranged at the head of the macro block. The macroblock data length 51 indicates the data length of each macroblock. When an error or the like occurs in a macro block, the head position of the next macro block is known using the information of the data length 51. This prevents an error occurring in a macroblock from spreading to other macroblocks.

Next, the macro block header 52 is arranged. The macroblock header 52 indicates the information of the entire macroblock in a unified manner, such as information on the comparison with the screen position and information on whether the entire macroblock is intra-frame or inter-frame compressed data. Is shown. Following the macro block header 52, four small blocks 50 are arranged.

In the small block 50, first, the quantization coefficient 53
Are arranged. In high efficiency coding, data is quantized after DCT transform. The quantization coefficient 53 is a coefficient for creating a quantization table used for this quantization processing.
For example, the quantization table is obtained by multiplying each data quantization coefficient of the basic quantization table. In the present embodiment, the quantization coefficient 53 has a meaning as an original quantization coefficient and also functions as a control signal for branching into three systems described later. For example, using 5-bit information (0 to 31) as the value A of the quantization coefficient 53,
The original quantization coefficient is represented by 0 to 29 (= A1). If the value A of the quantization coefficient 53 is A1, the process branches to the next small block header 54, and the value A becomes 30.
When (= A2), the process branches to the data adjustment bit length 58, and when the value A is 31 (= A3), the process branches to a modification instruction.

It should be noted that almost no branching by A = A2, A3 is performed during transmission from a normal broadcasting station. A = A2, A3
Is mainly performed in a recording medium such as a VCR.

In the branch at A = A1, small block headers 54 are arranged first. Small block header
54 describes the header of the small block 50. The small block header 54 makes it possible to determine whether the compression is intra-frame compression or inter-frame compression, and whether the compression is a field or a frame. Further, other necessary information regarding the small block 50 is included. Subsequent to the small block header 54, the process branches to either the motion vector 55 or the intra data length 56. The intra data length 56 indicates the data length of the small block 50 when the small block 50 is compressed data in a frame. As mentioned above,
Intra-frame data can be decoded independently, and VC
In R and the like, the reproduction efficiency at the time of special reproduction is improved by rearranging the intra-frame data. That is, such a change in the data format for the recording medium can be performed relatively easily with the information having the intra data length 56. On the other hand, if the small block 50 is inter-frame compressed data, the process branches from the small block header 54 to the motion vector 55. The motion vector 55 gives a vector (motion vector) indicating the pixel position of the previous frame as a reference for the inter-frame compressed frame.

Following the intra data length 56 or the motion vector 55, variable length data 57 is arranged. The variable length data 57 is obtained by, for example, quantizing the DCT transform coefficient, and performing Huffman coding (variable length coding) on the quantized output read out by zigzag scanning according to the generation probability.

On the other hand, in the branch at A = A 2, the data adjustment bit length 58 is arranged following the quantization coefficient 53. The data adjustment bit length 58 indicates the bit length of the adjustment bit for adjusting the time difference caused by the difference in the code amount. For example, it is assumed that the data amount of a two-hour program with a signal rate of 200 Mbps is highly efficient coded to compress the information amount and transmitted at 10 Mbps. Even in this case, the compressed data of the two-hour program is basically transmitted over two hours. However, since variable-length coding is performed, a scene where the amount of information to be transmitted is large and a scene where the amount of information to be transmitted is small occur depending on a difference in compression ratio for each scene. Therefore, the encoding / decoding device has a buffer. Since the time is adjusted by this buffer, almost no adjustment bits are needed. However, during special reproduction of a VCR, reproduced data may be discontinuous, or only valid data may be reproduced. The time corresponding to the discontinuous portion cannot be absorbed by the buffer. For this reason, a bit tone adjustment path is provided. In this case, the adjustment bit length 58 indicates the bit length of the discontinuous portion of the reproduction data. Adjustment bit length
With 58, the start position of the next reproduction data can be known.

Next, the adjustment bit data 59 is arranged. The adjustment bit data 59 is adjustment bit data to be inserted into a discontinuous portion of the data by the bit length specified by the data adjustment bit length 58. The transmission rate is made constant by the adjustment bit data 59. Since it is clear that the transmission data is an adjustment bit by branching at A = A2, any data may be used as the adjustment bit data 59. But variable length data
If the adjustment bit data is arranged immediately after the variable length data 57 without adding the additional data to the variable length data 57, a bit string that does not exist in the variable length data 57 (Huffman code) as the adjustment bit data 59 (for example, all “1”) Must be employed.

In the branch at A = A3, only the control signal indicating the retouching operation is transmitted. The decoding circuit is controlled by the control signal, and the discontinuous portion of the data is corrected by, for example, the data of the previous frame.

Since the transmission data thus configured has a macroblock data length 51, the head of the next macroblock can be known without decoding the variable length data 57. Further, even if an error occurs in a predetermined macroblock, the error is completed within that macroblock, and the error does not propagate to other macroblocks. The macroblock header 52 is transmitted after the macroblock data length 51. The macro block header 52 compares the screen position with the screen position, thereby enabling the screen to be reproduced from the decoded data even during the special reproduction of the VCR. Note that address information is not transmitted in units of macroblocks, and the data use efficiency is improved as compared with the related art.

Next, four small blocks 50 are transmitted. Each small block 50 has a quantization coefficient 53 arranged at the top, and then A
In the branch according to = A1, small block headers 54 are arranged. Most of the transmission data from the broadcasting station is branched by A = A1. When the small block 50 is intra-frame data, an intra data length 56 is transmitted, and when the small block 50 is inter-frame data, a motion vector 55 is transmitted. Next, the variable length data 57 is transmitted. As described above, each small block 50 has the small block header 54 in addition to the variable-length data 57, so that error propagation is suppressed.
At the time of VCR special reproduction, reproduction data is discontinuous in a relatively short data unit. However, a small block header 54 is provided for each small block 50 to reduce the decoding unit.
The reproduction efficiency (decoding efficiency) is improved.

Incidentally, the intra-frame data can be decoded independently. For this reason, in a VCR or the like, the format of the transmitted data may be converted and the intra-frame data may be rearranged. In this embodiment, the data length of the intra frame data is transmitted by the intra data length 56. Thereby, V
Format conversion becomes easy in CR and the like. Also,
Due to the intra data length 56, during VCR special playback,
Without having to decode the data, you can know that the intra-frame part was played normally without errors,
Further, it is possible to know the end point of the data.

Here, it is assumed that data formed by branching according to A = A1 is transmitted from a broadcasting station to a VCR, converted into a recording format for special reproduction in the VCR, and recorded on a recording medium. In this case, the branching is controlled by changing the value A of the quantization coefficient 53 in the VCR. 5 and 6 are explanatory diagrams for explaining this operation.

Now, as shown in FIG. 21, it is assumed that only the data recorded in the hatched portion is reproduced by the special reproduction of the VCR. Further, when the reproduced signal in the hatched portion is decoded into a variable-length code, the only data that can be restored to the original image signal using the single data is the in-frame compressed data. On the other hand, in the inter-frame compressed data, only the difference (prediction) signal is decoded.
In order to obtain an original image signal, data of a previous frame is required. Therefore, only the in-frame compressed data of the reproduced signal is restored to the image, and the other data is unnecessary.

Now, it is assumed that the image in the shaded area in FIG. 5 is restored by the compressed data in the frame reproduced at the time of the special reproduction, and the shaded area corresponds to the small block. That is, the first, seventh, fourteenth, twenty-first,
... Reproduction data of each one small block of the macro block can be decoded. Therefore, in this case, at the time of recording, the VCR records data only for each one of the first, seventh, fourteenth,... Macroblocks.
That is, in a predetermined frame, the data of the first small block of the first macroblock is stored following the frame head data (FIG. 4D). That is, the value A of the quantization coefficient 53 of the first small block is A1, and data based on the branch at A = A1 is recorded. Next, the value A of the quantization coefficient 53 is set to A3 from the second small block to the fourth small block of the first macroblock. Similarly, the branch according to A = A3 is selected in all the small blocks of the second to sixteenth macroblocks. That is, in this case, only the control signal of the modification instruction is stored. Next, the first small block of the seventeenth macroblock selects a branch based on A = A3, and the second small block selects a branch based on A = A1. Thereafter, in the same manner,
Variable length data is recorded only in the portion corresponding to the hatched portion in FIG. 5, and the control signal of the modification instruction is recorded in the other portions.

By the way, by selecting the branch at A = A3, the amount of transmission data is reduced. Therefore, there is a margin in time after transmitting the data of the 240th macroblock. Therefore, in order to adjust the time, the branch of A = A2 is selected by changing the quantization coefficient 53. FIGS. 7 to 9 are explanatory diagrams for explaining this branch of A = A2.

FIG. 7 corresponds to the data of one frame, and the hatched portions indicate the adjustment bits by the branch of A = A2. In FIG. 7, the quantization coefficient 53 is set to A = A2 after the data transmission of the 240th macroblock. The data adjustment bit length 58 is transmitted following the quantization coefficient 53, and then the adjustment bit data 59 is transmitted. With the data adjustment bit length 58, the adjustment bit data 59 is inserted for each constituent unit of the data packet, and the head of the next frame is also clarified. FIG. 8 shows a format of data recorded on a recording medium. In FIGS. 7 and 8, the adjustment bits are transmitted at the end of the frame. However, as shown in FIG. 9, the adjustment bits may be inserted between macroblocks and transmitted.

On the other hand, at the time of reproduction, the intra-frame data indicated by the hatched portion in FIG. 6 is decoded, and is made to correspond to the position on the screen by the macroblock header 52. Further, for the other parts, the control signal of the modification instruction is reproduced, and thereby, the image is reproduced by, for example, the data of the previous frame.

As described above, according to the data configuration of the present embodiment, only the head data of the frame is transmitted as the address information, and the data use efficiency is improved. Further, the position on the screen is compared with the position on the screen by the macro block header 52, so that the data use efficiency can be improved as compared with the related art. Further, since the small block which is the decoding unit is a combination of the header and the variable length code, the reproduction efficiency when the reproduction data is discontinuous can be improved. Further, since the data length of the intra-frame data is transmitted, format conversion in a VCR or the like becomes easy. In addition to the system for normal data transmission, a system for inserting an adjustment bit for time adjustment and a system for giving a modification instruction are selected according to the recording state. Even in the case of continuous data, it is possible to restore an image from reproduced discontinuous data. In this way, an extremely effective data format can be obtained in a medium such as a television broadcast where the conditions of compression efficiency are severe and a data error and discontinuous reproduction occur such as a VCR.

Although the present embodiment has been described in units of small blocks, it may be configured in units of blocks, or the configuration of FIG. 1 may be made independent in units of small blocks. In this case, the macroblock data length 51 in FIG.
The macro block header 52 and the small block 50 are a transmission unit. In this case, the intra-frame data length 56 is unnecessary.

FIG. 10 is a block diagram showing an encoding circuit for realizing the data configuration of FIG.

The preprocessing circuit 61 samples the input signal and outputs it to the subtractor 12 and the switch 62 in small block units shown in FIGS. The output of the subtractor 12 is also given to the switch 62, and the switch 62 is controlled by the intra-frame / inter-frame identification circuit 63 and outputs one of two inputs to the DCT circuit 13. The intra-frame / inter-frame discrimination circuit 63 receives an external control signal and a motion determination signal from the motion detection circuit 26 described later, and controls the switch. That is, the intra-frame / inter-frame discrimination circuit 63 causes the switch 62 to select the output of the pre-processing circuit 61 when the intra-frame compression is instructed by an external control signal or when the motion is larger than a predetermined value. Force compression.

The DCT circuit 13 receives a signal in block units, and converts the input signal into a frequency component by an 8 × 8 two-dimensional DCT (discrete cosine transform) process. DCT circuit
The output of 13 is supplied to the quantization circuit 15, which receives the quantization coefficient from the rate control circuit 64 and requantizes the DCT output to reduce the redundancy of the signal of one block. The rate control circuit 64 generates a quantization coefficient based on the transform coefficient from the DCT circuit 13 and the data from the rate control circuit 67. The quantized data from the quantization circuit 15 is provided to the variable length coding circuit 16 and the inverse quantization circuit 21.

When performing inter-frame compression, it is necessary to compensate for motion in an image. The quantized output is supplied to an inverse quantization circuit 21. The inverse quantization circuit 21 is a rate control circuit.
The quantization coefficient is given from 64, and the quantization output is inversely quantized and supplied to the inverse DCT circuit 22. The inverse DCT circuit 22 performs an inverse DCT process on the output of the inverse quantum circuit 21 to return to the original video signal and provides the video signal to the adder 23. In this case, since the output of the subtractor 12 is the difference information, the output of the inverse DCT circuit 22 is also the difference information. The output of the adder 23 is fed back via the inter-frame prediction circuit 68 and the switch 69, and the adder 23 reproduces and outputs the data of the current frame by adding the difference data to the data of the previous frame.

The inter-frame prediction circuit 68 includes the motion detection circuit 26
Also gives a motion vector. For the motion vector 26, an input signal is given from the preprocessing circuit 61 to obtain a motion vector. The inter-frame prediction circuit 68 corrects the output of the adder 23 using the motion vector and outputs the corrected output to the subtractor 12 and also outputs the same to the adder 23 via the switch 69. The switch 69 is controlled by an intra-frame / inter-frame identification circuit 63.
In this way, the data of the motion-compensated previous frame is subtracted.
Supply to 12.

On the other hand, the variable length encoding circuit 16 subjects the quantized output to, for example, Huffman encoding and outputs the result to the buffer 65 and the data length measuring circuit 66. The buffer 65 accumulates the variable length code and outputs it to a multiplexer (hereinafter, referred to as MPX) 70.
Depending on the accumulation state of the buffer 65, the rate control circuit 67
The output data amount from the variable length coding circuit 16 is monitored, and based on the monitoring result, the variable length coding circuit 16 is controlled to limit the output data amount, and the rate control circuit 64 is controlled to control the quantization circuit. The output data amount is adjusted by changing the 15 quantization coefficients. The data length adjustment circuit 74 is controlled by the rate control circuit 67 to create adjustment bit data and output it to the buffer 65.

On the other hand, the data length measuring circuit 66 measures the data length of each block from the output of the variable length coding circuit 16 and further accumulates the block data length to obtain the data length of the small block. Output to the length measurement circuit 71. The data length measurement circuit 71 accumulates the data lengths of the four small blocks from the output of the data length measurement circuit 66, adds the data length of the header, obtains the macroblock data length, and outputs it to the MPX 70. The header signal creation circuit 72 creates a header of the small block and the macro block. For example, the header signal creation circuit 72 creates a header signal indicating whether the frame is an intra frame or an inter frame based on the output of the intra-frame / inter-frame identification circuit 63 and outputs the header signal to the MPX 70. The MPX 70 is controlled by the control circuit 73 to transmit the input data in the data array shown in FIG.

Next, the operation of the encoding circuit thus configured will be described.

The input signal is pre-processed in the pre-processing circuit 61 and is input to the subtracter 12 and the switch 62 in block units. When performing intra-frame compression, the intra-frame / inter-frame identification circuit 63 causes the switch 62 to select the output of the pre-processing circuit 61. The block data from the preprocessing circuit 61 is DC
The signal is supplied to a T circuit 13 for two-dimensional DCT processing. DCT circuit 13
Are quantized by a quantization circuit 15 and converted into a variable length code by a variable length coding circuit 16. This variable length code is stored in the buffer 65. Depending on the accumulation state of the buffer 65, constant (rate) control of the data amount is performed. That is, the rate control circuit 67 controls the variable length encoding circuit 16 to regulate the upper limit of the data length. The rate control circuit 64
Controls the quantization coefficient based on the output of the rate control circuit 67 and the DCT transform coefficient to adjust the data length.

On the other hand, when performing inter-frame compression, the output of the pre-processing circuit 61 is given to the subtractor 12. The data of the previous frame subjected to motion compensation is input to the subtractor 12 as a predicted value, and the subtracter 12 outputs a two-input difference signal to the DCT circuit 13 via the switch 62. The output of the quantization circuit 15 is inversely quantized by the inverse quantization circuit 21, subjected to inverse DCT processing by the inverse DCT circuit 22, returned to the original data before input to the DCT circuit 13, and given to the adder 23. The output of the adder 23 is supplied to an inter-frame prediction circuit 68, which obtains a prediction value based on the motion vector from the motion detection circuit 26, outputs the predicted value to the subtractor 12, and outputs the addition value via a switch 69.
Return to 23. That is, the adder 23 locally obtains difference data, and the inter-frame prediction circuit 68 obtains a prediction value from the difference data and the motion vector. The intra-frame / inter-frame identification circuit 63 controls whether to perform intra-frame compression or inter-frame compression based on an external control signal and a motion detection signal.

Thus, the variable length coding circuit 16 obtains the variable length data of the inter frame and the variable length data of the intra frame, the rate control circuit 64 obtains the quantization coefficient, the motion detection circuit 26 obtains the motion vector, and obtains the MPX 70 To supply.

Further, the data length measurement circuit 66 measures the data length of the block from the variable length code, accumulates the data length of the block, obtains the data length of the small block, and outputs it to the MPX 70. Further, the data length measuring circuit 71 accumulates the small block data length, obtains the macro block data length, and outputs it to the MPX 70. Further, the header signal creation circuit 72 creates a header of the macro block and the small block and outputs the header to the MPX 70. Note that the data length measurement circuit is used during intra-frame compression.
The output of 66 is the intra data length.

The MPX 70 is controlled by the control circuit 73 to select input data, order the data, and output the data. Thus, data can be arranged and transmitted in a data format using the system of A = A1 in FIG.

Although the data length data of the headers of the macro block and the small block are not input to the data length measurement circuits 66 and 71, the macro block data length 51 and the intra data length 56 are not used in the format of FIG. It may or may not include the data length of the header. Control circuit 73
The data length of the header is easily obtained by the control circuit 73. Therefore, when the data length of the header is included in the macro block data length 51 and the intra data length 56, the data may be provided from the control circuit 73 to the data length measurement circuits 66 and 71.

The system of A = A2, A3 in FIG. 1 is adopted in a recording medium such as a VCR. When these systems are selected, the rate control circuit 67
Let the value A of the quantization coefficient from 64 be A2 or A3. A =
In the case of A2, the data length adjusting circuit 74 is a rate control circuit.
Under the control of 67, adjustment bit data corresponding to the data adjustment bit length is output to MPX 70 via buffer 65. As a result, the data formats shown in FIGS. 8 and 9 are obtained. If A = A3, the control circuit 73 causes the MPX 70 to output a control signal indicating a modification instruction.

Incidentally, the system of A = A2 may be adopted also in data transmission from a broadcasting station. For example, when data becomes available due to a packet and the buffer 65 underflows.In this case, the rate control circuit 67 controls the data length adjustment circuit 74 to adjust the bit length to a predetermined bit length. Generate.

FIG. 11 is a block diagram showing a decoding circuit for decoding transmission data of the data format of FIG.

The header extraction circuit 81 of the decoding circuit extracts a macro block header and a small block header from the encoded data. The output of the header extraction circuit 81 is provided to a variable length decoding circuit 82, a control circuit 83, a quantization coefficient circuit 84, and a motion vector extraction circuit 85. The variable length decoding circuit 82 performs variable length decoding on the input data and outputs the result to the buffer 86. The control circuit 83 is provided with data of an intra data length, a macro block data length, and an adjustment bit length.The control circuit 83 controls the variable length decoding circuit 82 using these data, thereby preventing error propagation. Check whether the input block data is correct. The control circuit 83 is also provided with a header signal, identifies whether the data is compressed data within a frame or compressed data between frames, and controls a switch 89 described later.

The output of the buffer 86 is supplied to an inverse quantization circuit 87. The quantization coefficient circuit 84 extracts a quantization coefficient from the output of the header extraction circuit 81 and supplies it to the inverse quantization circuit 87.The inverse quantization circuit 87 inversely quantizes the variable-length decoded output using the quantization coefficient. And outputs it to the inverse DCT circuit 88. Inverse DCT circuit 88
Performs inverse DCT processing on the inverse quantized output to restore the original data, and outputs the data to the switch 89 and the adder 90. The switch 89 selects the decoded data from the inverse DCT circuit 88 and outputs it to the memory 92 when the control circuit 83 indicates that the input data is intra-frame compressed data.

On the other hand, the motion vector extraction circuit 85 extracts a motion vector from the output of the header extraction circuit 81 and outputs it to the prediction decoding circuit 91. The predictive decoding circuit 91 is provided with decoded data of the previous frame from the memory 92, performs motion compensation on the data of the previous frame by using a motion vector, and outputs the data to the adder 90. The adder 90 decodes the inter-frame compressed data by adding the output of the predictive decoding circuit 91 and the output of the inverse DCT circuit 88, and outputs the decoded data to the switch 89. switch
89 is controlled by the control circuit 83 to select the output of the adder 90 and to store the
Output to 92.

In this embodiment, the quantization coefficient circuit 84 determines the value of the quantization coefficient. That is, the quantization coefficient circuit
84 is an inverse quantization circuit as it is if A = A1
When A = A2, a signal indicating that the input data is an adjustment bit is output to the control circuit 83 so that the adjustment bit length can be grasped. As a result, the control circuit 83 stops the decoding operation of the variable length decoding circuit 82. The control circuit 83 stops decoding while data of the data length indicated by the adjustment bit length is input, and then gives an instruction to restart decoding.

When A = A3, the quantization coefficient circuit 84 gives a modification instruction to the buffer read instruction circuit 94. When the modification instruction is given, the buffer read instruction circuit 94 controls the buffer 86 to stop reading data, and controls the memory control circuit 93 to prohibit writing to the memory 92.
As a result, the data in the memory 92 is not updated with the decoded data of the block or the small block in which the modification instruction has been issued. That is, for these blocks, the decoded data of the previous frame remains without being updated. It should be noted that a request for a modification instruction is generated from the variable length decoding circuit 82 even when a variable length decoding error occurs in the buffer read instruction circuit 94.

Next, the operation of the decoding circuit thus configured will be described with reference to the timing charts of FIGS. FIG. 12 is for explaining a system in which A = A2, and FIG. 13 is for explaining a system in which A = A3. In FIGS. 12 and 13, H indicates a header.

The data input to the decoding circuit is supplied to a header extracting circuit 81 to extract a header signal. The variable length decoding circuit 82 performs variable length decoding on the output of the header extraction circuit 81 and outputs the result to the buffer 86. The decoded data is fixed-length by the buffer 86 and supplied to the inverse quantization circuit 87. Quantization coefficient circuit
Numeral 84 extracts a quantization coefficient and supplies it to an inverse quantization circuit 87. The inverse quantization circuit inversely quantizes the variable-length decoded data using the quantization coefficient. The inverse DCT circuit performs an inverse DCT process on the inverse quantized output and decodes the original data. If the input data is compressed data in a frame, the control circuit 83 causes the switch 89 to select the output of the inverse DCT circuit 88 and
The decoded output from the CT circuit 88 is stored in the memory via the switch 89.
Stored in 92. If the data is inter-frame compressed data, the output of the inverse DCT circuit 88 is supplied to the adder 90 to be added to the motion-compensated previous frame data from the predictive decoding circuit 91. As a result, a decoded output of the inter-frame compressed data is obtained, and the decoded output is stored in the memory 92 via the switch 89.

Now, it is assumed that the input data shown in FIG. As shown in FIG.
(N + 1) and (n + 4) macroblocks are coded data, that is, data obtained by branching according to A = A1 at the time of encoding, and (n + 2) and (n + 3) macroblocks are adjustment bit data, that is, A = data obtained by branching according to A2. When the quantization coefficient circuit 84 detects from the output of the header extraction circuit 81 that the quantization coefficient of the data of the n macroblocks is A = A1, the buffer read instruction circuit 94 inverts the decoded data from the variable length decoding circuit 82. The output to the quantization circuit 87 is instructed. The buffer read instruction circuit 94 generates a buffer read pulse shown in FIG. 12D, and the decoded output shown in FIG. 12C is output to the inverse quantization circuit 87.

Here, when the data of the (n + 2) macroblock is input, the quantization coefficient circuit 84 detects that A = A2, and outputs a signal indicating that the input data is an adjustment bit to the control circuit. Output to 83. The control circuit 83 gives an instruction to the variable length decoding circuit 82 to stop the decoding operation as shown in FIG. On the other hand, no buffer read pulse is generated from the buffer read instruction circuit 94 and no data is supplied to the inverse quantization circuit 87, as shown in FIG.

When the data of the (n + 4) macroblock is input, the decoding operation is restarted, and the decoded data of the (n + 4) macroblock is written into the memory 92. Thus, the input intra-frame data is reliably decoded.

Next, it is assumed that the input data sequence shown in FIG. As shown in FIG.
Encoded data is transmitted to macroblocks n, (n + 1), and (n + 3), and (n + 2), (n + 4), (n
+5) No data is transmitted for the macroblock.

When the data of the (n + 2) macroblock is input, the quantization coefficient circuit 84 detects that A = A3 from the output of the header extraction circuit 81, and outputs a modification instruction to the buffer read instruction circuit 94. I do. The buffer read instruction circuit 94 gives an instruction to the buffer 86 to stop reading the decoded output. Also, the buffer read instruction circuit 94
Also gives an instruction to the memory control circuit 93 to prohibit updating of the address of the memory 92 corresponding to the (n + 2) macroblock. Thus, it is possible to modify the portion corresponding to the adjustment bit with the data of the previous frame.

FIG. 14 is an explanatory diagram showing a data structure according to another embodiment of the present invention. 14, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The small block 100 of this embodiment has A = A 1,
A = A2 and A = A3 are divided into two branches A = A1 and A = A3.
Change to branch, adjust bit 101 following variable length data 57
Is different from the embodiment of FIG. Adjustment bit 101
Corresponds to the branch of A = A2 in FIG.

In the data format configured as described above, data that does not exist as a Huffman code (for example, a data string of all “1”) is added as the adjustment bit 101. As a result, the adjustment bits 101 are processed as data that cannot be decoded. After all, A = A in FIG.
Acts as a justification bit, similar to the branch of 2.

FIG. 15 is an explanatory diagram showing a data structure according to another embodiment of the present invention. 15, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, the basic quantization coefficient 111 of the macro block is arranged before the small block 110. Assuming that the value of the basic quantization coefficient 111 is A 'and the difference between A' and the basic quantization coefficient of each small block is A ", A '+ A" is the quantization coefficient B of the small block 110. At the head of the small block 110, a coefficient correction 112 for the quantized coefficient having the value A "is arranged. If the basic quantized coefficient value A 'of the quantized coefficient 111 is A1', the process branches to the coefficient correction 112. , A '= A2', the process branches to a quantization coefficient 113.
113 is the data of the quantization coefficient B of the small block. FIG. 1 shows a branch when the value of the quantization coefficient 113 is B1, B2, B3.
Are the same as the branches of A1, A2 and A3.

According to the data format configured as described above, branching is performed according to the value A 'of the basic quantization coefficient. That is, when the data is reproduced discontinuously, the quantization coefficient B of the small block cannot be obtained from the basic quantization coefficient A 'and the difference A ". In such a case, A' = A2 'enables the transmission of the quantized coefficient B. Other functions and effects are the same as those of the embodiment of FIG.

As described above, according to the present invention, format conversion on the receiving side is facilitated, decoding using discontinuous data is enabled effectively, and data utilization efficiency is reduced. This has the effect that the propagation of errors can be suppressed without any problem.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing one embodiment of a high-efficiency encoding / decoding system according to the present invention.

FIG. 2 is an explanatory diagram for explaining a method of configuring the data in FIG. 1;

FIG. 3 is an explanatory diagram for explaining a method of configuring the data in FIG. 1;

FIG. 4 is an explanatory diagram for explaining a data array of block data.

FIG. 5 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 6 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 7 is an explanatory diagram for explaining a branch of A = A2.

FIG. 8 is an explanatory diagram for explaining a branch of A = A2.

FIG. 9 is an explanatory diagram for explaining a branch of A = A2.

FIG. 10 is a block diagram illustrating an example of an encoding circuit.

FIG. 11 is a block diagram illustrating an example of a decoding circuit.

FIG. 12 is a timing chart for explaining the operation of FIG. 11;

FIG. 13 is a timing chart for explaining the operation of FIG. 11;

FIG. 14 is an explanatory view showing another embodiment of the present invention.

FIG. 15 is an explanatory view showing another embodiment of the present invention.

FIG. 261 is an explanatory diagram for describing a compression method of the recommendation proposal of H.261.

FIG. 17 is a block diagram showing a recording side of a recording / reproducing apparatus adopting predictive coding.

FIG. 18 is an explanatory diagram showing a configuration of a macroblock in a conventional example.

FIG. 19 is an explanatory diagram showing a data stream of a recording signal.

FIG. 20 is a block diagram showing a decoding side (reproduction side) of the recording / reproduction device.

FIG. 21 is an explanatory diagram for describing a recording track created on a recording medium by a VCR.

[Explanation of symbols]

50: small block, 51: macro block data length, 52: macro block header, 53: quantization coefficient, 54: small block header, 56: intra data length, 57: variable length data, 58: data adjustment bit length, 59 … Adjustment bit data

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N ^7/ 24-7/68 G11B 20/12 H04N 5/92

Claims (2)

(57) [Claims] 1. A small block constituted by at least one group of blocks which is a coding unit of input data, and a macro block data length constituted by at least one small block and indicating a data length at the head thereof. The small block is configured by a group of at least one or more pieces of data obtained by performing variable length coding of input data for each block as a coding unit as a first system. Variable length data, header information of the variable length data, and a small block data length indicating the data length, a second system having adjustment bit data and its data length, and a third system having Having a modification instruction signal, selecting at least one of the first to third systems as a coefficient based on an encoding characteristic of the variable length data; High-efficiency coding and decoding system characterized by transmitting by including data for. 2. An encoding means for performing variable length encoding of input data for each block as an encoding unit and outputting the data, and a data length measuring means for measuring and outputting a data length from an output of the variable length encoding means. A header information creating means for creating and outputting header information for the output of the encoding means; and a small block constituted by at least one or more of the blocks, wherein the output of the encoding means and the data length measuring means The output and the output of the header information creating means are packetized as a first system, and the predetermined adjustment bit data and information on its data length are packetized as a second system.
A means for packetizing the modification instruction signal as a system of
A first packet unit for performing packetization by at least one of the first to third systems; and a macroblock formed by at least one or more of the small blocks, and an output of the first packet unit includes: A high-efficiency encoding / decoding system, comprising: a second packet unit for packetizing and outputting the output of the data length measuring unit and the output of the header information creating unit.