JPH07162805A - Special reproducing device for compressed image - Google Patents

Abstract

PURPOSE:To provide an inverted regenerative image from compressed image data with small scale configuration. CONSTITUTION:The output of an adder 20 is applied to a compression and extension circuit 32. The compression and extension circuit 32 switches compression processing and extension processing for each frame corresponding to a compression/extension switching signal. Coded data thinned for each frame are prepared from the compression and extension circuit 32 and stored in memories 33 and 34. These coded data are read out in an inverse frame order, decoded by the compression and extension circuit 32 and outputted. An image memory 23 interpolates the output of a data order conversion part 31 and the inverted regenerative image is provided.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a special playback device for compressed images suitable for disk systems, digital VTRs and the like.

[0002]

2. Description of the Related Art In recent years, a disk system and a digital VTR for digitally compressing and recording and reproducing image data
Etc. have been commercialized. In this kind of compressed image recording / reproducing apparatus, MPEG which is an international standard is used as a compression method.
High efficiency coding using (Moving Picture experts group) may be adopted. High-efficiency coding is to code image data at a smaller bit rate using DCT (discrete cosine transform). In the DCT, one frame is divided into a plurality of blocks (m pixels × n horizontal scanning lines), and the video signal is converted into frequency components in units of blocks, whereby redundancy in the spatial axis direction can be reduced.
This method is described in detail in the literature (Hiroshi Yasuda, "International Standard for Multimedia Coding," Maruzen).

Furthermore, in MPEG, not only compression by DCT (intraframe compression) is performed within one frame, but also interframe compression for reducing redundancy in the time axis direction by utilizing correlation between frames is adopted. . The inter-frame compression is to further reduce the bit rate by utilizing the property that a general moving image is very similar to the preceding and following frames and obtaining the difference between the preceding and following frames and performing the DCT process on the difference value. . High compression is possible because the image is also compressed by using the correlation in the time direction, and in recent years, it has been adopted as a disk system for karaoke.

FIG. 4 is a block diagram showing a compressed image recording / reproducing apparatus adopting the MPEG system.

In the recording system, an input digital video signal is input to the input terminal 1 in block units of horizontal 8 pixels × vertical 8 pixels. This input signal is DC through the differencer 2.
It is given to the T circuit 3. The differentiator 2 obtains the difference between the current frame signal from the input terminal 1 and the motion-compensated predicted frame data described below, and outputs the difference to the DCT circuit 3 as a prediction error. That is, inter-frame coding for coding difference data is performed by utilizing redundancy of images between frames.

A signal whose one block is composed of 8 × 8 pixels is input to the DCT circuit 3, and the DCT circuit 3 converts the input signal into frequency components by an 8 × 8 two-dimensional DCT processing. This makes it possible to reduce spatial correlation components. That is, the output (transformation coefficient) of the DCT circuit 3 is given to the quantization circuit 4, and the quantization circuit 4 requantizes the transformation coefficient with a predetermined quantization coefficient to reduce the redundancy of the signal of one block. .

The quantized data from the quantizing circuit 4 is given to the variable length coding circuit 5 and, for example, Huffman coding is performed based on the result calculated from the statistical code amount of the quantized output. As a result, data having a high appearance probability is assigned a short bit, and data having a low appearance probability is assigned a long bit to further reduce the transmission amount. The coded output from the variable-length coding circuit 5 is given to the parity addition circuit 6, and the parity for error correction is added and output to the output terminal 7.

By the way, in the inter-frame coding, if the difference between the previous or subsequent frame and the current frame is simply obtained,
The difference is large when there is a motion in the image. Therefore, the position of the previous frame or the subsequent frame corresponding to the predetermined position of the current frame is calculated to detect the motion vector, and the difference is calculated at the pixel position corresponding to this motion vector to perform motion compensation and reduce the difference value. I have to.

The prediction frame is obtained by decoding the quantized output. That is, the output of the quantization circuit 4 is the inverse quantization circuit 8, the inverse DCT circuit 9,
It is also given to the local decoding unit 12 constituted by the adder 10 and the predictor 11. The inverse quantization circuit 8 of the local decoding unit 12 inversely quantizes the quantized output, and further inverse DCT
In the circuit 9, inverse DCT processing is performed to restore the original video signal.
Since the output of the differentiator 2 is difference information, the inverse DCT circuit 9
Is also difference information. The output of the inverse DCT circuit 9 is given to the adder 10. The output of the adder 10 is fed back to the adder 10 via the predictor 11, and the adder 10 adds the difference data to the predicted frame data from the predictor 11 and the current frame data (local decoded data). Play to predictor 11
Output to. The local decoding unit 12 can cancel out the error amount due to the DCT processing and the quantization processing.

The predictor 11 delays the local decoded data from the adder 10 for, for example, one frame period, and detects the motion vector of the data of the current frame from the input terminal 1 with the delayed local decoded data as a reference. The predictor 11 motion-compensates the local decoded data according to the obtained motion vector, and outputs it as a prediction frame to the difference unit 2. Thus, the motion-compensated previous frame data is supplied to the differentiator 2 as a prediction frame,
DCT processing is performed on the prediction error from the differentiator 2.

As described above, in the recording side apparatus, the compression rate is improved by adopting the inter-frame compression as well as the intra-frame compression. For example, when a digital video signal of a still image is input, the data from the predictor 11 and the input data substantially match, and the output of the difference unit 2 becomes substantially 0,
The code amount is extremely small.

In the MPEG system, an image unit GOP (group of pictures) is composed of at least one intraframe compression frame and interframe compression frame. For example, 15 frames make up one GOP, and one in-frame compressed frame is provided in one GOP.

On the other hand, in the reproducing system, the encoded output is input through the input terminal 15. This coded output is error-corrected by the error correction circuit 16, and then the variable-length decoding circuit 17
Give to. The variable length decoding circuit 17 obtains the original fixed length data by the variable length decoding process. The output of the variable length decoding circuit 17 is inversely quantized by the inverse quantization circuit 18, and the inverse DCT
Inverse DCT processing is performed by the circuit 19 and applied to the adder 20. The configurations of the inverse quantizing circuit 18 and the inverse DCT circuit 19 are the same as those of the inverse quantizing circuit 8 and the inverse DCT circuit 9 of the local decoding unit 12 on the recording side, respectively.
In a package medium such as R, these circuits are usually shared.

Inverse DC for interframe compressed frames
The output of the T circuit 19 is difference information, and the adder 20 outputs the inverse DC.
The video signal of the current frame is reproduced by adding the decoded output of the previous frame and the decoded output of the current frame from the T circuit 19. The output of the adder 20 is supplied to the image memory 23 via the switch 21 and also to the GOP memory 22. During normal reproduction, the switch 21 selects the output of the adder 20, and the output of the adder 20 is given to the image memory 23. The image memory 23 field-decodes the decoded output and outputs it to the output terminal 24.

As described above, the inter-frame compressed frame encodes only the prediction error, and the decoded output cannot be obtained only from the inter-frame compressed frame.
That is, the intra-frame compressed frame inserted in GOP units must be first decoded, and then the other inter-frame compressed frames must be decoded in the encoding order. Therefore, even in the case of reverse reproduction, it is necessary to reproduce each coded frame of 1 GOP in the forward direction and sequentially decode it.

That is, at the time of reverse reproduction, while reproducing the encoded data in each GOP in the forward direction, the encoded data of a series of GOPs is reproduced in the reverse order and input to the input terminal 15. At the time of reverse reproduction, the switch 21 selects the GOP memory 22. G
The OP memory 22 has two areas for storing the decoded output of 1 GOP, and when writing to one area, reading is performed from the other area. The decoded output of 1 GOP from the adder 20 is stored in one area of the GOP memory 22.
The decoded output for 1 GOP stored in the other area is read out in the reverse frame order which is the reverse order of the recording and is supplied to the image memory 23 via the switch 21. This allows the image memory 23
The reverse reproduction image is obtained by the video signal from.

As described above, when performing reverse reproduction, G
After the encoded data in the OP is reproduced in the forward direction and decoded, the GOP memory 22 is used to output the data in the reverse frame order. However, in the case of reversing reproduction of the compressed data of the MPBG method described above, it is necessary to provide two memories having a capacity of 1 GOP (for example, 15 frames), which causes a problem of enormous hardware scale. It was

[0018]

As described above, in order to enable reverse reproduction in an image recording / reproducing apparatus which has conventionally adopted interframe coding, a huge amount of memory is required and the hardware scale is extremely large. There was a big problem.

It is an object of the present invention to provide a special reproduction device for compressed images which enables reverse reproduction on a relatively small scale.

[Structure of Invention]

A special playback device for compressed images according to the present invention encodes an image encoded with a predetermined number of inter-frame compressed frames and at least one intra-frame compressed frame as an encoding unit. Decoding means for receiving data and decoding the coded data to obtain decoded data in the coding unit, and data for compressing the decoded data for each coding unit in a frame Compression and decompression means for decompressing the data, storage means for storing the data compressed by the compression and decompression means, and storage means for reading the stored data in reverse frame order and giving the data to the compression and decompression means for decoding. And switching means for switching the compression processing and the expansion processing of the expansion means at a predetermined cycle, and the decoding processing of the compression and expansion means at a predetermined cycle. The given subtracted image signal interpolation is obtained by including an interpolation means for obtaining a reverse reproduction images.

[0021]

In the present invention, the compression / expansion means compresses the decoded data for each coding unit in the frame again and stores it in the storage means. The compressed data stored in the storage means is read in the reverse frame order and decoded by the compression and decompression means. The data is compressed and then stored in the storage means, and the storage means can be configured with a relatively small storage capacity. The decoded data from the compression / expansion means is data in the reverse frame order thinned out in a predetermined cycle, and the interpolation means interpolates to obtain an image signal for reverse reproduction.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a reproduction system of a special reproduction device for compressed images according to the present invention. In FIG. 1, the same components as those in FIG. 4 are designated by the same reference numerals.

The structure of the recording system is the same as that of the recording system of FIG. In FIG. 1, reproduction data (transmission data) of encoded output, to which error correction parity has been added after being subjected to DCT processing, quantization processing and variable length coding processing, is input to an input terminal 15. This reproduced data is given to the error correction circuit 16, and the error correction circuit 16 performs error correction using the parity included in the reproduced data and outputs it to the variable length decoding circuit 17.

The variable length decoding circuit 17 converts the input variable length data into fixed data by the reverse processing of the variable length coding processing of the recording system and outputs it to the inverse quantization circuit 18. The inverse quantization circuit 18 inversely quantizes the input data using the quantized coefficient in the quantization processing of the recording system, and outputs it to the inverse DCT circuit 19. The inverse DCT circuit 19 returns the data converted into the frequency component to the original coordinate axis component by the inverse processing of the DCT processing of the recording system and outputs it to the adder 20. The adder 20 is an inverse DCT circuit of the prediction frame for the inter-frame compression frame.
The decoded output of the current frame is obtained by adding the output of 19 to the output of the switch 21 and the data order conversion unit 31.

FIG. 2 is a block diagram showing a concrete configuration of the data order conversion unit 31 in FIG.

The output of the adder 20 is the terminal of the data order conversion unit 31.
It is given to the terminal a of the switch 42 via 41. Switch 42
Selects and switches terminals a and b for each frame, and
Is supplied to the DCT and inverse DCT circuit 43, and the output from the DCT and inverse DCT circuit 43 is output to the terminal 46 via the terminal b.

The DCT and inverse DCT circuit 43 includes a switch 42.
And inverse quantization circuit by DCT processing data from
The output of the quantization and dequantization circuit 44 is inversely DCT processed and output to the terminal 46 via the switch 42. The quantizer and inverse quantizer circuit 44 includes a DCT and an inverse DCT.
The output of the circuit 43 is quantized and output to the variable length coding and variable length decoding circuit 45, and the output of the variable length coding and variable length decoding circuit 45 is dequantized to DCT and inverse DC.
Output to the T circuit 43. The variable length coding and variable length decoding circuit 45 variable length codes the output of the quantization and dequantization circuit 44 and outputs it to the memories 33 and 34 via the switch 35, and at the same time, it is read from the memories 33 and 34. The data is input through the switch 36, subjected to variable length decoding processing, and output to the quantization and dequantization circuit 44.

The switch 35 is switched every GOP. The switch 36 selects the memory 34 when the switch 35 selects the memory 33, and selects the memory 33 when the switch 35 selects the memory 34. DCT and inverse DCT
The compression / expansion circuit 32 configured by the circuit 43, the quantization / inverse quantization circuit 44, and the variable-length coding / variable-length decoding circuit 45 divides the compression processing and the expansion processing in time by the compression / expansion switching signal. It is designed to switch with. The compression / expansion circuit 32 uses only intraframe compression adopted in the JPEG standard, for example.

The DCT circuit and the inverse DCT circuit have the same hardware configuration. Therefore, in the present embodiment, the DCT and the inverse DCT which form the compression and expansion circuit 32.
As the circuit 43, either one of the DCT circuit and the inverse DCT circuit is used, and the processing is switched to the time division on a frame-by-frame basis to perform both the DCT processing and the inverse DCT processing. Similarly, the hardware configurations of the quantization circuit and the inverse quantization circuit and the hardware configurations of the variable length coding circuit and the variable length decoding circuit are the same. Therefore, also in the quantizing and dequantizing circuit 44, both the quantizing process and the dequantizing process are performed by switching the process of one circuit to time division in frame units. Further, also in the variable length coding / variable length decoding circuit 45, both the variable length coding processing and the variable length decoding processing are performed by switching the processing of one circuit to time division in frame units. .

Further, as shown in FIG. 4, the recording system has a DCT circuit 3, an inverse DCT circuit 9, a quantizing circuit 8, an inverse quantizing circuit 8 and a variable length coding circuit 5, and at the time of reproduction. Since these circuits are not used, these circuits are used as the respective circuits of the compression / expansion circuit 32.

The output of the DCT and inverse DCT circuit 43 is shown in FIG.
It is given to the image memory 23 via the switch 21 as the output of the compression and decompression circuit 32. The switch 21 selects the output of the adder 20 during normal reproduction, and selects the output of the data order conversion unit 31 during reverse reproduction. The image memory 23 converts the output of the switch 21 into a field and outputs it to the output terminal 24.

Next, the operation of the embodiment thus constructed will be described with reference to the timing chart of FIG. 3A shows a frame pulse, FIG. 3B shows a reproduced image, FIG. 3C shows a compression / expansion switching signal, and FIG. 3D shows writing to the memories 33 and 34. Shown in FIG.
(E) shows reading from the memories 33 and 34, and FIG.
Shows the output of the data order conversion unit 31, and FIG. 3 (g) shows the output of the image memory 23.

In a recording system (not shown), the image signal is subjected to DCT processing, quantization processing and variable length coding processing to add parity, and then recorded on, for example, a magnetic recording medium. For compression in the recording system, intraframe compression and interframe compression are adopted, and the intraframe compression frame is assumed to be inserted in GOP units. A reproduced image signal reproduced from the magnetic recording medium is input to the input terminal 15. This reproduced image signal is given to the error correction circuit 16 and subjected to error correction using parity, and then given to the variable length decoding circuit 17. The variable length decoding circuit 17 restores the input data to fixed length data. The fixed-length data is inversely quantized by the inverse quantization circuit 18, inverse DCT processing is performed by the inverse DCT circuit 19, and the signal before the DCT processing in the recording system is restored. The adder 20 reproduces the image data of the current frame by adding the inter-frame compressed frame to the predicted frame.

The decoded output of the adder 20 is output to the switch 21 and also to the switch 21 via the data order conversion unit 31. At the time of normal reproduction, the switch 21 selects the output of the adder 20, and the decoded output from the adder 20 is given to the image memory 23 for field formation. Thus, the output terminal
A reproduced image signal is obtained at 24.

Here, reverse reproduction is performed. In this case, a series of GOP encoded data are reproduced in reverse order and input to the input terminal 15. For example, coding order ... GOP
3, GOP2, GOP1, ... The encoded data recorded on the magnetic tape is ..., GOP1, GOP2, GOP3.
Play in this order. Even in this case, in order to enable decoding of the inter-frame compressed frame, the encoded data in each GOP is reproduced in the forward direction. For example, assuming that each GOP is composed of 8 compressed frames, and that the 8 compressed frames that compose GOP 1 are recorded in the order of intra-frame compressed frame A 1, inter-frame compressed frame A 2, A 3, ... Is the compressed frame A1, A2
,…, A8. It is assumed that GOP2 and GOP3 are composed of compressed frames B1 to B8 and compressed frames C1 to C8, respectively. That is, for the actual coding order C1 to C8, B1 to B8, A1 to A8, the compressed frames are input to the input terminal 15 in the playback order shown in FIG.

Since the reproduction order of the compressed frames in each GOP is the same as that in the normal reproduction, the same decoding process as in the normal reproduction is performed, and the decoded data of each frame is added from the adder 20 in each GOP unit. Is output. This decoded data is sent to the DCT and inverse DCT via the switch 42 of the data order conversion unit 31.
Supply to the circuit 43.

The DCT and inverse DCT circuit 43 is shown in FIG.
During the "H" period of the compression / expansion switching signal shown in, the input decoded data is DCT processed. During the "H" period of the compression / expansion switching signal, the quantizing and dequantizing circuit 44 performs the quantizing process, and the variable length coding and variable length decoding circuit 45 performs the variable length coding process. As a result, the decoded data from the adder 20 is encoded again during the "H" period of the compression / expansion switching signal. As shown in FIG. 3 (c), the compression / expansion switching signal is compressed frames A1 and A3 every other frame.
, ..., B1, B3, ..., C1, C3, ... Become "H" during the input period, and the decoded data of these compressed frames are again intra-coded and given to the switch 35.
The switch 35 switches in units of 1 GOP and supplies the encoded data to either one of the memories 33 and 34. Note that FIG.
In (d) and (e), each compressed frame A1 to A8, B
Intra-frame encoded data of the decoded data of 1 to B8 and C1 to C8 are A1 'to A8' and B1 'to B8, respectively.
′, C1 ′ to C8 ′. Compression and decompression circuit 3
Frame thinning is performed by 2, and the encoded data every other frame is stored in the memories 33 and 34 as shown in FIG.
Is stored in either one of

Coded data for one GOP (four frames) is stored in the memories 33 and 34, and then the next GOP2 is stored.
The decoded data of is input from the adder 20 to the compression and expansion circuit 32. Also in this case, during the "H" period of the compression / expansion switching signal, the decoding data of the compressed frames B1, B3, ...

On the other hand, during the "L" period of the compression / expansion switching signal, the DCT and inverse DCT circuit 43 performs inverse DCT processing,
The quantization and dequantization circuit 44 performs dequantization processing, and the variable length coding and variable length decoding circuit 45 performs variable length decoding processing. That is, as shown in FIG. 3E, the encoded data of GOP1 stored in the memories 33 and 34 is in the "L" period of the compression / expansion switching signal, that is, the compressed frames B2, B4, ... Of GOP2. During the input period of, the data is read through the switch 36 in the reverse order of the writing order. This encoded data is variable length decoded by the variable length encoding and variable length decoding circuit 45,
Inverse quantization by the quantization and inverse quantization circuit 44, DCT
And the inverse DCT circuit 43 performs inverse DCT processing to restore the original decoded data. The decoded data from the DCT and inverse DCT circuit 43 is sent to the switch 21 via the switch 42 and the terminal 46.
To the image memory 23.

The frame-thinned decoded data is input to the image memory 23, and the image memory 23 repeats the input decoded data to perform interpolation to perform interpolation, as shown in FIG. The image signal shown in is output to the output terminal 24. As shown in FIG. 3 (g), the image signals appearing at the output terminal 24 are in the reverse frame order, and a reverse reproduction image can be obtained.

As described above, in this embodiment, each GO is
The data reproduced and decoded in the forward direction for each P is re-encoded by the compression and expansion circuit 32, stored in the memories 33 and 34, read in the reverse frame order, and then decoded.
The decoded data in the reverse frame order is obtained. Since the data is stored in the memories 33 and 34 after being encoded, the memories 33 and 34 need only store compressed data of 1 GOP, respectively.
The capacity of 3, 34 can be significantly reduced compared to the conventional one. The compression / expansion circuit 32 performs both compression processing and decompression processing by sharing the compression circuit and the decompression circuit and switching the processing to time division in frame units. Therefore, the increase in circuit scale can be reduced. Further, the compression / expansion circuit 32 can be configured by diverting the circuit of the recording system, and the increase of the circuit scale can be significantly suppressed.

[0042]

As described above, according to the present invention, there is an effect that reverse reproduction can be made possible on a relatively small scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a special playback device for compressed images according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of a data order conversion unit in FIG.

FIG. 3 is a timing chart for explaining the operation of the embodiment.

FIG. 4 is a block diagram showing a compressed image recording / reproducing device.

[Explanation of symbols]

31 ... Data order conversion unit, 32 ... Compression and expansion circuit, 33, 34 ...
memory

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H04N 7/30 7/32 H04N 7/133 Z 7/137 Z (72) Inventor Taishi Ikyama Shinbashi, Minato-ku, Tokyo 3-3-9 TOSHIBA AVEE Co., Ltd. (72) Inventor Kenji Tomizawa 3-3-9 Shimbashi, Minato-ku, Tokyo Inside TOSHIBA AVEE Co., Ltd.

Claims (5)

[Claims] 1. Coded data of an image coded with a predetermined number of inter-frame compressed frames and at least one intra-frame compressed frame as a coding unit is provided, and the coded data is decoded to obtain the coded data. Decoding means for obtaining decoded data in coding units, compression and decompression means for compressing the decoded data for each coding unit in a frame and decompressing the compressed data, and compression by the compression and decompression means Storage means for storing the stored data, reading the stored data in reverse frame order and giving the data to the compression and expansion means for decoding, and switching means for switching the compression processing and expansion processing of the compression and expansion means at a predetermined cycle. And an image signal thinned out in a predetermined cycle by the decoding process of the compression and expansion means is given, and the reverse reproduction is performed by the interpolation process. Special reproducing apparatus for compressed image, characterized by comprising an interpolation means for obtaining the image. 2. The special reproduction apparatus for compressed images according to claim 1, wherein the compression and expansion means diverts a part of a decoding processing circuit of the decoding means. 3. The compression and expansion means diverts a part of an encoding circuit for creating encoded data input to the decoding means. The special playback device for compressed images according to one aspect. 4. The special reproduction apparatus for a compressed image according to claim 1, wherein the compression / decompression means switches between compression processing and decompression processing in one frame cycle. 5. The special reproduction device for a compressed image according to claim 1, wherein the storage means has a storage capacity for two encoding units.