JPH05276491A - High-efficiency coding/decoding device - Google Patents

Abstract

PURPOSE:To improve the picture quality of regenerative images at the time of special reproducing. CONSTITUTION:A low compressibility circuit 81 processes input video signals at low compressibility, and a high compressibility circuit 83 processes input video signals at high compressibility. The low compressibility processed signals and high compressibility processed signals are respectively added to a low compression flag and a high compression flag and supplied to a switch 86. A recording position deciding circuit 88 controls the switch 86 corresponding to track numbers. Thus, the high compressibility processed signals are outputted from the switch 86 at timing corresponding to a regenerative area at the time of special reproducing, and the low compressibility processed signals are outputted at the other timing. Since the high compressibility processed signals are decoded on the reproducing side at the time of special reproducing and one image is prepared by selecting one part of plural decoded outputs, the smooth regenerative image can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding / decoding device, and more particularly to a high-efficiency coding / decoding device for improving image quality during special reproduction.

[0002]

2. Description of the Related Art In recent years, digital processing of images has been studied. Magnetic recording / reproducing apparatus for digital image data (V
Various methods are being considered for recording to (CR).
FIG. 14 is an explanatory diagram for explaining the comparison between the position on the screen and the position on the recording track of the recording medium in this VCR. FIG. 14A shows the positions on the screen.
(B) shows the position on the recording track.

FIG. 14A shows a one-frame screen divided into eight parts in the vertical direction. Further, FIG. 14B shows the recording positions of the tracks # 1 to # 9 ... Similarly divided into eight. Recording on the recording medium starts from the lowermost end A of track # 1 and is sequentially performed toward the uppermost end I. For example, if one frame of data is recorded on one track, the data from the uppermost end a to b of the screen is recorded from the lowermost end A to B of the recording medium, and thereafter, b of the screen is similarly recorded.
Data from the bottom edge i to the bottom edge i of the recording medium
It records sequentially until. Further, for example, if one frame data is recorded on two tracks, a through e of the screen are displayed.
The data up to is recorded on the A to I of the # 1 track, and the data of e to i on the screen is recorded on the A to I of the # 2 track.

FIG. 15 is an explanatory diagram showing the relationship between the trace pattern and the reproduction envelope at the time of 3 × speed reproduction. Figure 15
(A) shows a trace pattern in the case where the head scan time is plotted on the horizontal axis and the track pitch or the tape travel distance is plotted on the vertical axis when the data is reproduced at a triple speed. The symbols + and − in FIG. 15A indicate the normal azimuth of the reproducing head, respectively. Also, in the figure, the numbers indicate the numbers of the reproduction tracks, the odd tracks are plus azimuth, and the even tracks are minus azimuth. FIGS. 15B to 15D show a reproduction envelope by a normal head, a reproduction envelope by a special head, and a composite envelope of both heads, respectively. FIG. 16 is an explanatory diagram showing the structure of the recording / reproducing head.

As shown in FIG. 16, a rotating cylinder 3 having a normal head 1 and a special head 2 is used for recording and reproduction. The rotary cylinder 3 is equipped with a pair of normal heads 1 having different azimuths and a pair of special heads 2 having different azimuths. Be different. As shown by the symbol + in FIG. 15A, the first and third tracks are traced by the plus azimuth normal head 1 in the first scanning period (trace period), and the minus azimuth is traced in the next scanning period. Normally, the head 1 traces the fourth and sixth tracks. In this way, the reproducing head shown in FIG. 15B is obtained by the normal head 1. The second head is traced by the special head 2 in the first scanning period, and the reproduction envelope shown in FIG. 15C is obtained in the same manner. By combining the reproduction output of the normal head 1 and the reproduction output of the special head 2, the combined envelope shown in FIG. 15D is obtained.

Table 1 below shows the reproduction output of the triple speed reproduction (see FIG. 15).
(D)) and the correspondence between the trace position and the position on the frame screen are shown.

[0007]

[Table 1] As shown in FIG. 15D and Table 1, in the first scanning period, the normal head 1 reproduces A to C of the first track # 1 in the first ¼ time, and the next ½. Of the second track # 2 is reproduced by the special head 2 during the above time, and G of the third track # 3 is reproduced by the normal head 1 during the next 1/4 time. Thereafter, similarly, three tracks are reproduced in one scanning period.

When a one-frame screen is recorded on one track, as shown in Table 1, A to C of the first track # 1 correspond to a to c on the screen of the first frame, and
Tracks # 2 C to G correspond to screens c to g of the second frame, and tracks G3 to G of track # 3 correspond to screens g to i of the third frame. Therefore, in this 3 × speed reproduction, as shown in FIG. 17A, the reproduction screen is displayed by combining the pictures at the respective positions of the first to third frames.

When the 1-frame screen is recorded on 2 tracks, as shown in Table 1, A to C of the first track # 1 correspond to a to b of the screen of the first frame, and Tracks # 2 C to G correspond to the frames f to h of the first frame, and tracks G3 to G of the third track # 3 correspond to the screens d to e of the second frame. Further, A to C of the fourth track # 4 correspond to e to f of the screen of the second frame, C to G of the fifth track # 5 correspond to b to d of the screen of the third frame, and Tracks # 6 G through I are third
It corresponds to h to i of the frame screen. Therefore, in this case, as shown in FIG. 17B, the reproduction screen has a mixture of pictures at the respective positions of the first to third frames.

By the way, in recent years, various standardization proposals have been proposed for high-efficiency coding for compressing image data. The high-efficiency coding technique is for coding image data with a smaller bit rate in order to improve the efficiency of digital transmission and recording. For example, CCI
TT (Comite Consultafif Internatinal Telegraphiqu
e et Telephonique) is a standardization recommendation H.264 for video conferencing / video telephony. 261 is proposed. In this recommendation, an intra-frame compressed frame (hereinafter also referred to as an intra frame) I and an inter-frame compressed (Inter-frame or Predictive frame) frame (hereinafter also referred to as an inter frame) P are described. Encoding is used.

FIG. 18 is an explanatory diagram for explaining the compression method of this recommendation.

Frame I is DCT (discrete cosine transform)
The image data of one frame is encoded by the processing. The frame P is the image data encoded by the predictive encoding using the frame I or another frame P. Furthermore, the bit rate is further reduced by performing variable length coding on these coded data. Since the frame I is encoded only by the information in the frame, it can be decoded only by the single encoded data. On the other hand, the frame P is encoded by utilizing the correlation with other image data, and cannot be decoded only by the single encoded data.

FIG. 19 is a block diagram showing the recording side of a conventional high-efficiency coding / decoding apparatus adopting such predictive coding.

The luminance signal Y and the color difference signals Cr and Cb are given to the multiplex processing circuit 11 and multiplexed in block units of 8 pixels × 8 horizontal scanning lines. The sampling rate of the color difference signals Cr and Cb in the horizontal direction is 1/2 of that of the luminance signal Y. Therefore, during the period in which two 8 × 8 luminance blocks are sampled, one 8 × 8 block is sampled for the color difference signals Cr and Cb. As shown in FIG. 20, the multi-processing circuit 11 configures a macro block by four blocks of two luminance blocks Y and one color difference block Cr, Cb. The two luminance blocks Y and the respective color difference blocks Cr and Cb represent the same position on the screen. The output of the multi-processing circuit 11 is given to the DCT circuit 13 via the subtracter 12.

When the intra-frame compression is performed, the switch 14 is off and the output of the multiplex processing circuit 11 is input to the DCT circuit 13 as it is, as described later. DCT circuit 13
A signal in which one block is composed of 8 × 8 pixels is input to the DCT circuit 13, and the DCT circuit 13 converts the input signal into frequency components by an 8 × 8 two-dimensional DCT (discrete cosine transform) process. This makes it possible to reduce spatial correlation components.
That is, the output of the DCT circuit 13 is given to the quantization circuit 15, and the quantization circuit 15 requantizes the DCT output with a predetermined quantization coefficient to reduce the redundancy of the signal of one block. Block pulses are supplied to the multiplexing processing circuit 11, the DCT circuit 13, the quantization circuit 15 and the like which operate in block units.

The quantized data from the quantizing circuit 15 is given to the variable-length coding circuit 16 and, for example, Huffman coding is performed based on the result calculated from the statistical code amount of the quantized output. As a result, data having a high appearance probability is assigned a short bit, data having a low appearance probability is assigned a long bit, and the transmission amount is further reduced. The output of the variable length coding circuit 16 is given to the error correction encoder 17, and the error correction encoder 17 adds the parity for error correction and outputs it to the multiplexing circuit 19.

The output of the variable length coding circuit 16 is also given to the coding control circuit 18. The amount of output data greatly changes depending on the input image. Therefore, the encoding control circuit 18 monitors the output data amount from the variable length encoding circuit 16 and controls the quantization coefficient of the quantization circuit 15 to adjust the output data amount. Further, the coding control circuit 18 may control the variable length coding circuit 16 to limit the amount of output data.

On the other hand, the synchronization / ID generation circuit 20 indicates the frame synchronization (sync) signal, the contents of data, and I indicating the additional information.
The D signal is created and output to the multiplexing circuit 19. The multiplexing circuit 19 composes one sync block of data from the sync signal, the ID signal, the compressed signal data and the parity, and outputs the data to a recording coding circuit (not shown). The recording / coding circuit records and codes the output of the multiplexing circuit 19 according to the characteristics of the recording medium, and then records it on a recording medium (not shown) via a recording amplifier (not shown).

On the other hand, when the switch 14 is on,
The signal of the current frame from the multiplex processing circuit 11 is subtracted from the data of the motion-compensated previous frame, which will be described later, in the subtracter 12 and is given to the DCT circuit 13. That is, in this case, interframe coding is performed in which the difference data is coded by utilizing the redundancy of images between frames. In inter-frame encoding, if the difference between the previous frame and the current frame is simply obtained, the difference becomes large when there is a motion in the image. Therefore, the position of the previous frame corresponding to the predetermined position of the current frame is obtained to detect the motion vector,
By calculating the difference at the pixel position corresponding to this motion vector, motion compensation is performed and the difference value is reduced.

That is, the output of the quantization circuit 15 is also given to the inverse quantization circuit 21. Quantization output is an inverse quantization circuit
Inverse quantization is performed in 15 and further inverse DCT processing is performed in the inverse DCT circuit 22 to restore the original video signal. In addition, D
In CT processing, requantization, inverse quantization and inverse DCT processing,
The original information cannot be completely reproduced, and some information is lost. In this case, since the output of the subtractor 12 is the difference information, the output of the inverse DCT circuit 22 is also the difference information. The output of the inverse DCT circuit 22 is given to the adder 23. The output of the adder 23 is fed back through a variable delay circuit 24 and a motion correction circuit 25 which delays the signal for about one frame period. The adder 23 adds the difference data to the data of the previous frame and the data of the current frame. Is reproduced and output to the variable delay circuit 24.

The data of the previous frame from the variable delay circuit 24 and the data of the current frame from the multiplex processing circuit 11 are applied to the motion detection circuit 26 to detect the motion vector. The motion detection circuit 26 finds a motion vector by, for example, full search motion detection by matching calculation. In full search type motion detection, the current frame is divided into predetermined blocks, and a search range of, for example, horizontal 15 pixels × vertical 8 pixels is set in each block. For each block, matching calculation is performed in the corresponding search range of the previous frame to calculate the approximation between patterns. Then, the block of the previous frame that gives the minimum distortion in the search range is calculated, and the vector obtained by the block of the current frame is detected as the motion vector. The motion detection circuit 26 outputs the calculated motion vector to the motion correction circuit 25.

The motion correction circuit 25 extracts the data of the corresponding block from the variable delay circuit 24, corrects it according to the motion vector, outputs it to the subtracter 12 via the switch 14, and after the time adjustment. Output to the adder 23. Thus
The motion-compensated previous frame data is supplied from the motion compensation circuit 25 to the subtractor 12 via the switch 14, and when the switch 14 is on, the inter-frame compression mode is set. It is in compression mode.

The switch 14 is turned on and off based on the motion determination signal. That is, the motion detection circuit 26 creates a motion determination signal depending on whether or not the magnitude of the motion vector exceeds a predetermined threshold value and outputs it to the logic circuit 27. The logic circuit 27 controls the switch 14 to be turned on and off according to the logic judgment using the motion judgment signal and the refresh cycle signal. The refresh cycle signal is a signal indicating the intra-frame compressed frame I in FIG. When the refresh cycle signal indicates that the frame I is input, the logic circuit 27 turns off the switch 14 regardless of the motion determination signal. When the motion determination signal indicates that the motion is relatively fast and the minimum distortion due to the matching calculation exceeds the threshold, the logic circuit 27 turns off the switch 14 even if the frame P is input, and the block unit is selected. In-frame compression coding is performed with. Table 2 below shows ON / OFF control of the switch 14 by the logic circuit 27.

[0024]

[Table 2] FIG. 21 is an explanatory diagram showing a data stream of a recording signal output from the multiplexing circuit 19.

As shown in FIG. 21, the first input image signal
And the sixth frame is an intra-frame compressed frame I1, respectively.
I6, and the second to fifth frames are converted to interframe compressed frames P1 to P5. The ratio of the data amounts of the frame I and the frame P is (3 to 10): 1.
Although the data amount of the frame I is relatively large, the data amount of the frame P is extremely reduced. The data subjected to the inter-frame compression processing cannot be decoded unless other frame data is decoded.

FIG. 22 is a block diagram showing the decoding side (reproduction side) of the conventional high-efficiency coding / decoding apparatus.

The compressed code data recorded on the recording medium is reproduced by a reproducing head (not shown) and input to the error correction decoder 31. The error correction decoder 31 corrects errors that occur during transmission and recording. Error correction decoder
The reproduced data from 31 is supplied to the variable length data decoding circuit 33 via the code buffer memory circuit 32 and decoded into fixed length data. The code buffer memory circuit 32 may be omitted.

The output of the variable length decoding circuit 33 is an inverse quantization circuit.
Inverse quantization is performed at 34, and inverse D is performed at the inverse DCT circuit 35.
It is CT processed, decoded into the original video signal, and given to the terminal a of the switch 36. On the other hand, the output of the variable length decoding circuit 33 is also given to the header signal extraction circuit 37. The header signal extraction circuit 37 searches the header indicating whether the input data is the intra-frame compressed data or the inter-frame compressed data, and outputs it to the switch 36. The switch 36 selects the terminal a and outputs the decoded data from the inverse DCT circuit 35 when the header indicating the intra-frame compressed data is given.

The inter-frame compressed data is obtained by adding the output of the inverse DCT circuit 35 and the output of the previous frame from the predictive decoding circuit 39 by the adder 38. That is, the output of the variable length decoding circuit 33 is the motion vector extraction circuit 40.
To obtain the motion vector. This motion vector is given to the predictive decoding circuit 39. Meanwhile, switch 36
The decoded output from is delayed by one frame period by the frame memory 41. The predictive decoding circuit 39 motion-compensates the decoded data of the previous frame from the frame memory 41 with the motion vector, and outputs it to the adder 38. The adder 38 adds the output of the predictive decoding circuit 39 and the output of the inverse DCT circuit 35 to decode the data compressed between frames and switch the data.
Output to terminal b of 36. When the inter-frame compressed data is input, the switch 36 selects the terminal b by the header,
The decoded data from the adder 38 is output. in this way,
The compression and decompression operations are performed without delay in both the intraframe compression mode and the interframe compression mode.

However, the intra-frame compressed frame I
2 and the inter-frame compressed frame P have different code amounts,
When the data stream shown in No. 1 is recorded on the recording medium, it is not always possible to reproduce one frame by the reproduction data in the above-described triple speed reproduction. Further, since the inter-frame compressed frame P cannot be decoded by a single frame, it becomes unreproducible when a frame that is not decoded occurs such as triple speed reproduction.

In order to solve this problem, the applicant of the present application has proposed a method for arranging important data in a concentrated manner in Japanese Patent Application No. 2-117455 filed earlier. FIG. 23 is an explanatory diagram for explaining this method.
FIG. 23 (a) shows trace patterns at 3 × speed reproduction and 9 × speed reproduction, FIG. 23 (b) shows a recording state on the tape at 3 × speed reproduction, and FIG. 23 (c) shows 9 × speed reproduction. The recording state on the tape is shown.

In this proposal, important data is arranged in the shaded area in FIG. 23 (b) when, for example, 3 × speed reproduction is supported. Further, in the case of supporting 9 × speed reproduction, the important data is arranged in the shaded area in FIG. Each shaded area is an area which is reproduced during 3 × speed reproduction and 9 × speed reproduction, respectively.

FIG. 24 is an explanatory diagram showing a general structure of data recorded on one track.

Data is arranged in the X and Y directions and an error correction code is added. On the tape, (X, Y) =
Starting with the data of (0, 0), one row of data in the X direction is recorded, then advances one row in the Y direction, and the data of the next row is recorded. After that, the data in the X and Y directions are sequentially recorded toward the end of the tape. That is, as shown in FIG. 24, at the beginning of the tape, xi pieces in the X direction and y pieces in the Y direction are provided.
i groups of data are recorded as a preamble and are used as a clock pull-in and a margin for reproduced data.
Next, the video data is recorded. The video data has an RS (Reed-Solomon) product code structure, which is a type of error correction code, and is composed of n product code groups. Each product code is composed of a video data group having x × y data, and a sync signal and an ID signal for synchronizing the video data group are added to the head in the x direction. That is, the sync signal and the ID signal are composed of ys = y × n in the Y direction and xs in the X direction. Then, x0 × y0 group data is recorded on the end side of the tape as a postamble which also serves as a margin portion. The video data is high-efficiency coded data.

FIG. 25 is an explanatory diagram for explaining this video data.

The video data is MPEG (Moving Picture).
Compressed by the compression method presented by Experts Group). For videophone / conference use, 64K
b.times.n times the rate of H.264. 261 is presented,
Further, a compression method for a still image is presented by JPEG. MPEG is for quasi-motion pictures, and the transmission rate is 1.2.
It is Mbps and is used for a CD-ROM or the like. MPE
No. G shown in FIG. 1, No2
The frame data is converted into intra frame data I1, inter frame data B2, B3, inter frame data P4, ... As shown in FIG. In this way, the data of each frame is compressed at different compression rates.

The data shown in FIG. 25 (b) is rearranged in order to facilitate decoding. That is, since the interframe B can be decoded by decoding the interframe P, the intraframe I1, the interframes P4, B2, B3, ... , A recording medium or a transmission line.

In normal recording, the data shown in FIG. 25 (c) is sequentially recorded on the recording medium. Figure 25
(D) shows the state of this recording. On the other hand, in order to enable reproduction at a specific multiple speed, the above-described method converts the data array as shown in FIG. For example, in order to enable the 3 × speed reproduction, the data of the intraframe I is transferred to the start portion (I1 (1)) of the first track # 1, the center portion (I1 (2)) of the second track # 2, and The data is divided and recorded in the end portion (I1 (3)) of the third track # 3. Then, the shaded portion in FIG. 23B is reproduced, so that the data of the intra frame I is reproduced.

FIG. 26 is a block diagram showing the configuration of this proposal. In FIG. 26, the same components as those of FIG.

The data order changing circuit 101 receives the input signal A1
, B1 and C1 are exchanged in order to obtain signals A2, B2 and C2.
To the multiprocessing circuit 102. Input signals A1, B1,
Data of intraframe I and interframes P and B are given as C1. These frame data are composed of the luminance signal Y and the color difference signals Cr, Cb, and the multiplexing processing circuit 102 sequentially multiplexes the signals Y, Cr, Cb and outputs them. The output of the variable length coding circuit 16 is given to the address generation circuit 53 and the data rearrangement circuit 100 surrounded by a broken line in addition to the variable length control circuit 18. The data rearrangement circuit 100 is for recording important data (intra frame compressed data in this case) at a predetermined position on the tape shown by the diagonal lines in FIG. That is, the output of the variable length coding circuit 16 is separated into intra frame data and inter frame data, and the inter frame data is stored in the inter frame data memory 52 under the control of the memory control circuit 54. The address generation circuit 53 generates an address indicating the comparison between the output of the variable length coding circuit 16 and the position of the screen, and the adder 51 adds the address data to the intra frame data from the variable length coding circuit 16.
The intra frame data memory 57 is a memory I control circuit 55.
Is controlled to store the output of the adder 51. An address may be added to the interframe data.

Memory control circuit 54 and memory I control circuit 55
Each of them is supplied with encoding processing information from the variable length encoding circuit 16 and controls writing to the inter-frame data memory 52 and the intra-frame data memory 57. On the other hand, the data relocation control circuit 56 controls the data memory 5
At the time of reading from 2, 57, the memory control circuit 54, the memory I control circuit 55, and the MPX 58 are controlled to perform data rearrangement so that the data stream shown in FIG. That is, the track number measurement circuit
103 is provided with a track start signal such as a head switching pulse for instructing head switching, grasps the recording track, and outputs the recording track number to the data rearrangement control circuit 56. For example, in the case of supporting the 3 × speed reproduction, the track number measuring circuit 103 displays the track number 1 indicating that the recording tracks are three kinds of continuous recording tracks.
2 and 3 are sequentially and repeatedly output. Data relocation control circuit 56
Is an MPX based on the output of the track number measuring circuit 103.
Determine the sequence of the intraframe data from the data from 58. For example, to enable 3x speed playback,
When the data indicating the track number 1 is given, the output of the intra frame data memory 57 is arranged so as to be recorded at the start end of the recording track.
Is given, the output of the intra-frame data memory 57 is arranged so as to be recorded at the center and the end of the recording track.

In this way, the MPX 58 is controlled by the data rearrangement control circuit 56 and multiplexes the intra-frame compressed data according to the reproduction speed number and outputs it to the error correction encoder 17. The error correction encoder 17 adds the error correction parity and outputs it to the multiplexing circuit 19. Synchronization / ID creation circuit 20
Generates a synchronization signal and an ID signal and outputs the synchronization signal and the ID signal to the multiplexing circuit 19. The multiplexing circuit 19 outputs the synchronization signal and the ID signal to the MPX58.
It is designed to be added to the output of and output. Multiple circuit
The output of 19 is recorded on a recording medium via a recording head (not shown).

On the other hand, FIG. 27 is a block diagram showing the reproducing side. In FIG. 27, the same components as those of FIG. 22 are designated by the same reference numerals and the description thereof will be omitted.

On the reproducing side, basically the same decoding operation as in FIG. 22 is performed, but since the data is rearranged at the time of recording, a process for restoring the data array is added.
That is, the reproduction output from the recording medium (not shown) is demodulated and error-corrected by the error correction decoder 31, and then applied to the address / data length extraction circuit 61 and the DMPX 62. Since the intra-frame compressed frame data is recorded at a predetermined position on the recording medium in accordance with a predetermined reproduction speed number, the intra-frame compressed frame can be reproduced by performing the reproduction at this speed number.

The address and data length extraction circuit 61 extracts the address and data length of the intra frame data.
The DMPX 62 is controlled based on the address and the data length from the data length extraction circuit 61 to separate the intra-frame compressed data and the inter-frame compressed data from each other and to the variable length decoding circuit respectively.
Output to 64 and 65. The variable length decoding circuits 64 and 65 decode the input data into fixed length data and output them to the intra frame buffer 66 and the inter frame buffer 67, respectively.

On the other hand, the decoded data of the variable length decoding circuits 64 and 65 is also given to the header extraction circuit 63. Header extraction circuit 63
Is also given the output of the address and data length extraction circuit 61, creates an instruction signal for restoring the time series and outputs it to the memory I control circuit 69, the memory control circuit 70 and the intra data rearrangement cancellation circuit 68. To do. The intra-data rearrangement cancellation circuit 68 uses the memory I based on the instruction signal and header information.
It controls the control circuit 69, the memory control circuit 70, and the MPX 71. As a result, the memory I control circuit 69 and the memory control circuit 70 control the writing and reading of the intra frame buffer 66 and the inter frame buffer 67, respectively, so that the intra-frame compressed data and the inter-frame compressed data converted into the fixed length are MPX 71. Output to. The MPX 71 is controlled by the intra-data rearrangement canceling circuit 68, restores the original data time series before rearrangement, and outputs it to the portion 300 surrounded by a broken line.
The operation in the portion surrounded by the broken line 300 is the same as the processing after the inverse quantization processing in FIG. 22, and the switch 36 outputs the decoded output.

FIG. 28 is a block diagram showing a circuit considering error processing in FIG.

A portion 200 'surrounded by a broken line in FIG. 28 is shown in FIG.
The variable length decoding unit 200 and the error processing unit 202 are included. If a decoding error occurs during decoding, the error correction decoder 31 outputs a flag indicating the error generating unit to the variable length decoding unit 200. The decoding error flag control circuit 204 controls the error processing circuit 203 based on the output of the variable length decoding unit 200 to skip the data in which the error is propagated, and causes the decoding unit 300 (broken line portion in FIG. 27) to generate an error. The data of the generation unit is not supplied. In addition,
The error processing circuit 203 may include a circuit that corrects the error by using the data of the previous field or the previous frame at the same time series position as the error generating unit.

As described above, the apparatus shown in FIGS. 26 and 27 obtains a reproduced image by reproducing at least intraframe data during special reproduction. However, there is only one intra frame for every ten or more frames. Furthermore, during special playback, images of multiple frames that differ in time are combined to obtain a single playback image.
There is a problem that the reproduced image during special reproduction does not move smoothly and the image quality is extremely poor. In addition, in fact,
The amount of intra-frame data is relatively large, and as shown by the shaded areas in FIGS. 23 (b) and 23 (c), the intra-frame data is recorded beyond the reproduction area (hatched portion) during special reproduction. Therefore, interframe data cannot be recorded in the reproduction area in order to improve the image quality.

[0050]

As described above, in the above-mentioned conventional high-efficiency coding / decoding apparatus, even if the intraframe data is rearranged in accordance with the reproduction speed number, the temporal difference between the intraframe data is reduced. However, there is a problem that the image quality of the special reproduction image is extremely poor because a single image is formed by using the data of a plurality of frames during the special reproduction.

The present invention has been made in view of the above problems, and provides a high-efficiency coding / decoding apparatus capable of obtaining a high-quality special reproduction image even when high-efficiency coding is adopted. The purpose is to

[0052]

According to a first aspect of the present invention, a high-efficiency coding / decoding apparatus records a compression means for compressing an input video signal at a predetermined compression ratio and an output of the compression means. A high compression unit that compresses the input video signal so that the data rate can be recorded only in a data area that is reproduced during special reproduction of a recording track, and an output of the compression unit and an output of the high compression unit. Arrangement means for rearranging so that the output of the high compression means can be recorded in the data area reproduced at the time of special reproduction on the recording track, and the arrangement means from the data area reproduced at the time of special reproduction of the recording track. A high compression decoding means for decoding the reproduction signal, and one reproduction image by selecting a predetermined portion of the decoded data from the high compression decoding means at the time of special reproduction based on the special reproduction state. In the high-efficiency coding / decoding apparatus according to claim 2 of the present invention, the high-compression means is configured so that the high-compression means processes an input video signal into an intra-frame compression code, a unidirectional prediction code, and both The present invention is characterized in that the high-compression decoding means selectively decodes only the intra-frame compression code and the unidirectional prediction code. In the high-efficiency coding / decoding apparatus according to, the high-compression means encodes an input video signal into an intra-frame compression code, a unidirectional prediction code, and a bidirectional prediction code. All the intra-frame compression codes and the unidirectional prediction codes are decoded, and with respect to the bidirectional prediction codes, only a part of the data is decoded.

[0053]

In the present invention, the high compression means compresses the input video signal to a data rate recordable in the data area reproduced during special reproduction. The arranging means determines the arrangement of the output of the compressing means and the output of the high compressing means so that the output of the high compressing means is recorded in the data area to be reproduced at the time of special reproduction. At the time of special reproduction, the high compression decoding means decodes the reproduction data. In order to create one screen from the number of pieces of decrypted data based on the special reproduction state, the cutting and pasting means,
Based on the special reproduction state, a plurality of parts of the decoded data are rearranged and output, and the decoding rate is reduced to the recording rate.

[0054]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the recording side of a high efficiency coding / decoding apparatus according to the present invention.

The input video signal is supplied to the low compression ratio circuit 81 and the high pressure compression ratio circuit 83 via the spatial filter 82. The spatial filter 82 limits and outputs the data band to achieve a high compression ratio. The low compression ratio circuit 81 compresses the input video signal with a relatively low compression ratio and outputs it to the adder 84, and the high compression ratio circuit 83 compresses the input video signal with a relatively high compression ratio and outputs it to the adder 85. To do. In this embodiment, for example, the high compression ratio circuit 83 has a transmission rate of 1.
Adopts the MPEG1 system of 2 Mbps, low compression ratio circuit 81
For example, a JPEG method using only an intra frame which is a signal having a transmission rate higher than MPEG1 or an MPEG2 method having a transmission rate of 4 or 9 Mbps is adopted.

FIG. 2 shows a low compression ratio circuit 81 and a high compression ratio circuit 83.
5 is an explanatory diagram for explaining the output data amount of FIG. Figure 2
2A shows an input video signal data amount, FIG. 2B shows a high compression ratio processed signal, FIG. 2C shows a low compression ratio processed signal, and FIG. 2D shows a multistage compression ratio. The processed signal is shown. As shown in FIGS. 2A to 2C, the data amount of the high compression ratio processed signal is sufficiently smaller than the data amounts of the input signal and the low compression ratio processed signal. The adder 84 is a low compression ratio circuit 81
A low compression flag is added to the low-compression-ratio processed signal from the switch and is given to the terminal a of the switch 86.
It is given to terminal b of 86.

On the other hand, the track counter 87 is supplied with a recording track signal. The track counter 87 counts the recording track signal to measure the track number and outputs the measurement result to the recording position determination circuit 88. The recording position determination circuit 88 determines a recording position on the track between the output of the low compression ratio circuit 81 and the output of the high compression ratio circuit 83 based on the track number, and outputs a control signal for controlling the switch 86. Output.

FIG. 3 is an explanatory diagram for explaining the recording position on the track by the recording position determining circuit 88. FIG. 3 shows 5
The trace pattern during double speed reproduction is shown. In this embodiment, the output data of the high compression ratio circuit 83 is recorded in the reproduction area (hereinafter referred to as the specific arrangement area) indicated by the diagonal lines in FIG. 3, and the output of the low compression ratio circuit 81 is output outside the specific arrangement area. It is designed to record data. 3A shows an example in which the output of the high compression ratio circuit 83 is recorded in the specific arrangement area of all tracks, and FIG. 3B shows the output of the high compression ratio circuit 83 in the specific arrangement area of every other track. An example is shown. Since the data amount of the high compression ratio processed signal is sufficiently compressed, the high compression ratio processed signal of the entire screen can be recorded in the characteristic arrangement area. Further, in the present embodiment, when the recording rate of the video data is NMbps, the recording rate of the specific arrangement area is set to nMbps or less, and the transmission rate of the low compression ratio processed signal is set to (N−n) Mbps or less. ing.

The switch 86 is controlled by the recording position determining circuit 88 to selectively output the low compression ratio processed signal or the high compression ratio processed signal to the error correction encoder 17. The error correction encoder 17 adds parity for error correction and outputs it to the adder 19. The synchronization / ID creation circuit 20 creates a synchronization signal and an ID signal and gives them to the adder 19. The adder 19 adds the synchronization signal and the ID signal to the output of the error correction encoder 17 and outputs them to the recording modulation circuit 89. .. The recording modulation circuit 89 records and codes the output of the adder 19 according to the characteristics of a recording medium (not shown) and outputs it to a recording unit (not shown).

FIG. 4 is a block diagram showing an embodiment on the reproducing side.

A reproduction signal from a recording medium (not shown) is given to the terminal a of the switch 90 and the flag judgment circuit 91. The terminal a of the switch 90 is connected to the low compression decoding circuit 92, and the terminal b is connected to the high compression decoding circuit 93 and the frame number detection circuit 94. The flag determination circuit 91 detects a low compression flag or a high compression flag from the reproduction signal, determines whether the input reproduction signal is low compression ratio processed or high compression ratio processed, and outputs the determination result to the mode control circuit. Output to 92. The mode control circuit 92 is also supplied with a mode signal indicating the reproduction mode, and switches 90 based on the mode signal and the determination result.
Is controlled. That is, the mode control circuit 95 causes the switch 90 to select the terminal a when the normal reproduction mode is designated, and causes the switch 90 to select the terminal b when the special reproduction mode is designated.

The low compression decoding circuit 92 decodes the reproduction data subjected to the low compression ratio processing, that is, the data recorded outside the specific arrangement area, and outputs the decoded output to the terminal a of the switch 96. The switch 96 is also controlled by the mode control circuit 95 in conjunction with the switch 90.

On the other hand, the frame number detection circuit 94 is a switch.
The track number of the reproduction signal from 90 is detected and output to the high compression decoding circuit 93. The high compression ratio processed signal is composed of intra frame data I or inter frame data B and P depending on the track, and the high compression decoding circuit 93 is subjected to high compression ratio processing based on the detection result of the frame number detection circuit 94. The reproduced data is decoded and given to the cutting and pasting circuit 97. Note that these decoding circuits 92 and 93 have the same configuration as that described in the reference document "Development of High-Resolution Compression Encoding Decoder Chip for Broadcasting" (Video Information (1) 1991/6). Further, the track counter 99 counts the input track signal and cuts out the track number and outputs it to the pasting circuit 97. The cut-and-paste circuit 97 has a memory, the writing and reading of the decoded output of the high compression decoding circuit 93 are controlled based on the track number and the frame number, and a plurality of continuous images are combined to form one image. Is generated and output to the interpolation filter 98. That is, when the double speed reproduction is performed, the transmission rate increases according to the double speed number. For example, when 5 × speed reproduction is performed, the decoded output of 5 images can be obtained in one trace period of the head. For this reason, in the present embodiment, a predetermined portion of the decoded output is selected according to the double speed number so that one image is composed of a plurality of screens. Interpolation filter 98
Interpolates the data thinned by the band limitation at the time of recording and outputs it to the terminal b of the switch 96.

Next, the operation of the embodiment thus constructed will be described with reference to the explanatory view of FIG. Figure 5 (a)
Indicates the data used for the reproduction screen configuration among the reproduction outputs from the tracks of track numbers 1 to 5 during quintuple speed reproduction, and FIGS. 5B and 5C show the configuration of the reproduction screen.

On the recording side, the input video signal is supplied to the low compression ratio circuit 81 and the high compression ratio circuit 83 after being band-limited by the spatial filter 82. The low compression ratio circuit 81 compresses the input video signal by MPEG2, for example. The low compression ratio processed signal is added with a low compression flag in the adder 84 and is given to the terminal a of the switch 86. The high compression ratio circuit 83 inputs the input video signal to, for example, MPEG1.
Compress by. In MPEG1, a series of frames is converted into intra frame data I and inter frame data B, B, P, B, B, P, B, B, P, .... The high compression ratio processed signal is added with a high compression flag in the adder 85 and is given to the terminal b of the switch 86.

On the other hand, the track counter 87 counts the recording track signal and outputs the track number to the recording position determining circuit.
Output to 88. The recording position determination circuit 88 controls the switch 86 based on the track number. For example, the recording position determination circuit 88 first selects the terminal b at the timing corresponding to the specific arrangement area in the trace start track T1 during double speed reproduction in FIG.
The terminal a is selected at another timing to output the low compression ratio processed signal. In the next track T2, first, the terminal a
After selecting, the terminal b is selected at the timing corresponding to the specific arrangement area and the high compression ratio processed signal is output.
Thereafter, the switch 86 is similarly controlled to sequentially output the intra frame data I, the inter frame data B, B, P, ... At the timing corresponding to the specific arrangement area.

The output of the switch 86 is the error correction encoder 17
, The parity for error correction is added, and the adder 19
At, the synchronizing signal and the ID signal are added and supplied to the recording modulation circuit 89. The recording modulation circuit 89 modulates the output of the adder 19 so as to match the recording medium, and outputs it.

On the other hand, on the reproducing side, normal reproduction is performed. In this case, the mode control circuit 95 switches based on the mode signal and the determination result of the flag determination circuit 91.
Causes 90 and 96 to select terminal a. A reproduction signal from a recording medium (not shown) is supplied to the low compression decoding circuit 92 via the switch 90. The low compression decoding circuit 92 decodes a reproduction signal of MPEG2 data recorded in a portion other than the characteristic arrangement area of each recording track. The decoded output is output via the switch 96 and displayed on a display unit (not shown).

Here, it is assumed that special reproduction is performed.
In this case, the mode control circuit 95 causes the switches 90 and 96 to select the terminal b based on the mode signal and the determination result of the flag determination circuit 91. The high compression decoding circuit 93 performs decoding based on the detection result of the frame number detection circuit 94. That is, the intra-frame data I and the inter-frame data B, B, P, ... Are sequentially input to the high compression decoding circuit 93. The high compression decoding circuit 93 decodes the intra frame data I and then the data I Is used to decode the interframe data P, and the data I and P are used to decode the interframe data B and output to the cut and paste circuit 97.

Assuming that 5 × speed reproduction is performed, the image data of 5 sheets reproduced by one head scan is as shown in FIG.
As shown in (a), the frame is an intra frame I1 and inter frames B2, B3, P4, and B5. That is, the transmission rate of the decoded data from the high compression decoding circuit 93 is MPEG.
It is 5 times the transmission rate of 1. The cut-and-paste circuit 97 reduces the transmission rate, and in order to smooth an image using a series of five pieces of image data, the image data for one sheet is processed by intra-frame data I1, inter-frame data B2, B3. , P4, B5.
That is, the cut-and-paste circuit 97 is controlled to write and read the decoded data, and, as shown in FIG. 5A, using a part of each data indicated by diagonal lines, as shown in FIG. One image data is combined. Also, cut and paste circuit
As for 97, if the smoothness of movement is not taken into consideration, as shown in FIG. 5C, the data can be arranged so that a child screen is formed using each frame data. The output of the cut and paste circuit 97 is given to the interpolation filter 98 and interpolated,
It is output via the terminal b of the switch 96.

As described above, in the present embodiment, the high compression ratio processed signal is recorded in the specific arrangement area during special reproduction, and the decoding rate matches the recording rate during special reproduction. Using a series of image data of 1
I am trying to compose one image. Since the reproduced image is formed using continuous frame data, the reproduced image is smooth and the image quality can be improved.

FIG. 6 is a block diagram showing another embodiment of the present invention. This embodiment differs from the embodiment of FIG. 4 only in the portion surrounded by the broken line in FIG. 4, and only this portion is shown in FIG. 6, the same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

In the embodiment shown in FIG. 4, all the reproduced data are decoded. On the other hand, in this embodiment,
Only the intra-frame data I and the inter-frame data P are decoded to shorten the processing time. A reproduction signal input via the terminal b of the switch 90 (see FIG. 4) is transferred via the switch 111 to the data buffer 11
3 and the picture header extraction circuit 112
Is also entered. The picture header extraction circuit 112 discriminates whether the reproduction signal is the intra frame data I, the inter frame P or the inter frame B, and controls the on / off of the switch 111 according to the discrimination result. .. The data buffer 113 stores the data input via the switch 111 and outputs it to the high compression decoding circuit 93.

Next, the operation of the embodiment thus constructed will be described with reference to the explanatory views of FIGS. 7 and 8.

At the time of special reproduction, the reproduction signal is transmitted through the switch 90 to the switch 111 and the picture header extraction circuit 112.
Given to. Now, it is assumed that the reproduction screen is composed of the data indicated by the diagonal lines in FIG. Picture header extraction circuit 11
In the first scan of the head, the switch 2 first turns on the switch 111 for passing the intra frame data I1, and then turns on the switch 111 for passing the inter frame data P4. Data buffer
113 stores the input data and gives it to the high compression decoding circuit 93. The high compression decoding circuit 93 uses the intra frame data I
After decoding 1, the interframe data P4 is decoded using this data I1. The cut-and-paste circuit 97 outputs one image data by using the output of the high compression decoding circuit 93.

In the second scan, the picture header extraction circuit 112 controls the switch 111 to supply the inter frame data P7 and the inter frame data P10 to the data buffer 113 as shown in FIG. The decoding circuit 93 highly compresses and decodes these data, and the cutting and pasting circuit 97
Outputs one image data using the decoded data.

Further, the structure of the reproduction screen can be made as shown by the diagonal lines in FIG. 8, for example. FIG. 8 shows that in the first scan, one intra-frame data I1 and the inter-frame data P4 are used to compose one reproduction screen.
In the scan, one playback screen is constructed using the inter-frame data P7 and the inter-frame data P10, and in the third scan, one playback screen is constructed using only the inter-frame data P13. ing. In this embodiment, the data I,
By using the reproduced image data for one sheet obtained from P, the decoding rate is matched with the recording rate.

As described above, in the present embodiment, only the intra frame data I and the inter frame data P are decoded to obtain the reproduction screen, and the processing rate is reduced as compared with the embodiment of FIG. ..

FIG. 9 is a block diagram showing another embodiment of the present invention. In FIG. 9, the same components as those of FIG. 6 are designated by the same reference numerals and the description thereof will be omitted.

In the embodiment of FIG. 6, since the frame data to be decoded is not the data of consecutive frames,
The movement and the like of the reproduced image are not always smooth. Therefore, in the present embodiment, by decoding a part of the inter frame data B in addition to the intra frame data I and the inter frame data P, the reproduced image is smoothed and the processing rate is reduced. ..

That is, the reproduction signal from the terminal b of the switch 90 is input to the data buffer 113 via the switch 111 and also to the picture block extracting circuit 121. The picture block extraction circuit 121 discriminates whether the reproduced signal is the intra-frame data I or the inter-frame data P, B and determines the discrimination result by the control circuit 122.
Output to. The control circuit 122 is a track counter 99 (see FIG.
Track number from
The control signal is output to 111, the data buffer 113, the high compression decoding circuit 93, the B decoding image memory 123, and the cut and paste circuit 97.

Next, the operation of the embodiment thus constructed will be described with reference to FIG.

The control circuit 122 switches the switch 111 based on the outputs of the picture block extraction circuit 121 and the track counter 99. In the first scan, in addition to the reproduced intra frame data I1 and inter frame data P4, inter frame data B2, B3,
Part of B5 passes through the switch 111 to the data buffer 113
Given to. Similarly, in the second and third scans,
In addition to the interframe data P7 and P13, the interframe data B6, B8, B9, B11, B12, B14, B
A part of 15 is supplied to the data buffer 113 via the switch 111.

The high compression decoding circuit 93 decodes the reproduction signal from the data buffer 113 according to the track number. That is, the high compression decoding circuit 93 firstly receives the intra frame data I.
After decoding 1, the interframe data P4 is decoded using the data I1, and these decoded data are stored in the I / P decoded image memory 124. Furthermore, the high compression decoding circuit 93
Uses these data I1 and P4 to decode a part of the interframe data B2, B3 and B5, and B
It is stored in the decoded image memory 123. The cut and paste circuit 97 is
In the first scan, the data I1 of the portion corresponding to the uppermost portion of the screen and the data P4 of the portion corresponding to the second lowermost portion of the screen are read from the I / P decoded image memory 124, and read from the B decoded image memory 123. The data B2, B3, B5 corresponding to the shaded areas in the first scan of FIG.
The image data of one sheet is constructed and output.

In the second and third scans, the high compression decoding circuit 93 decodes the interframe data P7 and P13 and stores them in the I / P decoded image memory 124, and the interframe data B6, B8, B9 and B11. , B12, B14,
A part of B15 is decoded and stored in the B decoded image memory 123. The cut-and-paste circuit 97 forms one screen by using a part of the decoded data of the interframe data B6, P7, B8, B9, P10 in the second scan, and the interframe data B11, B12, P13 in the third scan. , B14, B
One screen is constructed using a part of the decoded data of 15.

As described above, in this embodiment, in addition to the intra-frame data I and the inter-frame data P, the inter-frame data B is decoded, and one reproduction screen is displayed using the decoded data of each continuous frame. Since it has been obtained, it is possible to obtain a smoother image than the embodiment of FIG. Further, with respect to the interframe data B, it is not necessary to decode all the data, and only the data of the portion used for screen reproduction is decoded, so that the processing rate can be reduced.

FIG. 11 is a block diagram showing a modification of the embodiment shown in FIG. 11, the same components as those in FIG. 9 are designated by the same reference numerals and the description thereof will be omitted.

The reproduced signal from the terminal b of the switch 90 is supplied to the high compression decoding circuit 93 and the header extraction circuit 131. The header extraction circuit 131 extracts the header from the reproduction signal, identifies whether the reproduction signal is the intra frame I or the inter frames P and B, and outputs the identification result to the corresponding block calculation circuit 132. The corresponding block calculation circuit 132 is also given the information of the track number, and calculates the data of the block to be decoded in the reproduction data and outputs it to the decoding control circuit 133. The decoding control circuit 133 is the block calculation circuit 13
On / off control of the decoding operation of the high compression decoding circuit 134 is performed based on the output of 2.

With such a configuration, the corresponding block calculation circuit 132 calculates the block to be decoded, for example, the shaded area in FIG. 10, based on the output of the header extraction circuit 131 and the track number information. The reproduction signal is input to the high compression decoding circuit 134 in time series, and the decoding control circuit 133 controls the on / off of the decoding operation by the output of the corresponding block calculation circuit 132. As a result, the high compression decoding circuit 134 can decode only the data corresponding to the shaded area in FIG. Other operations are the same as in FIG.

FIG. 12 is a block diagram showing the recording side of another embodiment of the present invention. 12, the same components as those of FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. This embodiment is applied to a multi-stage coding system.

The multistage compression method first compresses input data with a high compression ratio and then adds additional data to the compressed data to improve the image quality, and is also called hierarchical coding.
In other words, the first high compression ratio process can obtain only a relatively rough image, but it gradually improves the image quality by performing a low compression ratio process to obtain an image with high definition, and is used in the field of communication. ing.

The input video signal is input to the high compression ratio circuit 141. The high compression ratio circuit 141 adopts, for example, MPEG1 to perform high compression ratio processing on the input video signal and outputs a high compression ratio processed signal to the adder 142. The adder 142 adds a high compression flag to the output of the high compression ratio circuit 141 and outputs it to the low compression ratio circuit 144 and the delay buffer 143. Low compression ratio circuit 144 is an adder
By processing the output of 142 with a low compression ratio, the detailed data of the input video signal is added and the high quality video data is added.
Output to 145. The adder 145 adds a low compression flag to the output of the low compression ratio circuit 144 and supplies it to the terminal a of the switch 86. The delay buffer 143 delays the output of the adder 142 and supplies it to the terminal b of the switch 86.

FIG. 13 is a block diagram showing an embodiment on the reproducing side in the multistage encoding system. In FIG. 13, the same components as those in FIG.

The reproduction signal is given to the high compression decoding circuit 147. The high-compression decoding circuit 147 is controlled by the mode control circuit 95 to decode the high-compression-ratio-processed signal of the reproduced signal and apply it to the low-compression decoding circuit 148 and the cut-and-paste circuit 97. The low compression decoding circuit 148 is controlled by the mode control circuit 95 to decode the low compression ratio processed signal of the output of the high compression decoding circuit 147 and output it to the terminal a of the switch 96.

In the embodiment constructed as described above,
On the recording side, the high compression ratio circuit 141 and the low compression ratio circuit 144 subject the input video signal to multistage compression ratio processing. Figure 2
(D) shows a multi-stage compression ratio processed signal, and the multi-stage compression ratio processed signal is composed of a high compression ratio processed signal and a low compression ratio processed signal. On the other hand, the high compression ratio processed signal is added with a high compression flag in the adder 142 and is supplied to the terminal b of the switch 86 via the delay buffer 143. Switch 86
Controlled by the recording position determination circuit 88, the terminal a is selected to output the multistage compression ratio processed signal at the timing corresponding to the portion other than the specific arrangement area in the special reproduction mode, and the terminal b is output at the timing corresponding to the specific arrangement area. To output a high compression ratio processed signal. Other actions on the recording side are shown in Fig. 1.
It is similar to the embodiment of.

On the other hand, on the reproducing side, when the special reproduction mode is designated, the reproduction data from the specific arrangement area is reproduced by the high compression decoding circuit 147 and given to the cut and paste circuit 97. The cut-and-paste circuit 97 creates and outputs one image data by using a plurality of continuous frame data reproduced from the specific arrangement area.

Further, in the normal reproduction mode, the output of the high compression ratio decoding circuit 147 is supplied to the low compression decoding circuit 148 and the low compression ratio processed signal is also decoded. In this way, all the data recorded on the track is decoded and the decoded data is supplied to the terminal a of the switch 96. Other functions are similar to those of the embodiment shown in FIG.

As described above, also in this embodiment, the same effects as those of the embodiments of FIGS. 1 and 4 can be obtained.

The present invention is not limited to the above-mentioned embodiment, and for example, the high compression ratio processing and the low compression ratio processing may not be MPEG1, 2, etc., and the present invention is not limited to the compression method. ..

[0100]

As described above, according to the present invention, it is possible to obtain a high quality special reproduction image even when high efficiency coding is adopted.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a recording side of a high efficiency encoding / decoding device according to the present invention.

FIG. 2 is an explanatory diagram for explaining a compression ratio in the embodiment.

FIG. 3 is an explanatory diagram for explaining a reproduction area during special reproduction.

FIG. 4 is a block diagram showing an embodiment of the reproducing side of the high efficiency encoding / decoding device according to the present invention.

5 is an explanatory diagram for explaining the operation of the embodiment of FIGS. 1 and 4. FIG.

FIG. 6 is a block diagram showing another embodiment of the present invention.

7 is an explanatory diagram for explaining the operation of the embodiment of FIG.

8 is an explanatory diagram for explaining the operation of the embodiment of FIG.

FIG. 9 is a block diagram showing another embodiment of the present invention.

FIG. 10 is an explanatory diagram for explaining the operation of the embodiment of FIG.

FIG. 11 is a block diagram showing a modification of the embodiment of FIG.

FIG. 12 is a block diagram showing the recording side of another embodiment of the present invention.

13 is a block diagram showing the reproducing side of the embodiment of FIG.

FIG. 14 is an explanatory diagram for explaining the comparison between the position on the screen and the position on the recording track of the recording medium in the conventional example.

FIG. 15 is an explanatory diagram showing a relationship between a trace pattern and a reproduction envelope during 3 × speed reproduction.

FIG. 16 is an explanatory diagram showing the structure of a recording / reproducing head.

FIG. 17 is an explanatory diagram illustrating a configuration of a reproduction screen in a conventional example.

FIG. 18: H. 261 is an explanatory view for explaining a compression method of the H.261 recommendation.

FIG. 19 is a block diagram showing the recording side of a conventional high-efficiency coding / decoding apparatus that employs predictive coding.

FIG. 20 is an explanatory diagram illustrating a macro block.

21 is an explanatory diagram showing a data stream of a recording signal in the apparatus of FIG.

FIG. 22 is a block diagram showing a decoding side (reproduction side) of a conventional high efficiency encoding / decoding device.

FIG. 23 is an explanatory diagram for explaining a conventional example in which important data is concentrated in a reproduction area during special reproduction.

FIG. 24 is an explanatory diagram showing a general configuration of data recorded on one track.

FIG. 25 is an explanatory diagram for explaining a data array in the conventional example of FIG. 23.

FIG. 26 is a block diagram showing a recording side of a conventional high-efficiency coding / decoding apparatus for realizing FIG. 23.

FIG. 27 is a block diagram showing a reproducing side of a conventional high-efficiency coding / decoding apparatus for realizing FIG. 23.

FIG. 28 is a block diagram showing a circuit considering error processing in FIG. 27.

[Explanation of symbols]

81 ... Low compression ratio circuit, 83 ... High compression ratio circuit, 84, 85 ... Adder, 86 ... Switch, 88 ... Recording position determining circuit

Claims (3)

[Claims] 1. A compression means for compressing an input video signal at a predetermined compression ratio, and a data rate capable of being recorded only in a data area reproduced during special reproduction of a recording track on which the output of the compression means is recorded. A high compression means for compressing the input video signal so that the output of the compression means and the output of the high compression means are rearranged so that the output of the high compression means is reproduced during special reproduction on the recording track. And a high compression decoding means for decoding a reproduction signal from the data area reproduced at the time of special reproduction of the recording track, and a high compression decoding means for special reproduction at the time of special reproduction. A high efficiency code, comprising: a cut-and-paste means for selecting a predetermined portion of a plurality of pieces of decoded data on the basis of the special reproduction state and forming one reproduced image. Decoding apparatus. 2. The high compression means encodes an input video signal into an intraframe compression code, a unidirectional prediction code, and a bidirectional prediction code, and the high compression decoding means includes an intraframe compression code and a unidirectional prediction code. The high-efficiency coding / decoding apparatus according to claim 1, wherein only the directional prediction code is selectively decoded. 3. The high compression means encodes an input video signal into an intraframe compression code, a unidirectional prediction code and a bidirectional prediction code, and the high compression decoding means includes all intraframe compression codes. 2. The high-efficiency coding / decoding apparatus according to claim 1, wherein the unidirectional predictive code is decoded and only a part of the data of the bidirectional predictive code is decoded.