JPH06245201A - High efficiency coding/decoding system - Google Patents

Abstract

PURPOSE:To improve the transmission frequency of data, to facilitate the format conversion of data, and to attain decoding even when the data are reproduced discontinuously. CONSTITUTION:A large block consists of four small blocks 50, a large block start code 110 and a large block header 52. Each of the small blocks 50 has a variable length data 57, small block header 103 and an intra-data length 56, The data are sent through a branch 1, an MB ESCAPE 102 are sent through a branch 2, an MBSTUFF 59 are sent through a branch 3, and an SKIP 101 are sent through a branch 4. Even when the data are discontinuously reproduced, the data are decoded by the branches.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding / decoding system suitable for recording / reproducing on / from a television broadcast and a recording medium.

[0002]

2. Description of the Related Art In recent years, various standardization proposals have been proposed for high efficiency encoding for compressing image data.
The high-efficiency coding technique is for coding image data with a smaller bit rate in order to improve the efficiency of digital transmission and recording. For example, CCITT (In
ternational Telegraph and Telephone Consultative C
ommittee) is a standardization recommendation H.264 for video conferencing / video telephony. 261 is proposed. In this recommendation, encoding is performed using a frame I that is intra-frame compressed (Intra-frame) and a frame P that is inter-frame compressed (Inter-frame or Predictive frame).

FIG. 15 is an explanatory diagram for explaining the compression method of this recommendation.

Frame I is DCT (discrete cosine transform)
The image data of one frame is encoded by the processing. The frame P is the image data encoded by the predictive encoding using the frame I or another frame P. Furthermore, the bit rate is further reduced by performing variable length coding on these coded data. Since the frame I is encoded only by the information in the frame, it can be decoded only by the single encoded data. On the other hand, the frame P is encoded by utilizing the correlation with other image data, and cannot be decoded only by the single encoded data.

FIG. 16 is a block diagram showing the recording side of a recording / reproducing apparatus adopting such predictive coding.

The luminance signal Y and the color difference signals Cr and Cb are given to the multiplex processing circuit 11 and multiplexed in block units of 8 pixels × 8 horizontal scanning lines. The sampling rate of the color difference signals Cr and Cb in the horizontal direction is 1/2 of that of the luminance signal Y.
Therefore, in the period in which two 8 × 8 luminance blocks are sampled, one 8 × 8 block is sampled for the color difference signals Cr and Cb. As shown in FIG. 17, the multi-processing circuit 11 configures a macro block (MB) with four blocks of two luminance blocks Y and one color difference block Cr, Cb. Two luminance blocks Y
And each of the color difference blocks Cr and Cb represent the same position on the screen. Further, a plurality of macroblocks constitutes a GOB (group of block), and a plurality of GOBs constitutes one frame. The output of the multi-processing circuit 11 is given to the DCT circuit 13 via the subtracter 12.

When performing the intra-frame compression, the switch 14 is off and the output of the multiplex processing circuit 11 is directly input to the DCT circuit 13 as described later. DCT circuit 13
A signal in which one block is composed of 8 × 8 pixels is input to the DCT circuit 13, and the DCT circuit 13 converts the input signal into frequency components by 8 × 8 two-dimensional DCT (discrete cosine transform) processing. This makes it possible to reduce spatial correlation components.
That is, the output of the DCT circuit 13 is given to the quantization circuit 15,
The quantization circuit 15 reduces the redundancy of the signal of one block by requantizing the DCT output with a predetermined quantization coefficient. The multiplexing processing circuit 1 that operates in block units
1, block pulses are supplied to the DCT circuit 13, the quantization circuit 15, and the like.

The quantized data from the quantization circuit 15 is given to the variable length coding circuit 16 and, for example, Huffman coding is performed based on the result calculated from the statistical code amount of the quantized output. As a result, short bits are assigned to data with a high appearance probability, long bits are assigned to data with a low appearance probability,
The amount of transmission is further reduced. The output of the variable-length coding circuit 16 is given to the error correction encoder 17, and the error correction encoder 17
Outputs to the multiplexing circuit 19 with the error correction parity added.

The output of the variable length coding circuit 16 is also given to the coding control circuit 18. The data amount of the output data greatly changes depending on the input image. Therefore, the encoding control circuit
Reference numeral 18 monitors the output data amount from the variable length coding circuit 16 and controls the quantization coefficient of the quantization circuit 15 to adjust the output data amount. The encoding control circuit 18 may control the variable length encoding circuit 16 to limit the amount of output data.

On the other hand, the synchronization / ID generation circuit 20 indicates the frame synchronization (sync) signal, the contents of data, and I indicating the additional information.
The D signal is created and output to the multiplexing circuit 19. The multiplexing circuit 19 composes one sync block of data with the sync signal, the ID signal, the compressed signal data, and the parity, and outputs the data to a recording coding circuit (not shown). The recording / coding circuit records and codes the output of the multiplexing circuit 19 according to the characteristics of the recording medium, and then records it on a recording medium (not shown) via a recording amplifier (not shown).

On the other hand, when the switch 14 is on,
The current frame signal from the multiplex processing circuit 11 is subtracted from the motion compensated previous frame data, which will be described later, by the subtracter 12, and the result is given to the DCT circuit 13. That is, in this case, interframe coding is performed in which the difference data is coded by utilizing the redundancy of images between frames. In inter-frame coding, if the difference between the previous frame and the current frame is simply obtained, the difference becomes large when the image has a motion. Therefore, the position of the previous frame corresponding to the predetermined position of the current frame is calculated to detect the motion vector, and the difference is calculated at the pixel position corresponding to this motion vector to perform motion compensation and reduce the difference value. There is.

That is, the output of the quantization circuit 15 is also given to the inverse quantization circuit 21. The quantized output is inversely quantized by the inverse quantization circuit 15, and further inverse DC by the inverse DCT circuit 22.
T-processed and restored to the original video signal. In the DCT processing, requantization, inverse quantization, and inverse DCT processing, the original information cannot be completely reproduced, and some information is lost. In this case, since the output of the subtractor 12 is difference information, the output of the inverse DCT circuit 22 is also difference information. Inverse DCT
The output of the circuit 22 is given to the adder 23. The output of the adder 23 is fed back via the variable delay circuit 24 and the motion compensation circuit 25 which delays the signal for about 1 frame period, and the adder 23 adds the difference data to the data of the previous frame and the data of the current frame. Is reproduced and output to the variable delay circuit 24.

The data of the previous frame from the variable delay circuit 24 and the data of the current frame from the multiplex processing circuit 11 are given to the motion detection circuit 26 to detect the motion vector. The motion detection circuit 26 obtains a motion vector by, for example, full search type motion detection by matching calculation. In full search type motion detection, the current frame is divided into predetermined blocks, and a search range of, for example, horizontal 15 pixels × vertical 8 pixels is set in each block. For each block, matching calculation is performed in the corresponding search range of the previous frame to calculate the approximation between patterns. Then, the block of the previous frame that gives the minimum distortion in the search range is calculated, and the vector obtained by the block of the current frame is detected as the motion vector. The motion detection circuit 26 outputs the calculated motion vector to the motion correction circuit 25.

The motion correction circuit 25 extracts the data of the corresponding block from the variable delay circuit 24, corrects it in accordance with the motion vector, outputs it to the subtracter 12 via the switch 14, and after time adjustment. Output to the adder 23. Thus
The motion-compensated previous frame data is supplied from the motion compensation circuit 25 to the subtracter 12 via the switch 14, and when the switch 14 is on, the inter-frame compression mode is set. It is in compression mode.

The switch 14 is turned on and off based on the motion determination signal. That is, the motion detection circuit 26 creates a motion determination signal depending on whether or not the magnitude of the motion vector exceeds a predetermined threshold value and outputs it to the logic circuit 27. The logic circuit 27 controls on / off of the switch 14 by a logic judgment using the motion judgment signal and the refresh cycle signal. The refresh cycle signal is a signal indicating the intra-frame compressed frame I in FIG. When the refresh cycle signal indicates that the frame I is input, the logic circuit 27 turns off the switch 14 regardless of the motion determination signal. When the motion determination signal indicates that the motion is relatively fast and the minimum distortion due to the matching calculation exceeds the threshold value, the logic circuit 27 turns off the switch 14 even if the frame P is input, and the block unit is selected. In-frame compression coding is performed with. Table 1 below shows ON / OFF control of the switch 14 by the logic circuit 27.

[0016]

[Table 1] FIG. 18 is an explanatory diagram showing a data stream of a recording signal output from the multiplexing circuit 19.

As shown in FIG. 18, the first input image signal
And the sixth frame is an intra-frame compressed frame I1, respectively.
I6, and the second to fifth frames are converted to interframe compressed frames P1 to P5. The ratio of the data amounts of the frame I and the frame P is (3 to 10): 1. Although the data amount of frame I is relatively large, the data amount of frame P is extremely reduced. Note that the data subjected to the inter-frame compression processing cannot be decoded unless other frame data is decoded.

FIG. 19 shows the decoding side (playback side) of the recording / playback apparatus.
It is a block diagram showing.

The compressed code data recorded on the recording medium is reproduced by a reproducing head (not shown) and given to the error correction decoder 31. The error correction decoder 31 corrects errors that occur during transmission and recording. The reproduced data from the error correction decoder 31 is given to the variable length data decoding circuit 33 via the code buffer memory circuit 32 and decoded into fixed length data. The code buffer memory circuit 32 may be omitted.

The output of the variable length decoding circuit 33 is an inverse quantization circuit.
Inverse quantization is performed in 34, and inverse DC is performed in the inverse DCT circuit 35.
T processing, decoding to the original video signal, terminal a of the switch 36
Give to. On the other hand, the output of the variable length decoding circuit 33 is also given to the header signal extraction circuit 37. The header signal extraction circuit 37 retrieves a header indicating whether the input data is the intra-frame compressed data or the inter-frame compressed data and outputs it to the switch 36. The switch 36 selects the terminal a and outputs the decoded data from the inverse DCT circuit 35 when the header indicating the in-frame compressed data is given.

The inter-frame compressed data is obtained by adding the output of the inverse DCT circuit 35 and the output of the previous frame from the predictive decoding circuit 39 by the adder 38. That is, the output of the variable length decoding circuit 33 is the motion vector extraction circuit 40.
To obtain the motion vector. This motion vector is given to the predictive decoding circuit 39. On the other hand, the decoded output from the switch 36 is delayed by the frame memory 41 for one frame period. The predictive decoding circuit 39 motion-compensates the decoded data of the previous frame from the frame memory 41 with the motion vector and outputs the motion-compensated data to the adder 38. The adder 38 adds the output of the predictive decoding circuit 39 and the output of the inverse DCT circuit 35 to decode the data compressed between frames and outputs the decoded data to the terminal b of the switch 36. When the inter-frame compressed data is input, the switch 36 selects the terminal b by the header and outputs the decoded data from the adder 38. In this way, the compression and decompression operations are performed without delay in both the intra-frame compression mode and the inter-frame compression mode.

By the way, various methods have been studied for recording such high efficiency coded digital image data in a magnetic recording and reproducing apparatus (VCR). FIG. 20 is an explanatory diagram for explaining a recording track created on a recording medium by this VCR.

In FIG. 20, A1, A2, ... Show recording tracks by the positive azimuth head, and B1, B2.
, ... indicate recording tracks by the minus azimuth head. In this case, no problem occurs during normal reproduction. However, for example, when the 3 × speed reproduction is performed, the trace by each head becomes as shown by the arrow in the figure, and only the shaded area in the figure in which the azimuth of the head and the recording track coincide with each other is reproduced. Even in this case, one screen can be reproduced by analog recording in which the position on the screen and the recording position on the recording medium correspond. However, the intra-frame compressed frame I and the inter-frame compressed frame P have different code amounts, and when the data stream shown in FIG. 18 is recorded in the recording medium, one frame is reproduced by the reproduction data at the time of triple speed reproduction. You can't always do it. Furthermore, since the inter-frame compressed frame P cannot be decoded by a single frame, it cannot be reproduced when a frame that is not decoded occurs, such as triple speed reproduction. Moreover, in this case, the data is reproduced discontinuously, so that in a system such as a videophone that continuously decodes the input data string, the data after the interruption cannot be utilized.

Therefore, it is conceivable to add block address information in order to associate each data with the position on the screen. However, unnecessary data other than the image data is added, and the data utilization efficiency is reduced. It is also conceivable that the receiving side adds address information corresponding to the position on the screen and records it on a recording medium, or performs format conversion suitable for storage and rearranges intraframe data, for example. However, the data required to perform these format conversions has not been transmitted. Furthermore, effective decoding using discontinuous reproduction data is not performed.

As a solution to these problems, the present application proposes a "high-efficiency coding / decoding system" in the specification of Japanese Patent Application No. 4-191045 filed previously.

In this proposal, one block is composed of 8 × 8 pixels, and the luminance signal Y and the color difference signals Cr and Cb are 4: 1 :.
Assuming that the sampling is performed at one sampling frequency, four luminance blocks Y and one color difference block Cr and Cb each form a small block. In addition, one macroblock is formed by a set of four small blocks.
Then, the macroblock data length is arranged at the head of the macroblock, and each block Y, C is used as the first system.
The variable length data of r and Cb and the small block data length, the adjustment bit data for rate control as the second system, the modification instruction signal as the third system, and the quantization coefficient It controls the branches of the first to third systems.

By properly selecting these three systems, it is possible to facilitate format conversion on the receiving side, enable decoding using discontinuous data effectively, and further reduce the data utilization efficiency. It suppresses error propagation.

The applicant of the present application filed Japanese Patent Application No.
In the specification of No. 330650, there is also proposed a "variable length code recording / reproducing apparatus" in which a received broadcast signal is format-converted without decoding and recorded in a VTR. Further, in the specification of Japanese Patent Application No. 4-067610, the applicant of the present invention adjusts the data length in consideration of the special reproduction of the VCR and adds a skip code to the "transmission device".
Is also proposing.

By the way, as a compression method for storage media for moving images, MPEG (Moving Picture Experts Gr
oup) 1 is proposed. MPEG is for quasi-moving images, the transmission rate is 1.2 Mbps, and CD-ROM
Etc. FIG. 21 is an explanatory diagram showing the data structure in this MPEG.

As shown in FIG. 21, the data structure of the MPEG system is hierarchical, and a start code is added to each layer except the macroblock layer. The bottom block layer is composed of horizontal 8 pixels × vertical 8 pixels. Since the luminance component and the color difference component have different sampling cycles, the size of one pixel (one block) differs between the luminance component and the color difference component. When the sampling ratio of the luminance component and the color difference component is 4: 1, the luminance 4 block corresponds to each color difference 1 block.
For this reason, headers are added to the four blocks Y0 to Y3, which are two blocks in the horizontal and vertical directions of the luminance component, and the two blocks Cr and Cb of the color difference signals, and the macro block layer (the above-mentioned "high-efficiency coding / decoding") is added. System) corresponding to the small blocks).

Predictive coding is performed in units of this macroblock to form a slice layer composed of one or a plurality of macroblocks (corresponding to the macroblocks of the above-mentioned "high efficiency coding / decoding system"), and N A picture layer of one frame is formed from the slice layer. As the predictive coding of the macroblock, bi-prediction, backward prediction, forward prediction or intra-picture prediction is adopted. Then, the GOP layer is composed of the picture layers of several frames. The GOP layer is composed of both prediction frames (B pictures), forward prediction frames (P pictures) and intra-frame prediction frames (I pictures). For example, when the predetermined frame is an I picture, all the macroblocks are encoded in the picture in the slice layer. Further, in a frame that is a P picture, each macroblock is encoded in the slice layer using the front or the inside of the image. Further, in the B picture, each macroblock is coded using in-picture, forward, backward, or both. A video sequence layer is composed of a plurality of GOPs. The headers of the video sequence layer, the GOP layer, the picture layer, and the slice layer have a start code indicating the start of each layer, and the header of the macroblock layer has a macroblock address.

"High-efficiency coding / decoding system" described above
Considers a system in which the data length includes the macroblock data length. However, in the MPEG system, there is no slice layer data length corresponding to this macroblock data length. Moreover, although the conditional branching in the above-mentioned "high-efficiency coding / decoding system" can be achieved by using the quantized coefficient of the MPEG system as it is, there is no such provision at present. For these reasons, MPEG
In consideration of application to the method, there is a problem in that it is difficult to handle the details in the same manner although they are the same in principle.

[0033]

As described above, the above-mentioned conventional high-efficiency coding / decoding system has a problem that it is difficult to apply it to the MPEG system as it is.

The present invention facilitates format conversion on the receiving side even when macroblock data length information does not exist and branching by a quantized coefficient is not performed.
It is an object of the present invention to provide a high-efficiency coding / decoding system that enables decoding that effectively uses discontinuous data and that suppresses error propagation without reducing the data utilization efficiency.

[0035]

A high-efficiency coding / decoding system according to the present invention includes a small block composed of at least one or more blocks which are coding units of input data, and at least one or more small blocks. A large block configured by the small blocks and arranging a special code indicating the data position at the head of the small blocks, and the small blocks have a first system in which variable length coding is performed for each block which is a coding unit. Variable length data constituted by at least one or more data sets obtained by the above, header information of the variable length data, and a small block data length indicating the data length in the case of intraframe coding. Which of the first to third systems has the adjustment bit data as the second system and the modification instruction signal as the third system. The present invention is characterized in that the data shown in FIG. 1 is transmitted and the input data is variable length coded for each block which is a coding unit and output. Data length measuring means for measuring and outputting the length, header information creating means for creating and outputting header information for the output of the encoding means, and a small block comprising at least one or more of the blocks, The output of the encoding means, the output of the data length measuring means, and the output of the header information creating means are packetized as a first system, predetermined adjusted bit data are arranged as a second system, and modified as a third system. First packet means for packetizing the instruction signal, the first packet means for packetizing by at least one of the first to third systems, and at least one or more front Second packet means for forming a large block by small blocks, and packetizing and outputting the special code indicating that the data is the large block and the output of the header information creating means to the output of the first packet means And is equipped with
Also, in the recording system, at least one small block composed of at least one coding unit block is arranged, and a large block in which a special code indicating the data position is arranged at the beginning thereof is one large block per frame. An input signal having the above is input, and a screen head large block detection unit that detects the large block at the screen head, a head detection unit that detects the head of each large block, and at least the large blocks and the small blocks An address generating means for obtaining an address corresponding to one screen position, and a packetizing means for packetizing the input signal by adding the address of the address generating means and the information of the large block start position to the packet are reproduced. In the system, an extracting means for extracting only the intra-frame compressed data from the reproduction signal, and the frame for each predetermined time unit. Recombining means for recombining compressed data, first adding means for adding a skip flag to the output of this recombining means at a timing other than the intraframe compressed data, and output of the recombining means. Second addition means capable of adding an adjustment bit for adjusting the data length is provided.

[0036]

In the present invention, when the first system of small blocks is selected, the size of a data block which can be independently decoded can be indicated by the small block data length for the intra-frame compressed data. Format conversion becomes easier when recording to. When the second system is selected, the adjustment bits are transmitted instead of the variable length data and the time adjustment is performed. When the third system is selected, the modification instruction signal is transmitted and the data can be modified even when the data is reproduced discontinuously.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing an embodiment of a high efficiency encoding / decoding system according to the present invention. FIG. 1 shows the structure of encoded data. 2 and 3 are explanatory diagrams for explaining a method of configuring the encoded data of FIG. Further, FIG. 5 is an explanatory diagram showing a bitstream structure (syntax) of the MPEG1 system.

First, only the part relating to the present embodiment will be described with respect to the syntax of the MPEG1 system shown in FIG. 5 (reference 1 "International Standard of Multimedia Coding" edited by Hiroshi Yasuda) (Maruzen Co., Ltd.). It should be noted that the abbreviations in the figure are not used in the document of the standard proposal, but are specific to Document 1.

As shown in FIG. 5, a sync code (hereinafter referred to as a start code) SSC (sequence start code) indicating the start of the layer is arranged at the head of the video sequence layer. Hereinafter, HS, VS, PAR, ..., UD are sequentially arranged, and then one or more GOPs (GOP layer data) are arranged. Finally, a synchronization code SEC (sequence end code) indicating the end of one or more sequences is arranged.

In the GOP layer, a start code GSC (group start code) indicating the start of GOP is arranged at the head.
Thereafter, data PICT (picture layer data) is formed by arranging TC, CG, ..., UD, and finally consisting of one or more I pictures and 0 or more pictures other than I pictures.
Array. The picture layer has a start code PSC (picture start code) at the beginning that indicates the start of the picture layer.
, And then TR, PCT, ... UD, and finally, one or more slice layer data SLICE (slice laye
r data). The slice layer has a start code SSC (slice start cod) that indicates the start of the slice layer.
e), then QS, EBS, EIS,
Finally, one or more macroblock layer data MB (macrob
lock layerdata) is arranged.

The macroblock layer has an MBAI (macroblock address in accordance with a condition defined for each coded image).
crement), MB STUFF (macroblock stuffing
) Or MB ESCAPE (macroblock escape). In the MPEG system, MBs that do not need to be transmitted due to interframe coding, such as when two screens are still images, are skipped without being transmitted. MBAI
Indicates the number of skips. The MBAI usually indicates the advance from the previously transmitted MB, but SLICE
The first MBAI indicates the horizontal position in the screen by the number of macroblocks. With these two pieces of information, the horizontal and vertical positions on the screen of each SLICE layer can be grasped. The number of skips that can be expressed by MBAI is up to 33, and the number of skips beyond this uses MB ESC corresponding to 33 skip MBs. MB S
TUFF is a dummy code used for rate control.

Table 2 below shows start codes.
As shown in Table 2, the start code SSC of each layer,
Each of GSC, PSC, and SSC is a special code composed of a plurality of bits and having a bit pattern distinguishable from other data. By detecting these codes, it is found to be the beginning of the video sequence layer, GOP layer, picture layer or slice layer. In addition, each SL
As shown in Table 2, the ICE start code (SSC) is a vertical pos that indicates the vertical block position of the screen.
ition is included.

[0043]

[Table 2] First, the configuration of the data format used in this embodiment will be described with reference to FIGS.

As shown in FIG. 2A, the 1-frame screen has horizontal 768 pixels × vertical 4 pixels with the luminance signal Y as a reference.
It is assumed to be composed of 80 pixels. This luminance signal Y
When one block is composed of 8 × 8 pixels, the number of luminance blocks in one frame screen is 96 as shown in FIG.
X 60. If the luminance signal Y and the color difference signals Cr and Cb are sampled at a sampling frequency of 4: 1: 1, the color difference signals Cr and Cb are shown in FIG.
As shown in (c) and (d), one frame screen is 24 ×
There are 60 color difference blocks. That is, the four luminance blocks Y and the respective color difference blocks Cr and Cb have the same size on the screen, and the four luminance blocks Y are the same.
And each of the color difference blocks Cr and Cb form a small block (corresponding to the MPEG macroblock MB) (FIG. 3A). The transform coding unit is one block.

Further, in the present embodiment, as shown in FIG. 3B, one large block is constituted by a set of four small blocks (a large block is an SL of MPEG system).
Equivalent to ICE). Therefore, one frame screen is composed of 24 small blocks in the horizontal direction and 60 small blocks in the vertical direction.
As shown in (c), it is composed of 6 large blocks in the horizontal direction and 60 large blocks in the vertical direction. Note that FIG.
In (c), the position on the screen for each large block is fixed, but the start position of the large block may be anywhere, and its length need not be fixed. For example, in FIG.
The numbers 1 to 16 in (c) may be one large block, and the numbers 1 to 32 may be one large block. In the MPEG system, the standard sampling frequency ratio of Y: Cr: Cb is 4: 2: 0, but in the present embodiment, the description will be made assuming that it is 4: 1: 1 for convenience of explanation.

FIG. 4 is an explanatory diagram for explaining the data array of block data.

As described above, the small block is composed of four luminance blocks Y and one color difference block Cr, Cb, respectively. As shown in FIG. 4A, the luminance blocks Y1, Y2, Y3, Y4, color difference blocks Cr, Cb are arranged in this order and transmitted. FIG. 4B shows the structure of each luminance block Y and color difference blocks Cr and Cb in a small block, and each block Y, Cr and Cb is sequentially described by the variable length data shown in FIG. 4B. . An EOB (End of Block) signal is added to the end of the variable length data. That is, one small block is formed by 6 pieces of the data shown in FIG. Note that FIG. 4B is an example in which all compression encoded data are sequentially described as variable-length data. However, as shown in FIG. 4C, the compression encoded data is converted into low-frequency data and high-frequency data. It may be transmitted separately as variable-length data.

Each large block (corresponding to SLICE) composed of four small blocks is transmitted in the order of the numbers shown in FIG. 3 (c). That is, as shown in FIG. 4 (d), data indicating the frame head is arranged at the head of one frame of data, and then the first, second, ..., Nth large blocks (n = n in FIG. 3) in the scanning order. The data of 360) is sequentially arranged. Next, the data at the beginning of the next frame is arranged.

The structure of each large block and each small block will be described with reference to FIG. In FIG. 1, the small blocks are shown surrounded by broken lines.

A large block start code 110 is arranged at the head of the large block. Large block start code 110
Indicates the data position of each large block. When an error or the like occurs in a large block, this start code 110 is detected to know the start position of the next large block. This prevents an error generated in a large block from spreading to other large blocks.

Next, the large block header 52 is arranged.
The large block header 52 indicates information of the entire large block in a unified manner, and indicates, for example, additional information. A plurality of small blocks 50 are arranged following the large block header 52.

In the small block 50, first, the quantization coefficient 53
Are arranged. In high efficiency encoding, data is quantized after DCT conversion. The quantization coefficient 53 is a coefficient for creating a quantization table used for this quantization processing.
After arranging the quantized coefficients 53, branches to branches 1 to 4 according to the conditions described later.

In the branch 1, the MBAI 104 is arranged first, and then the small block header 103 is arranged. The MBAI of the small block 50 at the head of the large block indicates the horizontal position of the large block, and the other MBAI indicates the difference in the number of addresses from the previously transmitted small block 50. For example, when a prediction error is 0 and a small block 50 that does not require transmission occurs as in the case of interframe coding of two still images, only the prediction error of this small block 50 is 0. Then, the transmission of the small block 50 is skipped. The MBAI other than the head of the large block indicates the number of small blocks 50 skipped by the branch described later.
Small block header 103 describes the header of small block 50. This small block header 103 indicates whether the compression is intraframe compression or interframe compression,
It is also possible to determine whether it is a field or a frame. In addition, the small block header 103 is
Contains other necessary information about

Next to the small block header 103, a branch is made to either a motion vector 55 or an intra data length 56.
The intra data length 56 indicates the data length of the small block 50 when the small block 50 is intraframe compressed data. As described above, the intra frame data can be independently decoded, and in the VCR or the like, the rear frame rearrangement improves the reproduction efficiency during special reproduction. That is, the information of the intra data length 56 makes it possible to relatively easily change the data format of the recording medium, and the variable length signal can be extracted without decoding even at the time of reproduction. On the other hand, when the small block 50 is the inter-frame compressed data, the small block header 103 branches to the motion vector 55. The motion vector 55 gives a vector (motion vector) indicating the pixel position of the previous frame serving as a reference of the inter-frame compressed frame.

Variable length data 57 is arranged following the intra data length 56 or the motion vector 55. The variable length data 57 is obtained, for example, by quantizing a DCT transform coefficient, and Huffman coding (variable length coding) the quantized output read by zigzag scanning according to the occurrence probability.

Branch 2 arranges the MB ESCAPE 102. MB ESCAPE 102 indicates that the number of small blocks to be skipped (hereinafter referred to as skip SB) is the predetermined number. When this embodiment is applied to the MPEG system,
The number of skips that can be expressed in MBAI104 is 33,
MB ESCAPE 102 indicates the number of skips of 33.
For example, when the number of skips is 34, MB ES
When the CAPE 102 and the MBAI 104 are 1 and the skip number is 68, the MB ESCAPE 102 is 2
(Indicates 66 skip SBs), MBAI104 is also 2
Is. By adopting this MBESCAPE102, the amount of data is reduced.

In branch 3, MB ST for data length adjustment
Arrange UFF59. The MB STUFF 59 is data of data length adjustment bits for keeping the transmission rate constant. The MB STUFF 59 may include information on the data length of the data length adjustment bit.

In branch 4, SKIP 101 indicating a modification instruction
Only transmit. SKIP101 is a branch 2 MB ES
It does not indicate that the difference value is zero as in CAPE102, but indicates that data is lost. The SKIP 101 controls the decoding circuit to correct the discontinuous portion of the data by the data of the previous frame, for example.

FIG. 6 is a block diagram showing an encoding circuit which realizes the data structure of FIG.

The preprocessing circuit 61 samples the input signal and outputs it to the subtracter 12 and the switch 62 in small block units shown in FIGS. The output of the subtracter 12 is also given to the switch 62, and the switch 62 is controlled by the intra-frame / inter-frame discrimination circuit 63 to output one of the two inputs to the DCT circuit 13. An external control signal and a motion determination signal from a motion detection circuit 26, which will be described later, are input to the intra-frame / inter-frame identification circuit 63 to control the switch. That is, the intra-frame / inter-frame identification circuit 63 causes the switch 62 to select the output of the pre-processing circuit 61 when the intra-frame compression is instructed by the external control signal or when the motion is larger than a predetermined value. Cause compression.

The DCT circuit 13 receives a signal in block units, and converts the input signal into frequency components by an 8 × 8 two-dimensional DCT (discrete cosine transform) process. DCT circuit
The output of 13 is given to the quantization circuit 15, and the quantization circuit 15 is given the quantization coefficient from the rate control circuit 64 to requantize the DCT output to reduce the redundancy of the signal of one block. The rate control circuit 64 generates a quantization coefficient based on the transform coefficient from the DCT circuit 13 and the data from the rate control circuit 67. The quantized data from the quantization circuit 15 is given to the variable length coding circuit 16 and the inverse quantization circuit 21.

By the way, when performing the inter-frame compression, it is necessary to compensate the motion of the image. The quantized output is given to the inverse quantization circuit 21, and the inverse quantization circuit 21 is the rate control circuit.
The quantized coefficient is given from 64, and the quantized output is inversely quantized and given to the inverse DCT circuit 22. The inverse DCT circuit 22 inverse DCT-processes the output of the inverse quantum circuit 21 to restore the original video signal and gives it to the adder 23. In this case, since the output of the subtractor 12 is difference information, the output of the inverse DCT circuit 22 is also difference information. The output of the adder 23 is fed back via the inter-frame prediction circuit 68 and the switch 69, and the adder 23 adds the difference data to the data of the previous frame to reproduce and output the data of the current frame.

The inter-frame prediction circuit 68 includes a motion detection circuit 26.
Also gives the motion vector. The motion detection circuit 26 receives the input signal from the pre-processing circuit 61 and obtains a motion vector. The inter-frame prediction circuit 68 corrects the output of the adder 23 with the motion vector and outputs the corrected output to the subtractor 12 and the adder 23 via the switch 69. The switch 69 is controlled by the intra-frame / inter-frame discrimination circuit 63.
Thus, the motion-compensated previous frame data is subtracted.
Supply to 12.

On the other hand, the variable length coding circuit 16 Huffman-codes the quantized output and outputs it to the buffer 65 and the data length measuring circuit 66. The buffer 65 accumulates the variable length code and outputs it to a multiplexer (hereinafter referred to as MPX) 70.
The rate control circuit 67, depending on the accumulation state of the buffer 65,
The output data amount from the variable length coding circuit 16 is monitored, and based on the monitoring result, the variable length coding circuit 16 is controlled to limit the output data amount, and the rate control circuit 64 is controlled to control the quantization circuit. The amount of output data is adjusted by changing the quantization coefficient of 15. The data length adjusting circuit 74 is controlled by the rate control circuit 67 to create adjusted bit data and output it to the buffer 65.

On the other hand, the data length measuring circuit 66 measures the data length of each block from the output of the variable length coding circuit 16, and further accumulates the block data length to obtain the data length of the small block, and the MPX 70 and the large size are calculated. Output to the block start code insertion circuit 71. Large block start code insertion circuit
The 71 accumulates the data lengths of the four small blocks from the output of the data length measuring circuit 66, further adds the data length of the header to obtain the large block data length, and obtains the start position of the large block. Output the start code to MPX70. The header signal creation circuit 72 creates headers for small blocks and large blocks. For example, the header signal creation circuit 72 creates a header signal indicating whether it is an intra frame or an inter frame based on the output of the intra-frame / inter-frame identification circuit 63 and outputs it to the MPX 70. The MPX 70 is controlled by the control circuit 73 to transmit the input data in the data array shown in FIG.

Next, the operation of the encoding circuit configured as described above will be described.

The input signal is pre-processed in the pre-processing circuit 61 and input to the subtracter 12 and the switch 62 in block units. When performing the intra-frame compression, the intra-frame / inter-frame identification circuit 63 causes the switch 62 to select the output of the pre-processing circuit 61. Block data from the preprocessing circuit 61 is DC
It is given to the T circuit 13 to perform two-dimensional DCT processing. DCT circuit 13
The output of is quantized in the quantization circuit 15 and converted into a variable length code in the variable length coding circuit 16. This variable length code is stored in the buffer 65. Depending on the storage state of the buffer 65, constant (rate) control of the data amount is performed. That is, the rate control circuit 67 controls the variable length coding circuit 16 to define the upper limit of the data length. In addition, the rate control circuit 64
Controls the quantization coefficient based on the output of the rate control circuit 67 and the DCT transform coefficient to adjust the data length.

On the other hand, when performing the inter-frame compression, the output of the preprocessing circuit 61 is given to the subtracter 12. The motion-compensated previous frame data is input to the subtractor 12 as a reference image, and the subtractor 12 switches the 2-input differential signal to the switch 62.
To the DCT circuit 13 via. The output of the quantization circuit 15 is inversely quantized in the inverse quantization circuit 21, and the inverse DCT circuit 22
In the inverse DCT process, the original data before inputting to the DCT circuit 13 is returned to the adder 23. The output of the adder 23 is given to the inter-frame prediction circuit 68, and the inter-frame prediction circuit 68 obtains a predicted value from the motion vector from the motion detection circuit 26 and outputs it to the subtractor 12, and at the same time, the adder via the switch 69. Return to 23. That is, the adder 23 locally obtains difference data (local decoded data), and the inter-frame prediction circuit 68 obtains a reference image from the difference data and the motion vector. Intra-frame / inter-frame identification circuit
An external control signal and motion detection signal 63 controls whether to perform intraframe compression or interframe compression.

Thus, the variable length coding circuit 16 obtains the variable length data of the inter frame and the variable length data 57 of the intra frame, the rate control circuit 64 obtains the quantization coefficient 53,
The motion detection circuit 26 obtains the motion vector 55 and supplies it to the MPX 70.

Further, the data length measuring circuit 66 measures the data length of the block from the variable length code, accumulates the data length of the block, obtains the data length of the small block, and outputs it to the MPX 70. Further, the large block start code insertion circuit 71 accumulates the small block data length to obtain the large block data insertion position and outputs the large block start code 110 to the MPX 70. Further, the header signal creating circuit 72 creates the large block and small block headers 52 and 103 and outputs them to the MPX 70. The output of the data length measuring circuit 66 becomes the intra data length 56 during the intra-frame compression. The data length adjustment circuit 74 is controlled by the rate control circuit 67 and outputs MBSTUFF59, which is adjustment bit data for the data adjustment bit length, to the MPX 70 via the buffer 65.

The MPX 70 is controlled by the control circuit 73 to select input data, sequence it, and output it. In this case, the control circuit 73 responds to the branches 1 to 4 with the MBA.
I104, MB ESCAPE102, MB STUFF59
Alternatively, the SKIP 101 is generated and output from the MPX 70.
For example, in the case of branch 4, the control circuit 73 causes the MPX 70 to output SKIP 101 indicating a modification instruction. In addition, MPE
In G system, MBAI 1-33, MB ESCAP
E and MB STUFF are identified by different codes in the same table, as shown in Macroblock Address Increment VLC (Reference 1) in Table 3 below. Also, S
Although KIP101 is not adopted in the MPEG system, for example, the number of skips that can be expressed by MB ESCAPE is 3
Alternatively, the code of the increment value 33 in Table 3 below may be assigned as SKIP101.

[0072]

[Table 3] By the codes 104, 102, 59, 101 generated by the control circuit 73, data can be arranged and transmitted in a data format using one of the systems of branches 1 to 4 in FIG. The system of branch 4 in FIG. 1 is adopted in a recording medium such as a VCR.

FIG. 7 is a block diagram showing a decoding circuit for decoding the transmission data of the data format of FIG.

The header extraction circuit 81 of the decoding circuit extracts a large block header and a small block header from the encoded data. The output of the header extraction circuit 81 is a variable length decoding circuit.
82, a control circuit 83, a quantization coefficient circuit 84, and a motion vector extraction circuit 85. The variable length decoding circuit 82 variable length decodes the input data and outputs it to the buffer 86. Control circuit 83
Is given data of an intra data length, a large block data length, and an adjustment bit length, and the control circuit 83 controls the variable length decoding circuit 82 using these data to prevent error propagation and input. Check if the block data is correct. The control circuit 83 is also supplied with a header signal and discriminates whether the data is the intra-frame compressed data or the inter-frame compressed data, and controls the switch 89 described later.

The output of the buffer 86 is given to the inverse quantization circuit 87. The quantized coefficient circuit 84 extracts the quantized coefficient from the output of the header extraction circuit 81 and supplies it to the inverse quantization circuit 87. The inverse quantization circuit 87 inversely quantizes the variable length decoding output using the quantized coefficient. And outputs it to the inverse DCT circuit 88. Inverse DCT circuit 88
Performs inverse DCT processing on the inverse quantized output to restore the original data and outputs it to the switch 89 and the adder 90. The switch 89 selects the decoded data from the inverse DCT circuit 88 and outputs it to the memory 92 when the data input by the control circuit 83 is shown to be the intra-frame compressed data.

On the other hand, the motion vector extraction circuit 85 extracts a motion vector from the output of the header extraction circuit 81 and outputs it to the predictive decoding circuit 91. The predictive decoding circuit 91 is supplied with the decoded data of the previous frame from the memory 92, and performs motion compensation on the data of the previous frame with the motion vector and outputs the data to the adder 90. The adder 90 adds the output of the predictive decoding circuit 91 and the output of the inverse DCT circuit 88 to decode the inter-frame compressed data and output it to the switch 89. switch
89 is controlled by the control circuit 83, and when the inter-frame compressed data is input, the output of the adder 90 is selected and stored in the memory.
Output to 92.

In this embodiment, the header extraction circuit 81
Is a branch 1 or 2, if the quantization coefficient is the inverse quantization circuit
87, in the case of branch 3, a signal indicating that the input data is an adjustment bit is output to the control circuit 83 so that the adjustment bit length is grasped. As a result, the control circuit 83 stops the decoding operation of the variable length decoding circuit 82. The control circuit 83 gives an instruction to restart the decoding after the decoding is stopped during the period in which the adjustment data is input.

Further, in the case of branch 4, a modification instruction is given to the buffer read instruction circuit 94. When this modification instruction is given, the buffer read instruction circuit 94 controls the buffer 86 to stop the reading of data, and at the same time controls the memory control circuit 93 to control the memory.
Disable writing to 92. As a result, the data in the memory 92 is not updated by the decoded data of the block or small block for which the modification instruction has been issued. That is, for these blocks, the decoded data of the previous frame remains without being updated. The buffer read instruction circuit
At 94, the modification length request is issued from the variable length decoding circuit 82 even when a variable length decoding error occurs.

As described above, in this embodiment, by adopting the start code indicating the beginning of the large block, the leading position of the large block can be known without requiring the large block data length information. The screen position of large block data can be grasped. Also, SKIP
The modification instruction can also be transmitted by. And start code, MBAI, MB ESCAPE and MB
Since STUFF is used, even when applied to the MPEG system, it facilitates format conversion on the receiving side, enables decoding that effectively uses discontinuous data, and further improves data utilization efficiency. It is possible to suppress the error propagation without lowering it.

FIG. 8 is a block diagram showing another embodiment of the present invention. This embodiment shows an example applied to a VCR.

The input signal is given to the frame head detecting means 200. The frame head detecting means 200 detects a large block at the head of the frame and outputs it to each large block head detecting means 201. In the MPEG system, the frame head and SL
If neither of the ICE heads is detected, the SLICE head of the frame head may not be detected.
Each large block head detecting means 201 detects a large block start code included in the input signal, detects the head of the large block, and outputs it to the large block screen position measuring means 202. The large block screen position measuring means 202 calculates the vertical position of the large block on the screen from the start code and the horizontal position on the screen from the MBAI information, and adds the packetizing means 204 and the address pointer. The screen position comparison information is output to the means 203.

The address / pointer adding means 203 outputs the screen position information of each large block or small block as an address, and also outputs the head position information in the packet of each large block. The packetizing means 204 adds address information and head position information of a large block to the input data, packetizes it in a predetermined unit, and outputs it to the error code adding means 206.

Error code adding means 206 Packetizing means 20
The error correction code is added to the output of 4 and is given to the multiplexing circuit 207, and the SYNC / ID creating means 205 outputs the synchronization signal (SYNC).
C) and the ID signal are created and given to the multiplexing circuit 207. The multiplexing circuit 207 multiplexes the SYNC.ID signal with the packet data to which the error correction code is added and gives it to the recording modulation means 208. The recording modulation unit 208 modulates the input data into a signal suitable for recording, and the recording amplifier 209 outputs the recording head.
It is given to 210 and recorded on tape 211.

On the other hand, in the reproducing system, the reproducing head 212
Reproduces the recorded data recorded on the tape 211 and gives it to the equalization / synchronization / demodulation circuit 214 via the reproduction amplifier 213.
The equalization / synchronization / demodulation circuit 214 waveform-equalizes the reproduction data,
The sync signal is extracted, demodulated, restored to the original digital signal and given to the TBC circuit 215.

The TBC circuit 215 corrects the time axis of the input data and supplies it to the error correction circuit 216. The error correction circuit 216 performs error correction using the error correction code and outputs it to the intra data extraction circuit 217. When the error remains uncorrected, the error correction circuit 216 also transmits the error flag to the intra data extraction circuit 217.

When the special reproduction mode is instructed by the reproduction mode signal, the intra data extraction circuit 217 extracts only the intra data using the intra data length information. The screen position of each data is identified by the screen position comparison information. The output of the intra data extraction circuit 217 is given to the code re-synthesis circuit 219, and the code re-synthesis circuit 219 receives the intra-data extraction circuit 217 based on the reproduction mode signal.
The output of is recombined for one frame. The intra data extraction circuit 217 outputs a valid data instruction signal to the SKIP data adjustment circuit 219, and the SKIP data adjustment circuit 218 indicates that the valid data instruction signal indicates invalid data such as a block that has not been reproduced. , SKIP flags are output to the code recombining circuit 219, and when a shortage of the data length is instructed, a signal instructing adjustment of the data length is output to the code recombining circuit 219. The code re-synthesis circuit 219 uses S
When the KIP flag is given, the SKIP flag indicating the SKIP (correction) block is output at the timing corresponding to the block that has not been reproduced, and if the data length is insufficient, the data length is adjusted. It is designed to output.

Next, the operation of the embodiment thus constructed will be described with reference to FIGS. 9 to 12. 9 is an explanatory diagram showing an input data string, FIG. 10 is an explanatory diagram showing a recording format of a VCR, FIG. 11 is an explanatory diagram for explaining extraction of intra data, and FIG. 12 is a diagram showing reproduced data. It is explanatory drawing for demonstrating the position on a screen.

The input signal shown in FIG. 9 is supplied to the frame head detecting means 200 and each large block head detecting means 201. A large block start code indicated by a shaded area in FIG. 9 is added to the head of each large block, and a start code corresponding to, for example, an MPEG picture start code is added to the large block at the head of the frame. The frame head detecting means 200 and each large block head detecting means 201 detect the head position of the frame and the head position of each large block from these start codes.

The large block screen position measuring means 202 obtains the vertical position of the large block on the screen from the start code, obtains the horizontal position of the screen from the MBAI information, and outputs the screen position contrast information. Contrast the large block with the screen position. The packetizing means 204 packetizes each packet unit length of the VCR. In this case, the screen position comparison information is converted into an address by the address / pointer adding means 203 and given to the packetizing means 204. The packetizing means 204 adds the address information and the start of the large block to the input data. The position information is added and packetized and output to the error code adding means 206.
Since each packet includes screen position comparison information and large block start position information, even if discontinuous data is reproduced due to an error or the like, it can be reproduced from the middle of the packet, and error propagation can be prevented. it can.

Error correction code is added to the packetized data by the error code adding means 206, and SY is further added.
The SYNC and ID signals from the NC / ID creating means are multiplexed in the multiplexing circuit 207 and given to the recording modulating means 208. The recording modulator 208 converts the recording format suitable for VCR and records it on the tape 211 via the recording amplifier 209 and the recording head 210.

FIG. 10 shows an example of recording data.
As shown in FIG. 10, SYNC is added to the beginning of the packet data.
The signal and the ID signal are arranged, then the screen position contrast information indicating the screen position of each large block is arranged, and then the head position information (l1, l2, l3, ...) Of each large block is arranged. As shown in FIG. 10, the start code (hatched portion) of the large block 1 is arranged after the interval l1 from the head position information of the large block 1, and then the large block 1 is arranged. The same applies to subsequent large blocks.

At the time of reproduction, the data recorded on the tape 211 is reproduced by the reproduction head 212 and reproduced by the reproduction amplifier 213.
To the equalization / synchronization / demodulation circuit 214 via. The equalization / synchronization / demodulation circuit 214 restores the reproduced data to digital data and supplies it to the TBC circuit 215, and the TBC circuit 215 corrects the time axis and supplies it to the error correction circuit 216. Error correction circuit
216 performs error correction using the error correction code and outputs it to the intra data extraction circuit 217.

As shown in FIG. 11, a start code is followed by intra data length information (1-A, 3-A, 4-A, ...) In a large block containing intra data. At the time of special reproduction, the extraction circuit 217 extracts only the intra data from the reproduction data by using the intra data length information and outputs it. For example, in the case of the large block 3, only the intra data of the large block 3 is obtained by using the intra data length information 3-A arranged next to the start code to find the start position of the large block 3 by the head position information l3. To extract.

The code re-synthesis circuit 219, during special reproduction,
The screen position is grasped by the screen position comparison information of each large block, and the input intra data of each large block is sequentially stored for one frame time corresponding to the screen position. Figure 1
Reference numeral 1 indicates the correspondence between the intra data stored in the code re-synthesis circuit 219 and the screen position. In the portions of the intra data and the inter data that have not been reproduced, the intra data extraction circuit 217 outputs a signal indicating that the data is invalid, and the SKIP data adjustment circuit 218 outputs the SK data.
The IP code is output to the code resynthesis circuit 219. As a result, the code re-synthesis circuit 219 skips parts other than the input intra data part. Note that the code reproduction / synthesis circuit 219 inserts and outputs an adjustment bit according to the data from the SKIP data adjustment circuit 218 when the data is insufficient after the synthesis.

As a result, even in special reproduction, the screen can be configured by effectively utilizing the reproduced data.

Furthermore, regarding special reproduction, FIG. 13 and FIG.
It will be specifically described with reference to.

Now, as shown in FIG. 20, it is assumed that only the data recorded in the shaded area can be reproduced by the special reproduction of the VCR. Furthermore, when the reproduction signal in the shaded area is decoded into a variable length code, the only data that can be restored to the original image signal using a single data is the intra-frame compressed data. On the other hand, for inter-frame compressed data, since only the difference (prediction) signal is decoded,
The data of the previous frame is required to obtain the original image signal. Therefore, only the intra-frame compressed data of the reproduction signal is restored to the image, and the other data is unnecessary.

Now, it is assumed that the image in the shaded area in FIG. 5 is restored by the intra-frame compressed data reproduced in the special reproduction, and the shaded area corresponds to a small block. That is, the 1st, 8th, 15th, 22nd,
... The reproduced data of each one small block of the large block can be decoded. Therefore, in this case, the VCR extracts data for only one small block of each of the first, eighth, fifteenth, ... Large blocks. That is, in the predetermined frame, the first data is added after the frame head data (FIG. 4D).
The data of the first small block of the large block is extracted. That is, the branch of the first small block is 1. Next, from the second small block to the fourth small block of the first large block, the branch is set to 4 and the retouching operation is instructed. Similarly, the second to the seventh
The branch by branch 4 is selected also in all the small blocks of the large block. That is, in this case, only the control signal for the modification instruction is transmitted. Next, the first small block of the eighth large block selects the branch by the branch 4, and the second small block selects the branch 1
Select the branch by. Thereafter, similarly, the variable length data is transmitted only to the portion corresponding to the hatched portion in FIG. 5, and the control signal for the modification instruction is transmitted to the other portions.

By the way, by selecting the branch by the branch 4, the amount of transmission data is reduced. For this reason,
There is a time margin after transmitting the data of the 360th large block. Therefore, the branch of the branch 3 is selected in order to adjust the time. FIG. 14 is an explanatory diagram for explaining this branch by the hatched portion.

FIG. 14 corresponds to one frame of data, and the shaded portion shows the adjustment bit by the branch 3. In FIG. 14, the data adjustment bit 59 is transmitted after the 360th large block of data is transmitted.

[0101]

As described above, according to the present invention, even when the macroblock data length information does not exist and the branch by the quantization coefficient is not performed, the format conversion on the receiving side is facilitated, and This has the effect of enabling decoding that effectively uses discontinuous data, and suppressing the propagation of errors without lowering the data utilization efficiency.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an embodiment of a high efficiency encoding / decoding system according to the present invention.

FIG. 2 is an explanatory diagram for explaining a method of configuring the data in FIG.

FIG. 3 is an explanatory diagram for explaining a method of configuring the data in FIG.

FIG. 4 is an explanatory diagram for explaining a data array of block data.

FIG. 5 is an explanatory diagram for explaining the syntax of the MPEG system.

FIG. 6 is a block diagram showing an example of an encoding circuit.

FIG. 7 is a block diagram showing an example of a decoding circuit.

FIG. 8 is a block diagram showing another embodiment of the present invention.

9 is an explanatory diagram for explaining the operation of the embodiment in FIG.

FIG. 10 is an explanatory diagram for explaining the operation of the embodiment of FIG.

FIG. 11 is an explanatory diagram for explaining the operation of the embodiment of FIG.

FIG. 12 is an explanatory diagram for explaining the operation of the embodiment of FIG.

13 is an explanatory diagram for explaining the operation of the embodiment of FIG.

FIG. 14 is an explanatory diagram for explaining the operation of the embodiment of FIG.

FIG. 15: 261 is an explanatory view for explaining a compression method of the recommendation proposal of H.261.

FIG. 16 is a block diagram showing the recording side of a recording / reproducing apparatus that employs predictive coding.

FIG. 17 is an explanatory diagram showing the structure of a macro block in a conventional example.

FIG. 18 is an explanatory diagram showing a data stream of a recording signal.

FIG. 19 is a block diagram showing the decoding side (reproduction side) of the recording / reproducing apparatus.

FIG. 20 is an explanatory diagram for explaining a recording track created on a recording medium by a VCR.

FIG. 21 is an explanatory diagram for explaining a hierarchical structure of the MPEG system.

[Explanation of symbols]

50 ... Small block, 52 ... Large block header, 56 ... Intra data length, 57 ... Variable length data, 59 ... MB STUF
F, 101 ... SKIP, 102 ... MB ESCAPE, 103
… Small block header, 110… Large block start code

Claims (3)

[Claims] 1. A small block composed of at least one group of blocks, which is a coding unit of input data, and a special code, which is composed of at least one or more small blocks and which indicates the data position at the head. And a variable block constituted by at least one or more data sets obtained by variable-length coding the input data for each block, which is a coding unit, as a first system. It has long data, header information of this variable length data, and a small block data length that indicates the data length in the case of intra-frame coding, has adjustment bit data as a second system, and has a third system. With a modification instruction signal as
A high-efficiency coding / decoding system, which transmits by including data indicating which one of the first to third systems. 2. Coding means for variable length coding input data for each block which is a coding unit and outputting the data, and data length measuring means for measuring and outputting the data length from the output of the coding means, Header information creating means for creating and outputting header information for the output of the encoding means; and a small block composed of at least one or more of the blocks, the output of the encoding means, the output of the data length measuring means, and The output of the header information creating means is packetized as a first system, predetermined adjustment bit data is arranged as a second system, and a modification instruction signal is packetized as a third system. To first packet means for packetizing by at least one of the third to third systems, and a large block composed of at least one or more of the small blocks, High-efficiency coding, characterized in that the output of the packet means of (1) comprises a special code indicating that the data is the large block and the second packet means for packetizing and outputting the output of the header information creating means. Decryption system. 3. In the recording system, one large frame is formed by arranging at least one small block consisting of at least one coding unit block and arranging a special code indicating the data position at the head of the block. An input signal having one or more of them is input, and a screen head large block detection unit that detects the large block at the screen head, a head detection unit that detects the head of each large block, each large block and each small block Address generating means for obtaining an address corresponding to the screen position of at least one of the blocks, and packetizing means for packetizing the input signal by adding the address of the address generating means and the information of the large block start position Then, in the reproduction system, an extraction means for extracting only the intra-frame compressed data from the reproduction signal, and a predetermined time unit Recombining means capable of recombining the in-frame compressed data, first adding means for adding a skip flag to the output of this recombining means at a timing other than the in-frame compressed data, and the recombining means A high-efficiency coding / decoding system, comprising: a second adding means capable of adding an adjustment bit for adjusting the data length to the output of.