JP4113233B2 - Transmission system and transmission method - Google Patents

Description

  The present invention relates to a transmission system that transmits encoded data subjected to high-efficiency compression encoding processing including variable-length encoding as transmission data to a decoding-side apparatus.

  In recent years, digital processing of images has been studied. Various systems have been studied for recording digital image data on a magnetic recording / reproducing apparatus (VCR). FIG. 5 is an explanatory diagram for explaining the comparison between the position on the screen and the position on the recording track of the recording medium in the VCR. FIG. 5A shows the position on the screen, and FIG. 5B shows the position on the recording track.

  FIG. 5A shows a one-frame screen divided into eight parts in the vertical direction. Further, FIG. 5B shows the recording positions of the respective tracks # 1 to # 9. Recording on the recording medium starts from the lowermost end A of the track # 1 and sequentially proceeds toward the uppermost end I. For example, if one frame data is recorded on one track, the data from the uppermost edge a to b of the screen is recorded from the lowermost edge A to B of the recording medium, and thereafter the same from the b to the lowermost edge i. Are sequentially recorded from B to the top end I of the recording medium. Also, for example, if 1 frame data is recorded on 2 tracks, data from a to e on the screen is recorded on A to I on the # 1 track, and data on e to i on the screen is A on the # 2 track. To I.

  FIG. 6 is an explanatory diagram showing the relationship between the trace pattern and the playback envelope during 3 × speed playback. FIG. 6A shows a trace pattern in the case of reproducing at 3 × speed with the head scanning time on the horizontal axis and the track pitch or tape travel distance on the vertical axis. The symbols + and − in FIG. 6A indicate the regular azimuth of the reproducing head. In the figure, the numbers indicate the numbers of the playback tracks, the odd tracks are plus azimuths, and the even tracks are minus azimuths. FIGS. 6B to 6D respectively show a reproduction envelope by a normal head, a reproduction envelope by a special head, and a combined envelope of both heads. FIG. 7 is an explanatory diagram showing the configuration of the recording / reproducing head.

  As shown in FIG. 7, it is assumed that a rotating cylinder 3 equipped with a normal head 1 and a special head 2 is used for recording and reproduction. A pair of normal heads 1 having different azimuths and a pair of special heads 2 having different azimuths are mounted on the rotating cylinder 3, and the azimuths of the adjacent normal heads 1 and special heads 2 are also arranged. Is different. As shown by the symbol + in FIG. 6A, the first and third tracks are traced by the normal head 1 of plus azimuth in the first scanning period (trace period), and minus azimuth in the next scanning period. Normally, the fourth and sixth tracks are traced by the head 1. In this way, the reproduction envelope shown in FIG. 6B is obtained by the normal head 1. In the first scanning period, the second track is traced by the special head 2, and the reproduction envelope shown in FIG. 6C is obtained in the same manner. By synthesizing the reproduction output of the normal head 1 and the reproduction output of the special head 2, a synthesis envelope shown in FIG. 6D is obtained.

Table 1 below shows the reproduction output of 3 × speed reproduction (FIG. 6D) and the correspondence between the trace position and the position on the frame screen.

  As shown in FIG. 6D and Table 1, during the first scanning period, A to C of the first track # 1 are reproduced by the normal head 1 during the first ¼ time, and the next ½ During the period, C to G of the second track # 2 are reproduced by the special head 2, and G to I of the third track # 3 are reproduced by the normal head 1 during the next ¼ time. Thereafter, similarly, three tracks are reproduced in one scanning period.

  When one frame screen is recorded on one track, as shown in Table 1, A to C of the first track # 1 correspond to a to c on the screen of the first frame, and the second track # 2 C to G correspond to c to g of the screen of the second frame, and G to I of the third track # 3 correspond to g to i of the screen of the third frame. Therefore, in this triple speed playback, as shown in FIG. 8A, the playback screen is displayed by combining the pictures at the respective positions of the first to third frames.

  In addition, when one frame screen is recorded on two tracks, as shown in Table 1, A to C of the first track # 1 correspond to a to b of the screen of the first frame, and the second track # 2 C to G correspond to f to h of the screen of the first frame, and G to I of the third track # 3 correspond to d to e of the screen of the second frame. Further, A to C of the fourth track # 4 correspond to e to f of the screen of the second frame, C to G of the fifth track # 5 correspond to b to d of the screen of the third frame, and the sixth G to I of the track # 6 correspond to h to i on the screen of the third frame. Therefore, in this case, as shown in FIG. 8B, the reproduction screen includes a mixture of pictures at positions of the first to third frames.

  Incidentally, in recent years, various standardization proposals have been proposed for high-efficiency encoding for compressing image data. High-efficiency encoding technology encodes image data with a smaller bit rate in order to improve the efficiency of digital transmission and recording. For example, CCITT (Comite Consultafif Internatinal Telegraphique et Telephonique) is a standardization recommendation H.264 standard for videoconferencing / videophones. 261 is proposed. In this recommendation, encoding is performed using a frame I subjected to intra-frame compression (Intra-frame) and a frame P subjected to inter-frame compression (Inter-frame or Predictive frame).

  FIG. 9 is an explanatory diagram for explaining the compression method of this recommendation.

  Frame I is obtained by encoding one frame of image data by DCT (Discrete Cosine Transform) processing. The frame P is obtained by encoding image data by predictive encoding using the frame I or another frame P. Furthermore, the bit rate is further reduced by variable-length encoding these encoded data. Since the frame I is encoded only by the information in the frame, it can be decoded only by the single encoded data. On the other hand, the frame P is encoded using the correlation with other image data, and cannot be decoded only by the single encoded data.

  FIG. 10 is a block diagram showing the recording side of a conventional recording / reproducing apparatus employing such predictive coding.

  The luminance signal Y and the color difference signals Cr and Cb are supplied to the multiprocessing circuit 11 and multiplexed in units of blocks of 8 pixels × 8 horizontal scanning lines. For the color difference signals Cr and Cb, the horizontal sampling rate is ½ that of the luminance signal Y. Accordingly, during the period in which two 8 × 8 luminance blocks are sampled, one 8 × 8 block is sampled for the color difference signals Cr and Cb. As shown in FIG. 11, the multiprocessing circuit 11 constitutes a macro block by four blocks of two luminance blocks Y and one chrominance block Cr, Cb. Two luminance blocks Y and one color difference block Cr, Cb each represent the same position on the screen. The output of the multiprocessing circuit 11 is given to the DCT circuit 13 via the subtractor 12.

  When performing intra-frame compression, as will be described later, the switch 14 is off, and the output of the multiprocessing circuit 11 is input to the DCT circuit 13 as it is. The DCT circuit 13 receives a signal in which one block is composed of 8 × 8 pixels, and the DCT circuit 13 converts the input signal into a frequency component by 8 × 8 two-dimensional DCT (discrete cosine transform) processing. Thereby, a spatial correlation component can be reduced. That is, the output of the DCT circuit 13 is given to the quantization circuit 15, and the quantization circuit 15 requantizes the DCT output with a predetermined quantization coefficient, thereby reducing the redundancy of the signal of one block. Note that block pulses are supplied to the multiplexing processing circuit 11, the DCT circuit 13, the quantization circuit 15 and the like which operate in units of blocks.

  The quantized data from the quantizing circuit 15 is given to the variable length coding circuit 16, and is subjected to, for example, Huffman coding based on the result calculated from the statistical code amount of the quantized output. As a result, short bits are assigned to data having a high appearance probability, and long bits are assigned to data having a low appearance probability, thereby further reducing the amount of transmission. The output of the variable length coding circuit 16 is given to the error correction encoder 17, and the error correction encoder 17 adds a parity for error correction and outputs it to the multiplexing circuit 19.

  The output of the variable length coding circuit 16 is also given to the coding control circuit 18. The amount of output data varies greatly depending on the input image. Therefore, the encoding control circuit 18 monitors the output data amount from the variable length encoding circuit 16, and controls the quantization coefficient of the quantization circuit 15 to adjust the output data amount. Also, the encoding control circuit 18 may control the variable length encoding circuit 16 to limit the amount of output data.

  On the other hand, the synchronization / ID creation circuit 20 creates a frame synchronization (sync) signal and an ID signal indicating data contents and additional information, and outputs them to the multiplexing circuit 19. The multiplexing circuit 19 forms data of one sync block with the sync signal, ID signal, compressed signal data, and parity, and outputs the data to a recording encoding circuit (not shown). The recording encoding circuit records and encodes the output of the multiplexing circuit 19 according to the characteristics of the recording medium, and then records it on a recording medium (not shown) via a recording amplifier (not shown).

  On the other hand, when the switch 14 is on, the signal of the current frame from the multiprocessing circuit 11 is subtracted from the data of the previous frame subjected to motion compensation, which will be described later, in the subtractor 12 and supplied to the DCT circuit 13. It is done. In other words, in this case, interframe coding is performed in which difference data is coded using the redundancy of images between frames. In the inter-frame coding, when the difference between the previous frame and the current frame is simply obtained, the difference becomes large when there is motion in the image. Therefore, the position of the previous frame corresponding to the predetermined position of the current frame is obtained to detect the motion vector, and the difference is obtained at the pixel position corresponding to the motion vector to perform motion compensation to reduce the difference value. Yes.

  That is, the output of the quantization circuit 15 is also given to the inverse quantization circuit 21. The quantized output is inversely quantized by the inverse quantization circuit 15 and further subjected to inverse DCT processing by the inverse DCT circuit 22 to be restored to the original video signal. In DCT processing, requantization, inverse quantization, and inverse DCT processing, the original information cannot be completely reproduced, and some information is lost. In this case, since the output of the subtractor 12 is difference information, the output of the inverse DCT circuit 22 is also difference information. The output of the inverse DCT circuit 22 is given to the adder 23. The output of the adder 23 is fed back via a variable delay circuit 24 and a motion correction circuit 25 that delay the signal for about one frame period. The adder 23 adds the difference data to the previous frame data and the current frame data. Is output to the variable delay circuit 24.

  The previous frame data from the variable delay circuit 24 and the current frame data from the multiprocessing circuit 11 are applied to the motion detection circuit 26 to detect a motion vector. The motion detection circuit 26 obtains a motion vector by, for example, full search motion detection by matching calculation. In full search type motion detection, the current frame is divided into predetermined blocks, and a search range of, for example, horizontal 15 pixels × vertical 8 pixels is set in each block. For each block, matching calculation is performed in the search range corresponding to the previous frame, and an approximation between patterns is calculated. Then, the block of the previous frame giving the minimum distortion in the search range is calculated, and a vector obtained from the block of the current frame is detected as a motion vector. The motion detection circuit 26 outputs the obtained motion vector to the motion correction circuit 25.

  The motion correction circuit 25 extracts the data of the corresponding block from the variable delay circuit 24, corrects it according to the motion vector, outputs it to the subtractor 12 via the switch 14, and after the time adjustment, the adder 23 Output to. Thus, the motion-compensated previous frame data is supplied from the motion compensation circuit 25 to the subtractor 12 via the switch 14, and when the switch 14 is turned on, the interframe compression mode is set, and when the switch 14 is turned off. Intra-frame compression mode.

The switch 14 is turned on / off based on a motion determination signal. That is, the motion detection circuit 26 creates a motion determination signal depending on whether the magnitude of the motion vector exceeds a predetermined threshold value, and outputs the motion determination signal to the logic circuit 27. The logic circuit 27 controls the switch 14 to be turned on and off by logic judgment using the motion judgment signal and the refresh cycle signal. The refresh cycle signal is a signal indicating the intra-frame compressed frame I in FIG. If the refresh cycle signal indicates that the frame I has been input, the logic circuit 27 turns off the switch 14 regardless of the motion determination signal. In addition, when the motion determination signal indicates that the motion is relatively fast and the minimum distortion based on the matching calculation exceeds the threshold, the logic circuit 27 turns off the switch 14 even when the frame P is input. In-frame compression encoding is performed. Table 2 below shows on / off control of the switch 14 by the logic circuit 27.

  FIG. 12 is an explanatory diagram showing a data stream of a recording signal output from the multiplexing circuit 19.

  As shown in FIG. 12, the first and sixth frames of the input image signal are converted into intra-frame compressed frames I1 and I6, respectively, and the second through fifth frames are converted into inter-frame compressed frames P1 through P5. Although not shown, a header indicating whether the data is intraframe compressed data or interframe compressed data is added to the encoded frame data. The ratio of the data amount of frame I and frame P is (3 to 10): 1. Although the data amount of frame I is relatively large, the data amount of frame P is extremely reduced. The data subjected to the inter-frame compression processing cannot be decoded unless other frame data is decoded.

  FIG. 13 is a block diagram showing the decoding side (playback side) of the recording / playback apparatus.

  The compressed code data recorded on the recording medium is reproduced by a reproduction head (not shown) and input to the error correction decoder 31. The error correction decoder 31 corrects errors that occur during transmission and recording. The reproduction data from the error correction decoder 31 is supplied to the variable length data decoding circuit 33 via the code buffer memory circuit 32 and decoded into fixed length data. The code buffer memory circuit 32 may be omitted.

  The output of the variable length decoding circuit 33 is inversely quantized by the inverse quantization circuit 34, is subjected to inverse DCT processing by the inverse DCT circuit 35, is decoded into the original video signal, and is given to the terminal a of the switch 36. On the other hand, the output of the variable length decoding circuit 33 is also given to the header signal extraction circuit 37. The header signal extraction circuit 37 searches for a header indicating whether the input data is intra-frame compressed data or inter-frame compressed data, and outputs it to the switch 36. The switch 36 selects the terminal a and outputs the decoded data from the inverse DCT circuit 35 when a header indicating the intra-frame compressed data is given.

  The inter-frame compressed data is obtained by adding the output of the inverse DCT circuit 35 and the output of the previous frame from the predictive decoding circuit 39 by the adder 38. That is, the output of the variable length decoding circuit 33 is given to the motion vector extraction circuit 40 to obtain a motion vector. This motion vector is given to the predictive decoding circuit 39. On the other hand, the decoded output from the switch 36 is delayed by one frame period by the frame memory 41. The predictive decoding circuit 39 performs motion compensation on the decoded data of the previous frame from the frame memory 41 with a motion vector and outputs the motion data to the adder 38. The adder 38 adds the output of the predictive decoding circuit 39 and the output of the inverse DCT circuit 35 to decode the inter-frame compressed data and outputs it to the terminal b of the switch 36. When the inter-frame compressed data is input, the switch 36 selects the terminal b by the header and outputs the decoded data from the adder 38. Thus, the compression and expansion operations are performed without delay in both the intra-frame compression mode and the inter-frame compression mode.

  However, the intra-frame compression frame I and the inter-frame compression frame P have different code amounts. When the data stream shown in FIG. 12 is recorded on a recording medium, one frame is reproduced by the reproduction data in the above-described triple-speed reproduction. It is not always possible. Furthermore, since the inter-frame compressed frame P cannot be decoded by a single frame, it cannot be reproduced when a frame that is not decoded occurs, such as triple-speed reproduction.

  Further, a block (8 × 8 pixels) obtained by dividing one frame into a plurality is quantized, and the quantized data is further subjected to variable length coding, so that the transmission amount is further reduced. In such data that has been subjected to high-efficiency compression coding including variable-length coding, if part of the data is lost and transmitted to the decoding means, the data after the lost data is correctly decoded. Cannot be restored, that is, the image cannot be restored correctly. For example, when such data is recorded on a recording medium such as a tape and played back at a triple speed, the data is lost and data that is not transmitted is generated. For example, some blocks are lost, and the subsequent data is restored. However, it is not played back as a correct image. However, conventionally, there is no way for the decoding means to input such data to detect whether or not such data is missing, and the decoding circuit performs an extra decoding process regardless of whether or not the data is missing. At the same time, useless image reproduction was performed.

  This problem will be described with reference to FIGS. FIG. 14 is an explanatory diagram for explaining a broadcasting system employed in a video conference and a video phone.

  In a broadcasting station, a video signal from a camera (not shown) is encoded with high efficiency by an encoding circuit 51, and an error correction code corresponding to the transmission path 54 is added by an error correction encoder 52. The transmission modulation circuit 53 performs modulation suitable for the transmission path 54 on the output of the error correction encoder 52, converts it into a radio wave or the like, and outputs it to the transmission path 54. On the reception side, the reception signal input via the transmission path 54 is demodulated by the reception demodulation circuit 55. The error correction circuit 56 corrects an error generated in the transmission path 54 and supplies it to the switch 57 and also to the VCR 58. The VCR 58 records the input signal, reproduces it, and gives it to the switch 57. The switch 57 is switched by an input switching signal based on a user operation, selects the output of the error correction circuit 56 or the VCR 58, and outputs it to the decoding circuit 59. The decoding circuit 59 decodes the high-efficiency encoded signal and returns it to the original signal, and the error correction circuit 60 corrects the remaining error without being corrected in the decoded output and outputs it to a monitor television (not shown). Thus, the broadcast signal input via the transmission path 54 or the reproduction signal from the VCR 58 is displayed on the display screen of the monitor television.

  FIG. 15 is a block diagram showing the configuration of a VCR capable of high-efficiency encoding / decoding. 14 has the same configuration as that on the right side from the broken line in FIG.

  The video signal is encoded with high efficiency by the encoding circuit 61 and supplied to the error correction encoder 62. The error correction encoder 62 adds an error correction parity code conforming to the VCR to the encoded data and outputs it to the adder 63. The adder 63 adds the synchronization signal and ID signal created by the synchronization / ID creation circuit 64 to the output of the error correction encoder 62, and gives it to the recording modulation circuit 65. The recording modulation circuit 65 performs modulation suitable for recording on the recording medium and outputs it to the recording amplifier 66. The recording amplifier 66 amplifies the modulation signal, applies it to the magnetic head 67, and records it on the tape 68.

  At the time of reproduction, the tape 68 is traced by the magnetic head 67, and the recorded signal is reproduced and supplied to the reproduction amplifier 69. A reproduction signal from the reproduction amplifier 69 is subjected to waveform equalization in order to reduce intersymbol interference in the waveform equalization circuit 70 and is provided to the synchronization circuit 71. The synchronizing circuit 71 returns the reproduction data to the recording data string unit and gives it to the demodulation circuit 72, and the demodulation circuit 72 demodulates the reproduction data and gives it to the error correction circuit 73. The error correction circuit 73 performs error correction and outputs the result to the decoding circuit 74. The decoding circuit 74 and the error correction circuit 75 have the same configuration as the decoding circuit 59 and the error correction circuit 60 of FIG. 14, respectively, decode the output of the error correction circuit 73, correct the error, and output it.

  Assume that the VCR 58 is selected by the switch 57 in FIG. Data transmitted from the broadcasting station side via the transmission path 54 is supplied to the VCR 58 via the reception demodulation circuit 55 and the error correction circuit 56. In this way, the recording data string shown in FIG. In the figure, the subscript n indicates the track number, and the subscript m indicates the recording data string number. That is, Gn, m means the mth data string of the nth track.

  Assuming that a data string Gn, 1 to Gn, m is recorded in the VCR 58, and this data string is reproduced without error, during normal reproduction, as shown in FIG. It will be the same. However, at the time of triple-speed reproduction, as described above, the magnetic head reproduces across the track, so the reproduced data does not match the recorded data. That is, as shown in FIG. 16C, the first track is reproduced from the k0th data string to the k1th data string, the k2th to k3th data strings are reproduced on the second track, and the k4th data string is reproduced on the third track. Data from the data string to the k5th data string are reproduced.

  The VCR 58 performs demodulation processing, error correction processing, decoding processing, and the like on the reproduced data. In the portion where the reproduction track is switched, the data may not be reproduced reliably, and the reproduction data string becomes discontinuous at the switching point of the reproduction track, so that the data in the vicinity of the switching portion of the track cannot be used for decoding. In the VCR 58, the synchronization signal and the ID signal are added to the video data at the time of recording, and the data is not reproduced in the middle of the synchronization block because the synchronization circuit demodulates by the synchronization circuit at the time of reproduction. Even in this case, it can be demodulated from the start position of the next synchronization block. Thus, as shown in FIG. 16 (d), the reproduction data obtained in one scan of the triple speed reproduction does not output a broken line portion with respect to FIG. 16 (c).

  However, the monitor television cannot reconstruct an image using these data even if a header and an address are added to the data, and simply reproduces the images sequentially in the order of the input image data. Since the data string to be transmitted is a variable length code, the starting position of the next data string k2 'cannot be identified even if the data length of the broken line in FIG. Therefore, in a system that continuously decodes an input data string such as a videophone, subsequent data cannot be used if the data is interrupted.

Therefore, in order to stop error propagation, when the range in which variable length coding is completed is the number of image information blocks corresponding to the data areas of a plurality of synchronization blocks, decoding of image information is performed in units of synchronization blocks. Thus, there is one that stops error propagation in the synchronization block and enables special reproduction. That is, a range (for example, one frame or a predetermined number of image blocks) in which variable length encoding is completed is determined, encoding is performed with a fixed length unit, and decoding is performed in that unit. Propagation is stopped in that unit. In other words, when the encoding device encodes the input signal, it performs a special encoding process to make it a fixed length with a fixed length, and prevents error propagation even if an error occurs in specific unit data is doing. (See Patent Document 1)
JP-A-4-86181

  As described above, when error-efficient data such as missing data is transmitted to the decoding device when transmitting data that has been subjected to high-efficiency encoding processing including variable-length encoding from the encoding device to the decoding device, conventionally, On the device side, there is a problem in that unnecessary data may be decoded and unnecessary data restoration processing may be performed. Also, in Patent Document 1, when the encoding device encodes an input signal, a special encoding process of making the input signal a fixed length must be executed, which increases the load on the encoding device side. Not only affects the quality of the restored image.

  The present invention has been made in view of such a problem, and when transmitting data subjected to high-efficiency compression encoding processing including variable-length encoding from the encoding device to the decoding device, there is an error on the decoding device side. An object of the present invention is to provide a transmission system that recognizes generated transmission data and enables autonomous decoding processing on the decoding device side.

  According to one aspect of the present invention, in a transmission system for transmitting data from an encoding unit that outputs variable length encoded data by performing compression encoding processing including variable length encoding on an input signal, Means for generating first transmission data consisting of variable-length encoded data and a first identifier arranged before the data and indicating the identification of the data, and outputting the first transmission data to the decoding means; fixed pattern data; A means for generating second transmission data that is arranged before the fixed pattern data and that includes a second identifier indicating that the decoding means does not target the fixed pattern data; and variable length data Means for generating third transmission data; and when outputting the first transmission data as transmission data to the decoding means, the second transmission data is inserted into a gap generated in the transmission data stream. And means for outputting the serial third transmission data,
  A transmission system characterized by transmitting a stream of transmission data including the first, second and third transmission data to the decoding means at a predetermined bit rate.
  According to another aspect of the present invention, in a transmission method for transmitting data from an encoding unit that performs compression encoding processing including variable length encoding to an input signal and outputs variable length encoded data to a decoding unit, Generating first transmission data comprising the variable-length-encoded data and a first identifier arranged in front of the data and indicating the identification of the data, and outputting the first transmission data to the decoding means; fixed pattern data Generating second transmission data that is arranged in front of the fixed pattern data and that the decoding means includes a second identifier indicating that the fixed pattern data is not to be decoded; and from variable length data And generating the third transmission data, and when outputting the first transmission data as the transmission data to the decoding means, the second transmission data and the previous data are inserted into a gap generated in the transmission data stream. Outputting a third transmission data, and transmitting the transmission data stream including the first, second, and third transmission data to the decoding means at a predetermined bit rate. It is a transmission method.

  According to the present invention, when transmitting data that has been subjected to high-efficiency compression encoding processing including variable-length encoding from the encoding device to the decoding device side, transmission data in which an error has occurred on the decoding device side is recognized, It is possible to provide a transmission system that enables autonomous decoding processing on the decoding device side.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a coding side of a transmission system according to the present invention. FIG. 2 is a block diagram showing an embodiment of the decoding side of the transmission system according to the present invention. 1 and 2, the same components as those in FIG. 15 are denoted by the same reference numerals. This embodiment is applied to a recording / reproducing apparatus.

  In FIG. 1, the received video signal input via the transmission path 80 is input to the reception demodulation circuit 81. The received video signal is sequentially transmitted in units of frames. Each frame is divided into small blocks of 8 pixels in the horizontal direction and 8 pixels in the vertical direction, and a head flag is added to the head of the frame. Each block data is subjected to encoding such as DCT processing. The reception demodulation circuit 81 demodulates the received video signal and outputs it to the format conversion circuit 82 and the address creation circuit 83. The multiplexing circuit 84 multiplexes and outputs the outputs of the address creation circuit 83 and the format conversion circuit 82.

  FIG. 3 is an explanatory diagram for explaining the format conversion circuit 82, the address generation circuit 83, the multiplexing circuit 84, and the error correction encoder 62.

  As shown in FIG. 3 (a), one frame of image data from the transmission path 80 is added with a head flag indicating the head of the frame at the head, and is composed of a plurality of block data of blocks 1, 2,. ing. The address creation circuit 83 attaches a series of frame numbers or headers to the head flag, creates address data of Block (B) 1, 2,... For each block 1, 2,. Output to. The format conversion circuit 82 converts the format of the received image data and outputs it to the multiplexing circuit 84 so that the address data is arranged at the head of each block data. The multiplexing circuit 84 adds address data to the head of each block data and outputs the data stream shown in FIG. 3B to the error correction encoder 62. In order to improve the data reproduction efficiency, the format conversion circuit 82 may change the order of the reproduction data.

  The error correction encoder 62 adds a parity signal P suitable for recording to the output of the multiplexing circuit 84 and outputs it to the adder 63. The synchronization / ID creation circuit 64 creates a synchronization signal and an ID signal and outputs them to the adder 63. The adder 63 adds the synchronization signal S to the output of the error correction encoder 62 and outputs it. Eventually, as shown in FIG. 3C, the adder 63 outputs a data stream in which the synchronization signal S is added to the head of the frame number and the parity signal P and the synchronization signal S are added in the middle of the data stream. Is done.

  The output of the adder 63 is given to the recording modulation circuit 65. The recording modulation circuit 65 performs modulation suitable for recording on the output of the adder 63 and outputs the result to the recording amplifier 66. The recording amplifier 66 amplifies the modulation signal from the recording modulation circuit 65, gives it to the magnetic head 67, and records it on the magnetic tape 68.

  On the other hand, on the decoding side, the data recorded on the magnetic tape 68 is reproduced by the magnetic head 67 as shown in FIG. The reproduction signal from the magnetic head 67 is supplied to the reproduction amplifier 69, and the reproduction amplifier 69 amplifies the reproduction signal and supplies it to the waveform equalization circuit 70. The waveform equalization circuit 70 equalizes the waveform of the reproduced signal to remove intersymbol interference, enables data identification, and outputs the data to the synchronization circuit 71. The synchronization circuit 71 extracts the synchronization signal and the ID signal and supplies the reproduction data to the demodulation circuit 72 in units of the synchronization signal. The demodulation circuit 72 demodulates the reproduction data and gives it to the error correction circuit 93.

  The error correction circuit 93 corrects the error of the reproduced data and outputs it to the delay circuit 85, and adds an error flag to the data that could not be corrected. Further, the error correction circuit 93 outputs the error flag and the address data of the decoded data to the zero data creation control circuit 86. The zero data creation control circuit 86 outputs a switching signal to the switches 87 and 88 in synchronization with a block having an error (error block) from the error flag and the address data, and controls the delay circuit 85. The zero data creation control circuit 86 creates address data by estimating an address from address data before and after the address data when an error flag indicates an address data error. .

  The output of the zero data creation circuit 89 with an error flag is supplied to the terminal a of the switch 87, and the data length adjustment bit 90 is supplied to the terminal b. The error flag-added zero data creation circuit 89 creates and outputs zero data with a flag (F) indicating that there is no redundant bit or data to be ignored in the decoding process in units of blocks. The data length adjustment bit 90 is an adjustment bit for continuing a block having an error and a block having no error. The switch 87 is controlled by the output of the zero data creation control circuit 86 to select the terminals a and b and supply them to the terminal b of the switch 88.

  The output of the delay circuit 85 is supplied to the terminal a of the switch 88. The delay circuit 85 is controlled by the zero data creation control circuit 86 to delay the output of the error correction circuit 93, thereby adjusting the timing with the output of the switch 87. The switch 88 is controlled by the zero data creation circuit 86 to select the terminals a and b, and outputs the output of the delay circuit 85 as it is for a block that does not have an error, and for a block that has an error, Instead of the output of the delay circuit 85, the output of the switch 87 is output.

  Next, the operation of the embodiment configured as described above will be described with reference to the explanatory diagram of FIG. 4A shows the combined data for one scan of the head at the time of 3 × speed reproduction, FIG. 4B shows the output of the switch 88, and FIG. 4C shows the zero data creation circuit 89 with an error flag. Output is shown. In the figure, the portion between G1, k1 'and G2, k2' and the portion between G2, K3 'and G3, k4' indicated by broken lines are unreproducible data and unusable due to many errors. Data or data that cannot be used because the synchronization signal is not reproduced.

  On the recording side, the reception demodulation circuit 81 demodulates the data input via the transmission path 80 and outputs it to the format conversion circuit 82 and the address creation circuit 83. By the format conversion circuit 82, the address generation circuit 83, and the multiplexing circuit 84, the frame number is added to the head of the frame data in the received data, and the address data is added to each block unit and supplied to the error correction encoder 62. . The parity data P is added to the received data by the error correction encoder 62, the synchronization signal S and the ID signal are added by the adder 63, and the data is given to the recording modulation circuit 65. The recording modulation circuit 65 performs modulation suitable for recording on the output of the adder 63 and applies the modulation signal to the magnetic head 67 via the recording amplifier 66 to record it on the magnetic tape 68.

  It is assumed that reproduction data shown in FIG. 4A is obtained from the magnetic head 67 by performing 3 × speed reproduction on the reproduction side. The reproduction data is supplied to the waveform equalization circuit 70 via the reproduction amplifier 69 and is subjected to waveform equalization. A synchronization signal is detected by the synchronization circuit 71 and demodulated by the demodulation circuit 72 in units of synchronization signals. The demodulated output is error-corrected by the error correction circuit 93 and output to the delay circuit 85.

  The error correction circuit 93 is shown by broken lines in FIG. 4A, that is, blocks G1, (k1 + 1) 'to G2, (k2-1)' and blocks G2, (k3 + 1) 'to G3, ( For k4-1) ′, an error flag is added and these address data are output to the zero data creation control circuit 86. The zero data creation control circuit 86 determines the delay amount of the delay circuit 85 from the error flag and the address data, and controls the switches 87 and 88. The switch 87 outputs the zero data (FIG. 4 (c)) of the block unit from the zero data creation circuit 89 with an error flag to the terminal b of the switch 88 at the error block timing. A data length adjustment bit for continuation with a block that has not been output is output to the terminal b of the switch 88.

  The output of the delay circuit 85 is supplied to the terminal a of the switch 88, and the switch 88 is controlled by the zero data creation control circuit 86 to select the terminals a and b. Thus, the switch 88 selects the delay circuit 85 during the period corresponding to the blocks G1, K0 ′ to G1, K1 ′ in FIG. 4A and outputs the demodulated output of the reproduced data as it is, to the blocks G1, k1 ′. During the period corresponding to the subsequent block G2, k2 ', the output of the switch 87 is selected and the zero data blocks G1, (k1 + 1)' to G2, (k2-1) 'with the error flag added are output. Further, a data length adjustment bit (shaded portion) for adjusting the recording rate is output by making the zero data block and the blocks G2, K2 'continuous. Next, the switch 88 selects the output of the delay circuit 85 during the period corresponding to the blocks G2, K2 'to G2, K3'. Next, the switch 88 selects the terminal b and outputs the zero data blocks G2, (K3 + 1) ′ to G3, (K4-1) ′ and the data length adjustment bits indicated by the diagonal lines. During the period corresponding to the next blocks G3, K4 'to G3, K5', the output of the delay circuit 85 is selected. Thus, zero data to which an error flag is added is inserted in the portion that is not reproduced as indicated by the broken line in FIG. 4A, and continuous sequential data is output from the switch 88.

  Thus, in this embodiment, before recording on the tape 68, an address is added to the data, and after demodulating the signal reproduced from the tape 68, an error flag is generated by the error correction circuit 93, and the address data is Ask. When data that is missing and becomes discontinuous is supplied to the decoding side, if the error block is replaced with zero data with an error flag based on the address data of the error block, the image data will be sequentially input The output of the switch 88 is supplied to a device that reproduces the image. On the image reproduction device (decoding means) side, original error handling processing based on the error flag added to the data, for example, no extra decoding of meaningless data even if decoding is performed, or decoding is performed. Skips the image restoration process, searches for the start address of the next block, re-recognizes data that can be decoded correctly, and controls to escape from error propagation. Is possible.

The block diagram which shows one Embodiment of the encoding side of the transmission system which concerns on this invention. The block diagram which shows one Embodiment of the decoding side of the transmission system which concerns on this invention. Explanatory drawing for demonstrating embodiment. Explanatory drawing for demonstrating operation | movement of embodiment. Explanatory drawing for demonstrating contrast with the position on the screen and the position on the recording track of a recording medium in a prior art example. Explanatory drawing which shows the relationship between the trace pattern at the time of 3 time speed reproduction | regeneration, and a reproduction envelope. Explanatory drawing which shows the structure of a recording / reproducing head. Explanatory drawing for demonstrating the structure of the reproduction | regeneration screen in a prior art example. H. 261 is an explanatory diagram for explaining a compression method of the H.261 recommendation. The block diagram which shows the recording side of the recording / reproducing apparatus which employ | adopted prediction encoding. Explanatory drawing for demonstrating a macroblock. Explanatory drawing which shows the data stream of the recording signal in the apparatus of FIG. The block diagram which shows the decoding side (reproduction | regeneration side) of a recording / reproducing apparatus. The block diagram for demonstrating the problem of a prior art example. The block diagram for demonstrating the problem of a prior art example. Explanatory drawing for demonstrating the problem of a prior art example.

Explanation of symbols

  82 ... Format conversion circuit, 83 ... Address creation circuit, 84 ... Multiple circuit

Claims (3)

In a transmission system for transmitting data from an encoding unit that performs compression encoding processing including variable length encoding to an input signal and outputs variable length encoded data to a decoding unit,
  Means for generating first transmission data composed of the variable length encoded data and a first identifier arranged in front of the data and indicating the identification of the data, and outputting the first transmission data to the decoding means;
  Means for generating second transmission data comprising fixed pattern data and a second identifier arranged before the fixed pattern data and indicating that the decoding means does not target the fixed pattern data;
  Means for generating third transmission data comprising variable length data;
  Means for outputting the second transmission data and the third transmission data in a gap generated in a stream of the transmission data when outputting the first transmission data as transmission data to the decoding means;
  A transmission system, wherein a transmission data stream including the first, second, and third transmission data is transmitted to the decoding means at a predetermined bit rate. 2. The transmission system according to claim 1, wherein address data indicating continuity is added to the transmission data transmitted continuously. In a transmission method for transmitting data from an encoding unit that performs compression encoding processing including variable length encoding to an input signal and outputs variable length encoded data to a decoding unit,
  Generating first transmission data composed of the variable-length encoded data and a first identifier arranged in front of the data and indicating the identification of the data, and outputting the first transmission data to the decoding unit;
  Generating second transmission data comprising fixed pattern data and a second identifier arranged before the fixed pattern data and indicating that the decoding means does not target the fixed pattern data;
  Generating third transmission data comprising variable-length data;
  A step of outputting the second transmission data and the third transmission data in a gap generated in a stream of the transmission data when outputting the first transmission data as transmission data to the decoding means;
  A transmission method comprising transmitting a stream of transmission data including the first, second, and third transmission data to the decoding means at a predetermined bit rate.

Images