JP3144236B2 - Surface treatment method for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface treatment method for a semiconductor element having a mesa structure in which a plurality of pn junctions are connected in series via electrodes.

[0002]

2. Description of the Related Art Generally, a semiconductor device has a plurality of p-type and n-type regions in a silicon chip. In a planar type semiconductor device where the bonding interface is exposed on the chip surface,
Normally, the pn junction interface is always protected by an oxide film, which is a surface protection film, from the start of the process to the completion of the process.
However, in a mesa-type semiconductor device, the pn junction interface is exposed on the side surface instead of the chip surface, and it is difficult to protect with an oxide film. Usually, at the final stage of the process, the side surface where the pn junction interface of the chip is exposed is exposed. After the surface treatment, a method of covering with a protective film is employed. This surface treatment is performed with a high-concentration acid or alkali solution in order to remove a mechanically distorted layer formed by a dicing saw during chip formation.

FIG. 4 is a sectional view showing a main part of a conventional mesa diode in which a pn junction is laminated via a metal layer 11 composed of electrode metals 4 and 5 and solder 6. FIG. 3A is a sectional view of a main part after machining. p ^{+ on} one of the n-type semiconductor wafers
Layer 3 and n ⁺ layer 2 formed on the other side by diffusion to form a pn structure of p ⁺ layer 3, n layer 1 and n ⁺ layer 2, and n ⁺ layer 2 and p ⁺ layer 3
The electrodes 4 and 5 are applied to the surface of the substrate to form a diode structure.
Are stacked in series via a solder 6, and then the wafer is cut with a dicing saw to form small stacked diode pieces, and lead wires 7 and 8 are connected to both sides of the mesa diode by soldering, respectively. And A mechanical strain layer 9 at the time of dicing is formed on the surface layer on the side surface where the pn junction of the stacked diode pieces is exposed. FIG. 2B is a sectional view of a main part after the diode piece of FIG. 1A is wet-etched with a high-concentration aqueous solution of potassium hydroxide. The n ⁺ layer 2 in contact with the electrode metal 4 has a wedge-shaped notch 10 formed by etching. However, lead wire 7
There is no wedge-shaped notch 10 at the interface of the n ⁺ layer 2 adjacent to.

[0004]

As described above, if there is a wedge-shaped missing portion 10, the diode pieces laminated from this portion are easily broken, and the current is reduced at the missing portion in terms of mechanical strength. This becomes a hindrance factor for reducing the area of the diode piece. An object of the present invention is to provide a method for treating a surface of a semiconductor device in which a wedge-shaped missing portion does not occur.

[0005]

According to the present invention, in order to achieve the above object, a p-type second semiconductor layer is provided on one main surface of an n-type first semiconductor layer, and a p-type second semiconductor layer is provided on the p-type second semiconductor layer. A metal layer is formed, a high-concentration n-type third semiconductor layer is formed on the other main surface of the n-type first semiconductor layer, and at least a semiconductor substrate on which the metal layer is formed on the high-concentration n-type third semiconductor layer is formed. In a semiconductor element piece formed by stacking and cutting two or more semiconductor elements in series, the side surface of the stacked structure including the n-type third semiconductor layer, the metal layer, and the p-type second semiconductor layer has at least ammonia water and hydrogen peroxide. Etching is performed using a mixed solution of water and water. Alternatively, the side surface of the laminated structure composed of the n-type third semiconductor layer, the metal layer, and the p-type second semiconductor layer is formed by applying the following equation between both ends of the laminate: V (V) = 0.059 × n × ΔpH (where n Is the number of layers in which the n-type third semiconductor layer, the metal layer, and the p-type second semiconductor layer are laminated as a set of layers, and ΔpH is the difference between the pH value of the electrolyte used and the pH value of the electrolyte where no problem occurs.) And wet etching using an electrolyte so as to apply a voltage that satisfies the following conditions.

[0006]

[Function] Metal layer and n⁺Silicon layer at interface with layer is wedge
Phenomenon that abnormal etching occurs as if
The following describes the mechanism. FIG. 5 shows that the metal layer 11 is the n-layer 1,
n⁺Layer 2 semiconductor and p⁺Sandwiched between layer 3 and n-layer 1 semiconductor
Enlarged sectional view of the indented part and the electron energy corresponding to each layer
FIG. 3 is a diagram schematically showing levels. FIG. 3A shows the order of each layer.
This is a diagram showing the positional relationship, with the metal layer 11 sandwiched between the left and right sides.
Each layer of the body is located. FIG. 2B shows the energy in the joined state.
Fig. 2 shows a Lugie level diagram, and a Fermi level 12 is indicated by a dotted line.
Do not apply voltage to the diode pieces without immersion in the electrolyte.
In the state, the Fermi level 12 is the n-layer 1, n⁺Layer 2, metal
Layers (including layers containing metal electrodes, solder layers and metal electrodes)
U) 11, p⁺Layer 3 and n-layer 1 have the same height.
ing. Also, a forbidden band on the semiconductor side at the interface with the metal layer 11.
Energy band 13 is n ⁺Layer 2 side, p⁺Layer 3 side
Bent so that the electron energy level becomes higher, and n
⁺On the layer 2 side, injection of electrons into the metal layer 11 is suppressed.
Is a non-ohmic junction, p⁺Holes are metal on layer 3 side
Ohmic junction freely injected into layer 11
You. When this system comes into contact with the electrolyte, the electrode potential E (electron energy)
At the potential expressed by the Luggy level
Is opposite to the potential) is expressed by Nernst's equation.
Therefore, it fluctuates.

[0007]

E = E ^O −2.3 kTpH (eV) (1) [where E ^O is the standard electrode potential before contacting the electrolyte, k
Is the Boltzmann constant, T is the absolute temperature of the system, and pH is the pH value of the electrolyte (strictly, it should be discussed not by the pH value but by the activity of ions in the electrolyte, but here the pH value is used for convenience). is there. When the system is immersed in an electrolyte having a high pH value, the electrode potential E decreases from the above equation, and when the system is immersed in an electrolyte having a low pH value, the electrode potential E increases.

FIG. 1C is a view showing a state where the system in the joined state shown in FIG. 1B is placed in an electrolyte having a high pH value. Due to the effect of the electrolyte, the electron energy level on the semiconductor side is relatively higher than that on the metal layer 11, and the Fermi level is
It bends so that the electron energy level on the semiconductor side at the interface with 1 becomes low. Therefore, on the n ⁺ layer 2 side, an ohmic junction in which electrons are freely injected into the metal layer 11 is changed, and silicon in the n ⁺ layer 2 near the metal layer 11 is dissolved in the electrolyte,
At this time, the electrons left in the n ⁺ layer 2 enter the metal layer 11, while the holes of the p ⁺ layer 3 enter the metal layer 11 through the ohmic junction, and some of the electrons and holes enter the metal layer 11.
Inside, and partly bonds with silicon dissolved in the electrolyte in contact with the metal layer 11.

FIG. 1D is a view showing a state in which the system in the joined state shown in FIG. 1B is placed in an electrolyte having a low pH value. The Fermi level 12 on the semiconductor side relative to the metal layer 11 is relatively lower than that of the metal layer 11 due to the influence of the electrolyte. Therefore, the energy band 13 on the semiconductor side at the interface with the metal layer 11 is n ⁺ layer 2 side, p
⁺ Both the layer 3 side and this system are not immersed in the electrolyte,
It is bent so that the electron energy level becomes higher,
Although the p ⁺ layer 3 side keeps ohmic properties, n ⁺
On the layer 2 side, non-ohmicity is enhanced, and injection of electrons from the n ⁺ layer 2 to the metal layer 11 is blocked. Therefore, the silicon of the n ⁺ layer 2 does not dissolve in the electrolyte. However, an electrolyte having a low pH value is an acid, but treatment with an acid has problems such as corrosion of a metal layer made of an electrode metal and a solder, and is difficult to employ. The following method is practical.

The same effect can be obtained by giving the p ⁺ layer 3 a high potential (lower electron energy level) with respect to the metal layer 11. At this time, the voltage V to be applied is estimated by the following equation using Nernst's equation as a guide.

[0011]

V = 0.059 × n × ΔpH (V) (2) [where n is the number of layers in which the n ⁺ layer 2 -metal layer 11 -p ⁺ layer 3 are stacked as one set of layers, ΔpH Is the difference between the pH value of the surface treatment liquid used and the pH value of the surface treatment liquid that does not cause any trouble. Further, unlike the above, there is a method of oxidizing silicon and removing the oxide film by etching. In this case, injection of electrons and holes into the metal film 11 is blocked by the oxide film, so that a similar effect is obtained.

[0012]

FIG. 1 is a sectional view showing a main part of a first embodiment of the present invention, before and after surface treatment. FIG.
2 shows a structural diagram of a main part of a stacked diode before surface treatment. After forming a diode composed of an n ⁺ layer 2 -n layer 1 -p ⁺ layer 3 on a silicon wafer and applying electrodes on the n ⁺ layer 2 and the p ⁺ layer 3 by Ni / Au electroless plating, Ten wafers are stacked and bonded to each other with a high-temperature solder, cut with a dicing saw to form stacked diode pieces, and lead wires 7 and 8 are attached to both ends of the diode pieces. By this cutting, a mechanical strain layer 9 is formed on the surface layer. FIG. 1B is a cross-sectional view of a main part of the diode after the surface treatment. The side surface of the diode piece in which the mechanical strain layer 9 in the state of FIG.
Surface treatment by wet etching is performed while immersing in an OH solution at 80 ° C. for 1.5 minutes while applying a voltage so that the p ⁺ layer 3 becomes a positive electrode and the n ⁺ layer 2 becomes a negative electrode on both sides of the diode piece. There is no wedge-shaped missing portion 10 (see FIG. 4B) unlike the conventional processing. FIG. 2 shows a jig and a diode 15 used for surface treatment, and FIG. 2A shows a jig 141 and 142 made of Pt for applying a simple voltage, with the lead wires 7 and 8 of the diode interposed therebetween. Figure (b)
Shows an enlarged view of a portion (A portion) sandwiching the lead wires 7 and 8. FIG. 3 is a diagram showing the polarity of the voltage applied between the lead terminals of the stacked diodes. At this time, the voltage V applied between the lead terminals is approximately 4 assuming that n = 10 and ΔpH = 7 from the equation (2).
V. As a result, the wedge depth L (see FIG. 4 (b)) generated in the no-voltage processing with the diode piece having a chip size of 450 μm square is reduced from 30 to 40 μm to almost 0.
μm.

A second embodiment of the present invention is a method using a mixture of aqueous ammonia and aqueous hydrogen peroxide as the surface treatment liquid. This liquid mixture is basically the same as that known as a cleaning liquid for wafers usually called SC-1. It is known that the mixed solution of the ammonia water and the hydrogen peroxide solution has an oxidizing action, an etching action and a cleaning action of the silicon substrate. In the case of NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5, an oxide film is instantaneously formed on the silicon substrate by about 5 ° and saturated at the thickness, but the etching is performed at about 1 nm / Proceed at a speed of minutes (90 ° C). That is, since the oxidation and etching coexist, the flow of electrons and holes into the metal film is intermittent, and the depth L of the wedge can be considerably reduced. Actually, as a result of immersion in the above surface treatment liquid for 3 minutes,
The same element characteristics as those of the related art were obtained, and the wedge depth L was 0.1 μm or less, which was a result having no practical problem.

[0014]

According to the present invention, an abnormal wedge-shaped side etch generated by a surface treatment for removing a mechanically strained layer of a mesa diode having a pn junction laminated is applied while applying a voltage to both ends of the diode. This can be prevented by performing surface treatment or changing the surface treatment solution from a conventional surface treatment solution to a mixed solution of aqueous ammonia and hydrogen peroxide. As a result, the stacked diode pieces did not break in the process after the surface treatment, and the process yield was improved. Also,
Since the mechanical strength can be ensured and the current-carrying cross-sectional area can be as large as the chip size, the chip size can be made smaller than before and equivalent performance can be obtained. As a result, a reduction in chip cost was achieved.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views of main parts of a stacked diode before and after surface treatment according to a first embodiment of the present invention. FIG. 1A is a cross-sectional view of main parts before surface treatment, and FIG. Cross-sectional view of main parts after processing

FIG. 2 is a diagram in which a diode is sandwiched in a jig for applying a voltage used when performing the surface treatment of the first embodiment.

FIG. 3 is a diagram illustrating polarities when a voltage is applied to a diode during surface treatment according to the first embodiment;

FIG. 4 is a cross-sectional view of a main part of a stacked diode before and after a conventional surface treatment. FIG.
FIG. 4B is a cross-sectional view of a main part after surface treatment.

FIG. 5 is an enlarged cross-sectional view of a stacked diode and a corresponding electron energy level diagram of each layer.

[Explanation of symbols]

Reference Signs List 1 n layer 2 n ⁺ layer 3 p ⁺ layer 4 electrode metal 5 electrode metal 6 solder 7 lead terminal 8 lead terminal 9 mechanically strained layer 10 wedge-shaped cutout 11 metal layer (electrode metal / solder / electrode metal) 12 Fermi level Position 13 Energy band of forbidden band 141 Voltage applying jig 142 Voltage applying jig 15 Diode L Depth of wedge

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kenki Okabayashi 1-1-1, Tanabe-Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (56) References JP-A-49-96676 (JP, A) JP-A-1-243435 (JP, A) JP-A-62-252141 (JP, A) JP-A-60-239028 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21 / 306,21 / 3063,21 / 308 H01L 21/304

Claims (2)

(57) [Claims] 1. A p-type second semiconductor layer is formed on one main surface of an n-type first semiconductor layer, and a metal layer is formed on the p-type second semiconductor layer. A semiconductor element formed by stacking at least two or more semiconductor substrates each having a high-concentration n-type third semiconductor layer formed on a surface thereof and a metal layer formed on the high-concentration n-type third semiconductor layer in series and cutting the same. In one of the above, the side surface of the laminated structure including the n-type third semiconductor layer, the metal layer, and the p-type second semiconductor layer is etched using at least a mixed solution of aqueous ammonia, aqueous hydrogen peroxide and water. Surface treatment method for a semiconductor element. 2. A p-type second semiconductor layer is formed on one main surface of the n-type first semiconductor layer, and a metal layer is formed on the p-type second semiconductor layer. A semiconductor element piece formed by laminating at least two or more semiconductor substrates each having a metal layer formed on the high-concentration n-type third semiconductor layer in series, and cutting the same. Wherein the side surface of the laminated structure including the n-type third semiconductor layer, the metal layer, and the p-type second semiconductor layer is defined by the formula V between both ends of the laminate.
(V) = 0.059 × n × ΔpH (where n is the number of layers in which an n-type third semiconductor layer, a metal layer, and a p-type second semiconductor layer are stacked as a set, and ΔpH is the pH of the electrolyte used. This is the difference between the value and the pH value of the electrolyte where no failure occurs.)
A wet etching process using an electrolyte so as to apply a voltage satisfying the following conditions.