JPH0897181A - Method for treating surface of semiconductor element - Google Patents

Abstract

PURPOSE: To eliminate breakage of a diode piece in the production step, reduce a chip area thereof and realize cost reduction while maintaining its characteristics by preventing abnormal etching that is caused during surface treatment of mesa-type diode with piled-up p-n joints. CONSTITUTION: A diode structure of n<+> layer 2-n layer 1-p<+> layer 3 is formed in a silicon wafer, and the wafer is piled up with electrode metals 4 and 5 in between by a solder 6, then the wafer is cut into diode pieces with a dicing saw. Further they are subject to surface treatment while a voltage is applied to them, or they are subject to surface treatment by a mixing liquid of ammonia solution and hydrogen peroxide.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface treatment method for a semiconductor device having a mesa structure in which a plurality of pn junctions are connected in series via electrodes.

[0002]

2. Description of the Related Art Generally, a semiconductor device has a plurality of p-type and n-type regions in a silicon chip. In the planar type semiconductor device of the type where the bonding interface is exposed on the chip surface,
Normally, from the process input to the process completion, the pn junction interface is always protected by an oxide film which is a surface protective film.
However, in the mesa type semiconductor device, the pn junction interface is not exposed on the surface of the chip but is exposed on the side surface, and it is difficult to protect it with an oxide film. Usually, at the final stage of the process, the exposed side surface of the pn junction interface of the chip is not used. After the surface treatment, a method of coating a protective film is adopted. This surface treatment is performed with a high-concentration acid or alkali solution in order to remove the mechanical strain layer formed by the dicing saw at the time of chip formation.

FIG. 4 shows a cross-sectional view of a main part of a mesa type diode in which a conventional pn junction is laminated via a metal layer 11 made of electrode metals 4 and 5 and solder 6. FIG. 3A shows a cross-sectional view of the main part after machining. p ^{+ on} one side of n-type semiconductor wafer
The layer 3 and the n ⁺ layer 2 on the other side are formed by diffusion to form the pn structure of the p ⁺ layer 3, the n layer 1 and the n ⁺ layer 2, and the n ⁺ layer 2 and the p ⁺ layer 3 are formed.
Electrode metals 4 and 5 are deposited on the surface of the device to form a diode structure, and two or more wafers having this diode structure (see FIG.
(In the case of one piece) are serially laminated via solder 6, and then the wafer is cut with a dicing saw to form small laminated diode pieces, and lead wires 7 and 8 are connected to both sides of each by solder to form a mesa diode. And A mechanical strain layer 9 at the time of dicing is formed on the surface layer on the side surface where the pn junction of the laminated diode pieces is exposed. FIG. 2B shows a cross-sectional view of essential parts after the diode piece of FIG. 1A is wet-etched with a high-concentration potassium hydroxide aqueous solution. A wedge-shaped missing portion 10 is formed by etching the n ⁺ layer 2 in contact with the electrode metal 4. However, lead wire 7
The interface of the n ⁺ layer 2 adjacent to is not provided with the wedge-shaped missing portion 10.

[0004]

As described above, if the wedge-shaped cutout portion 10 is present, the laminated diode piece is easily broken from this portion, and the current is narrowed at the cutout portion in terms of mechanical strength. This becomes an obstacle to the reduction of the area of the diode piece. SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a surface treatment method for a semiconductor device in which a wedge-shaped missing portion does not occur.

[0005]

In order to achieve the above-mentioned object, the present invention provides a second conductivity type semiconductor layer on one main surface of a first conductivity type semiconductor layer and a metal on the second conductivity type semiconductor layer. At least 2 semiconductor layers each having a high-concentration first-conductivity-type semiconductor layer formed on the other main surface of the first-conductivity-type semiconductor layer and a metal layer formed on the high-concentration first-conductivity-type semiconductor layer. In a semiconductor element piece formed by stacking at least one piece in series and cutting it, the surface strained layer on the side surface where the joint where the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are in contact is exposed is chemically treated. To remove. Further, it is effective to perform chemical treatment while applying a voltage to the junction between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. Further, the chemical treatment may be wet etching. Further, wet etching may be performed in a state of no voltage using at least a mixed solution of ammonia water, hydrogen peroxide water and water.

[0006]

[Function] Metal layer and n⁺The silicon layer at the interface with the layer is wedged
The phenomenon of abnormal etching as if there was
The mechanism for In FIG. 5, the metal layer 11 is an n-layer 1,
n⁺Layer 2 semiconductor and p⁺Sandwiched between layer 3 and n layer 1 semiconductor
Enlarged sectional view of the dented part and electron energy corresponding to each layer
FIG. 3 is a diagram schematically showing a level. The figure (a) shows the position of each layer
In the figure showing the positional relationship, the semiconductor layer is sandwiched between the left and right sides of the metal layer 11.
Each layer of the body is located. The figure (b) shows the energy in the joined state.
A Rougie level diagram is shown, and the Fermi level 12 is shown by a dotted line.
Do not apply voltage to the diode piece without immersing it in the electrolyte.
In the state, the Fermi level 12 is n layer 1, n⁺Layer 2, metal
Layers (including metal electrodes, solder layers and layers containing metal electrodes)
U) 11, p⁺Have the same height in each of the layers 3 and 1
ing. Also, the forbidden band on the semiconductor side at the interface with the metal layer 11
Energy band 13 of n ⁺Layer 2 side, p⁺With layer 3 side
It is bent so that the electron energy level becomes higher, and
⁺On the layer 2 side, it is possible to suppress injection of electrons into the metal layer 11.
Non-ohmic junction, p⁺On the layer 3 side, holes are metal
It is an ohmic junction that is freely injected into layer 11.
It When this system comes into contact with the electrolyte, the electrode potential E (electron energy
The potential expressed by the Lugie level for the ordinary positive charge
Is the opposite of the potential) is expressed by the Nernst equation,
Therefore, it fluctuates.

[0007]

## EQU1 ## E = E ^o -2.3 kTpH (eV) (1) [where E ^o is the standard electrode potential before coming into contact with the electrolyte, k
Is the Boltzmann constant, T is the absolute temperature of the system, and pH is the pH value of the electrolyte (strictly speaking, it should be discussed not by the pH value but by the activity of the ions in the electrolyte, but here it is the pH value for convenience). is there. When this system is dipped in an electrolyte having a high pH value, the electrode potential E decreases from the above formula. Conversely, when it is dipped in an electrolyte having a low pH value, the electrode potential E increases.

FIG. 3C is a diagram showing a state in which the system in the joined state of FIG. 1B is placed in an electrolyte having a high pH value. Due to the influence of the electrolyte, the electron energy level on the semiconductor side is relatively higher than that on the metal layer 11, and the Fermi level is on the metal layer 1.
Bend so that the electron energy level on the semiconductor side of the interface with 1 becomes low. Therefore, on the n ⁺ layer 2 side, an ohmic junction in which electrons are freely injected into the metal layer 11 is changed, silicon in the n ⁺ layer 2 near the metal layer 11 is dissolved in the electrolyte,
At that time, the electrons left in the n ⁺ layer 2 enter the metal layer 11, while the holes in the p ⁺ layer 3 enter the metal layer 11 through the ohmic junction, and some of the electrons and holes are in the metal layer 11.
It is bonded inside, and part of it is bonded to silicon dissolved in the electrolyte in contact with the metal layer 11.

FIG. 3D is a diagram showing a state in which the system in the bonded state of FIG. 1B is placed in an electrolyte having a low pH value. Due to the influence of the electrolyte, the Fermi level 12 is relatively low on the semiconductor side with respect to the metal layer 11, so that the energy band 13 on the semiconductor side at the interface with the metal layer 11 is on the n ⁺ layer 2 side, p side.
Compared to the case where the ⁺ layer 3 side is not immersed in the electrolyte,
Bent so that the electron energy level becomes higher,
The p ⁺ layer 3 side remains ohmic, but n ⁺
The non-ohmic property is enhanced on the layer 2 side, and the injection of electrons from the n ⁺ layer 2 to the metal layer 11 is blocked. Therefore, the silicon of the n ⁺ layer 2 will not dissolve in the electrolyte. However, although the electrolyte having a low pH value is an acid, the treatment with an acid has a problem that it corrodes the electrode metal and the metal layer made of solder, which makes it difficult to adopt. The following method is practical.

The above-mentioned phenomenon has the same effect by giving the p ⁺ layer 3 a high potential (reducing the electron energy level) to the metal layer 11. At this time, the applied voltage V is estimated by the following equation using the Nernst equation as a guide.

[0011]

[Formula 2] V = 0.059 × n × ΔpH (V) (2) [where n is the number of layers in which n ⁺ layer 2−metal layer 11-p ⁺ layer 3 are laminated as one set, ΔpH Is the difference between the pH value of the surface treatment liquid used and the pH value of the surface treatment liquid that does not cause any problems. Also, unlike the above, there is also a method of oxidizing silicon and removing the oxide film by etching. In this case, injection of electrons and holes into the metal film 11 is blocked by the oxide film, so that a similar effect is obtained.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cross-sectional view of a main portion of a laminated structure before and after the surface treatment of the first embodiment of the present invention. FIG.
[Fig. 3] shows a structural view of a main part of the stacked diodes before surface treatment. After forming a diode composed of n ⁺ layer 2 -n layer 1 -p ⁺ layer 3 on a silicon wafer and attaching electrodes on the n ⁺ layer 2 and p ⁺ layer 3 respectively by electroless plating of Ni / Au, Ten of the wafers are stacked and bonded to each other with high temperature solder, cut with a dicing saw to form a laminated diode piece, and lead wires 7 and 8 are attached to both ends of the diode piece. By this cutting, the mechanical strain layer 9 is formed on the surface layer. FIG. 3B shows a sectional view of the main part of the diode after the surface treatment. The side surface of the diode piece in which the mechanical strain layer 9 in the state of FIG.
A surface treatment is performed by wet etching while immersing in an OH liquid at 80 ° C. for 1.5 minutes while applying voltage such that the p ⁺ layer 3 serves as a positive electrode and the n ⁺ layer 2 serves as a negative electrode on both sides of the diode piece. The wedge-shaped missing portion 10 (see FIG. 4B) unlike the conventional processing is not generated. FIG. 2 shows a jig and a diode 15 used at the time of surface treatment, and FIG. 2 (a) shows a jig 141, 142 made of Pt for applying a simple voltage, in which the lead wires 7 and 8 of the diode are sandwiched. Figure and Figure (b)
Shows an enlarged view of a portion (A portion) sandwiching the lead wires 7 and 8. Between the lead terminals of the diodes, FIG. 3 is a diagram showing the polarities of the voltages applied between the lead terminals of the stacked diodes. At this time, the voltage V applied between the lead terminals is about 4 when n = 10 and ΔpH = 7 from the equation (2).
It was set to V. As a result, the depth L of the wedge (see FIG. 4 (b)) generated in the case of the voltage-free processing with the diode piece having the chip size of 450 μm □ is from 30 to 40 μm to almost 0.
could be made to be μm.

The second embodiment of the present invention is a method of using a mixed solution of ammonia water and hydrogen peroxide water as the surface treatment solution. This mixed solution is basically the same as what is generally known as SC-1 and is known as a wafer cleaning solution. It is known that this mixed solution of ammonia water and hydrogen peroxide water has an oxidizing action, an etching action and a cleaning action on the silicon substrate. In the case of NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5, the oxide film is instantly formed on the silicon substrate in an amount of about 5Å and saturates at that thickness, but the etching is about 1 nm / Proceed at a speed of 90 minutes. That is, since the system coexists with oxidation and etching, the inflow of electrons and holes into the metal film is intermittent, and the size of the depth L of the wedge can be made considerably small. In fact, as a result of soaking in the above surface treatment solution for 3 minutes,
The device characteristics that are the same as those of the conventional device were obtained, and the depth L of the wedge was 0.1 μm or less, which was a result with no practical problem.

[0014]

According to the present invention, the wedge-shaped abnormal side etching generated by the surface treatment for removing the mechanically strained layer of the mesa type diode in which the pn junction is laminated is applied while applying a voltage across the diode. This can be prevented by performing surface treatment or changing the surface treatment liquid from a conventional surface treatment liquid to a mixed liquid of aqueous ammonia and hydrogen peroxide. As a result, the laminated diode pieces did not break in the process after the surface treatment, and the process yield was improved. Also,
Since it is possible to secure mechanical strength and the current-carrying cross-sectional area can be as large as the chip size, the chip size can be made smaller than that of the conventional product, and equivalent performance can be obtained. As a result, the chip cost was reduced.

[Brief description of drawings]

1A and 1B are cross-sectional views of a main part of a stacked diode before and after surface treatment according to a first embodiment of the present invention, where FIG. 1A is a cross-sectional view of a main part before surface treatment, and FIG. Cross-sectional view of essential parts after processing

FIG. 2 is a diagram in which a diode is sandwiched in a jig for applying a voltage used when performing the surface treatment of the first embodiment.

FIG. 3 is a diagram showing the polarities when a voltage is applied to the diode during the surface treatment of the first embodiment.

FIG. 4 is a cross-sectional view of a main part of a stacked diode before and after conventional surface treatment, in which FIG. 4A is a cross-sectional view of the main part before surface treatment,
FIG. 3B is a cross-sectional view of the main part after the surface treatment.

FIG. 5 is an enlarged cross-sectional view of stacked diodes and corresponding electron energy level diagrams of each layer.

[Explanation of symbols]

1 n layer 2 n ⁺ layer 3 p ⁺ layer 4 electrode metal 5 electrode metal 6 solder 7 lead terminal 8 lead terminal 9 mechanical strain layer 10 wedge-shaped missing portion 11 metal layer (electrode metal / solder / electrode metal) 12 Fermi quasi Position 13 Forbidden energy band 141 Voltage application jig 142 Voltage application jig 15 Diode L Wedge depth

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenki Okabayashi 1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Fuji Electric Co., Ltd.

Claims (4)

[Claims] 1. A second conductivity type semiconductor layer is formed on one main surface of a first conductivity type semiconductor layer, and a metal layer is formed on this second conductivity type semiconductor layer, and the other main surface of the first conductivity type semiconductor layer is formed. A semiconductor element piece in which a high-concentration first-conductivity-type semiconductor layer is formed by stacking and cutting at least two semiconductor substrates in which metal layers are respectively formed on the high-concentration first-conductivity-type semiconductor layer 2. The method for surface treatment of a semiconductor device, wherein the surface strained layer on the side surface where the joint where the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are in contact is exposed is removed by a chemical treatment. 2. A second conductivity type semiconductor layer is formed on one main surface of the first conductivity type semiconductor layer, and a metal layer is formed on the second conductivity type semiconductor layer, and the other main surface of the first conductivity type semiconductor layer is formed. A semiconductor element piece in which a high-concentration first-conductivity-type semiconductor layer is formed by stacking and cutting at least two semiconductor substrates in which metal layers are respectively formed on the high-concentration first-conductivity-type semiconductor layer In, the surface strain layer on the side surface where the junction where the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are in contact is exposed, is applied to the junction between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. A method for surface treatment of a semiconductor element, characterized in that the surface is removed by a chemical treatment while applying. 3. The surface treatment method for a semiconductor device according to claim 1, wherein the chemical treatment is performed by using wet etching. 4. The surface treatment method for a semiconductor device according to claim 1, wherein the chemical treatment is performed using a mixed solution of at least ammonia water, hydrogen peroxide water and water.