JP3144199B2 - Skew correction circuit - Google Patents
Skew correction circuitInfo
- Publication number
- JP3144199B2 JP3144199B2 JP35279793A JP35279793A JP3144199B2 JP 3144199 B2 JP3144199 B2 JP 3144199B2 JP 35279793 A JP35279793 A JP 35279793A JP 35279793 A JP35279793 A JP 35279793A JP 3144199 B2 JP3144199 B2 JP 3144199B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- differential amplifier
- differential
- input
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、パターン信号のタイ
ミングを可変させ、タイミングスキューを補正する回路
についてのものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for varying the timing of a pattern signal and correcting timing skew.
【０００２】[0002]
【従来の技術】次に、従来技術によるスキュー補正回路
の構成を図２に示す。図２の１１と１２は差動増幅器、
１３は終端抵抗、１４はＤ／Ａ変換器である。図２で、
差動増幅器１１は反転入力端子と非反転入力端子にパタ
ーン信号を入力し、例えば非反転出力端子より差動増幅
器２の例えば非反転入力端子に接続するとともに、終端
抵抗３に接続する。また、Ｄ／Ａ変換器４の出力は差動
増幅器２の他の一方の例えば反転入力端子に接続する。2. Description of the Related Art FIG. 2 shows the configuration of a skew correction circuit according to the prior art. In FIG. 2, 11 and 12 are differential amplifiers,
13 is a terminating resistor, and 14 is a D / A converter. In FIG.
The differential amplifier 11 inputs a pattern signal to the inverting input terminal and the non-inverting input terminal. For example, the differential amplifier 11 connects the non-inverting output terminal to the non-inverting input terminal of the differential amplifier 2 and also connects to the terminating resistor 3. The output of the D / A converter 4 is connected to the other one of the differential amplifiers 2, for example, to an inverting input terminal.
【０００３】Ｄ／Ａ変換器１４は制御端子からの信号に
より出力電圧を可変させ、差動増幅器２の動作タイミン
グを変えることにより、差動増幅器２の出力パターンの
タイミングを可変させ、タイミングスキューを補正す
る。なお、図２では、例えば差動増幅器１１の非反転出
力端子の出力を差動増幅器１２の非反転入力端子に入力
しているが、それぞれ他の一方の反転側に接続しても良
い。The D / A converter 14 varies the output voltage according to the signal from the control terminal, and varies the operation timing of the differential amplifier 2 to vary the timing of the output pattern of the differential amplifier 2 and reduce the timing skew. to correct. In FIG. 2, for example, the output of the non-inverting output terminal of the differential amplifier 11 is input to the non-inverting input terminal of the differential amplifier 12, but they may be connected to the other inverting side.
【０００４】[0004]
【発明が解決しようとする課題】例えば、図２に示すよ
うに、差動増幅器１２の非反転入力側にパターンを入力
し、差動増幅器１２の反転入力側に入力する電圧レベル
を可変させて、動作タイミングを変化させる回路の場
合、電圧レベルを可変させるために、Ｄ／Ａ変換器を利
用しており、ロジック回路だけでは実現する事はできな
かった。この発明は、Ｄ／Ａ変換器を使用せず、ロジッ
ク回路のみで構成するスキュー補正回路の提供を目的と
する。For example, as shown in FIG. 2, a pattern is input to the non-inverting input side of the differential amplifier 12, and the voltage level input to the inverting input side of the differential amplifier 12 is varied. In the case of a circuit that changes the operation timing, a D / A converter is used to change the voltage level, and it cannot be realized by a logic circuit alone. SUMMARY OF THE INVENTION It is an object of the present invention to provide a skew correction circuit which does not use a D / A converter and includes only a logic circuit.
【０００５】[0005]
【課題を解決するための手段】この目的を達成するため
に、この発明は、反転入出力端子と非反転入出力端子を
備え、パターン信号を入力する第１の差動増幅器と、第
１の差動増幅器１の一方の出力を一方の入力端子に並列
に入力する複数の差動増幅器と、複数の差動増幅器の反
転出力と非反転出力を入力とし、複数の差動増幅器の出
力の１出力を選択して出力する選択回路９を備え、第１
の差動増幅器の一方の出力に終端抵抗７を接続するとと
もに、第１の差動増幅器１の他の一方の出力は、複数の
抵抗を直列に接続したものを終端抵抗とし、それぞれの
終端抵抗を介して複数の差動増幅器の他の一方の入力端
子に並列に入力する。また、第１の差動増幅器１の出力
端子からみた他の一方の出力側の複数の抵抗で形成され
る終端回路は、第１の差動増幅器１の出力端子からみた
一方の出力側の終端抵抗７の抵抗値及び終端電圧に等価
である。To achieve this object, the present invention provides a first differential amplifier having an inverting input / output terminal and a non-inverting input / output terminal for inputting a pattern signal, and a first differential amplifier. A plurality of differential amplifiers for inputting one output of the differential amplifier 1 to one input terminal in parallel; an inversion output and a non-inversion output of the plurality of differential amplifiers as inputs; A selection circuit 9 for selecting and outputting an output;
A termination resistor 7 is connected to one output of the differential amplifier, and the other output of the first differential amplifier 1 is connected to a plurality of resistors in series as a termination resistor. Are input in parallel to the other input terminals of the plurality of differential amplifiers. In addition, a termination circuit formed by a plurality of resistors on the other output side as viewed from the output terminal of the first differential amplifier 1 is a termination circuit on one output side as viewed from the output terminal of the first differential amplifier 1. It is equivalent to the resistance value of the resistor 7 and the termination voltage.
【０００６】[0006]
【作用】次に、この発明によるスキュー補正回路の構成
を図１に示す。図１の１〜６は差動増幅器、２は終端抵
抗、８Ａ〜８Ｆは終端抵抗、９は選択回路である。図１
で、差動増幅器１の非反転出力端子は、差動増幅器２〜
６の非反転入力端子に並列に接続されるとともに、終端
抵抗７に接続されており、差動増幅器２〜６の非反転入
力端子には、差動増幅器１の非反転出力波形がそのまま
印加される。FIG. 1 shows the configuration of a skew correction circuit according to the present invention. 1 to 6 are differential amplifiers, 2 is a terminating resistor, 8A to 8F are terminating resistors, and 9 is a selection circuit. FIG.
The non-inverting output terminal of the differential amplifier 1 is
6 is connected in parallel to the non-inverting input terminal of the differential amplifier 6, and is connected to the terminating resistor 7. The non-inverting output waveform of the differential amplifier 1 is applied to the non-inverting input terminals of the differential amplifiers 2 to 6 as they are. You.
【０００７】差動増幅器１の反転出力端子は、差動増幅
器４の反転入力端子に直接接続するとともに、差動増幅
器２の反転入力端子には、終端抵抗８Ｂ・８Ｃを介して
接続される。また、差動増幅器３の反転入力端子には、
終端抵抗８Ｃを介して接続し、差動増幅器５の反転入力
端子には、終端抵抗８Ｄを介して接続され、差動増幅器
６の反転入力端子には、終端抵抗８Ｄ・８Ｅを介して接
続する。The inverting output terminal of the differential amplifier 1 is directly connected to the inverting input terminal of the differential amplifier 4, and the inverting input terminal of the differential amplifier 2 is connected through terminating resistors 8B and 8C. The inverting input terminal of the differential amplifier 3
The differential amplifier 5 is connected via a terminating resistor 8D, the inverting input terminal of the differential amplifier 5 is connected via a terminating resistor 8D, and the inverting input terminal of the differential amplifier 6 is connected via terminating resistors 8D and 8E. .
【０００８】すなわち、差動増幅器４の反転入力端子に
は、差動増幅器１の反転出力波形がそのまま印加される
が、差動増幅器２・３の反転入力端子には、差動増幅器
１の反転出力電圧レベルより、（終端抵抗×その抵抗を
流れる電流）分だけ上にシフトした電圧レベルの波形が
印加され、差動増幅器５・６の反転入力端子には、差動
増幅器１の反転出力電圧レベルより（終端抵抗×その抵
抗を流れる電流）分だけ下にシフトした電圧レベルの波
形が印加される。That is, the inverted output waveform of the differential amplifier 1 is directly applied to the inverted input terminal of the differential amplifier 4, while the inverted input terminal of the differential amplifier 2 A waveform of a voltage level shifted upward by (terminal resistance × current flowing through the resistance) from the output voltage level is applied, and the inverted output voltage of the differential amplifier 1 is applied to the inverted input terminals of the differential amplifiers 5 and 6. A waveform of a voltage level shifted down by (terminal resistance × current flowing through the resistance) from the level is applied.
【０００９】次に、差動増幅器２〜６の各入力波形を図
３に示す。図３のアは差動増幅器２〜６の非反転入力端
子の入力波形であり、差動増幅器１の非反転出力の波形
である。図３のイ〜カは差動増幅器２〜６の反転入力波
形である。Next, the input waveforms of the differential amplifiers 2 to 6 are shown in FIG. FIG. 3A shows the input waveform of the non-inverting input terminals of the differential amplifiers 2 to 6, and the waveform of the non-inverting output of the differential amplifier 1. 3A to 3C show inverted input waveforms of the differential amplifiers 2 to 6. FIG.
【００１０】図３イは図１の差動増幅器２の反転入力の
波形であり、電圧レベルが一番高いので、図３アの非反
転入力波形と一番遅く交差するために、差動増幅器２の
非反転出力波形の立上りエッジは一番遅いタイミングで
出力される。図３カは図１の差動増幅器６の反転入力波
形であり、電圧レベルがいちばん低いので、非反転入力
波形と一番速く交差するために、差動増幅器６の非反転
出力波形の立上りエッジは、一番速いタイミングで出力
されることになる。FIG. 3A shows the waveform of the inverting input of the differential amplifier 2 of FIG. 1. Since the voltage level is the highest, it intersects the non-inverting input waveform of FIG. The rising edge of the second non-inverted output waveform is output at the latest timing. FIG. 3 shows the inverted input waveform of the differential amplifier 6 of FIG. 1. Since the voltage level is the lowest, the rising edge of the non-inverted output waveform of the differential amplifier 6 intersects quickly with the non-inverted input waveform. Will be output at the fastest timing.
【００１１】この時、差動増幅器１の出力端子からみた
反転出力側の終端抵抗８Ａ〜８Ｆで形成される終端回路
は、非反転出力側の終端抵抗７の抵抗値及び終端電圧に
等価になるような値を選ぶ。At this time, the terminating circuit formed by the terminating resistors 8A to 8F on the inverted output side as viewed from the output terminal of the differential amplifier 1 is equivalent to the resistance value and terminating voltage of the terminating resistor 7 on the non-inverted output side. Choose a value like
【００１２】差動増幅器２〜６の非反転出力端子及び反
転出力端子は選択回路９に入力し、制御端子に入力する
制御信号の状態により、いずれか１つを選択して出力す
る事により、差動増幅器２〜６の必要なタイミングの波
形を選択して出力し、スキューを補正する。The non-inverting output terminals and the inverting output terminals of the differential amplifiers 2 to 6 are input to a selection circuit 9, and one of them is selected and output according to the state of a control signal input to a control terminal. The waveforms at the necessary timings of the differential amplifiers 2 to 6 are selected and output, and the skew is corrected.
【００１３】例えば図１で、終端抵抗７を５０Ω、終端
抵抗８Ａを７２Ω、終端抵抗８Ｂ〜８Ｅをそれぞれ５
Ω、終端抵抗８Ｆを１２０Ωとすると、差動増幅器１か
らみた反転出力側の終端低抗は、ＧＮＤに対し８２Ωで
プルアップ、−５．２Ｖに対し１３０Ωでプルダウンと
なり、非反転出力端子の終端抵抗と同じように−２Ｖに
５０Ωの終端抵抗を接続したものと等価となる。For example, in FIG. 1, the terminating resistor 7 is 50Ω, the terminating resistor 8A is 72Ω, and the terminating resistors 8B to 8E are 5Ω each.
Assuming that Ω and the terminating resistor 8F are 120Ω, the terminating resistance on the inverted output side as viewed from the differential amplifier 1 is pulled up at 82Ω with respect to GND, pulled down with 130Ω with respect to −5.2V, and terminated at the non-inverted output terminal This is equivalent to connecting a termination resistance of 50 Ω to −2 V like a resistor.
【００１４】次に、差動増幅器２〜６の非反転出力波形
を図４のキ〜サに示す。図３で、差動増幅器２〜６の反
転入力波形の電圧レベルがそれぞれシフトするので、差
動増幅期２〜６の非反転波形と反転波形が交差し、出力
する時間が変化する。Next, non-inverted output waveforms of the differential amplifiers 2 to 6 are shown in FIG. In FIG. 3, since the voltage levels of the inverted input waveforms of the differential amplifiers 2 to 6 shift, respectively, the non-inverted waveforms and the inverted waveforms of the differential amplification periods 2 to 6 intersect and the output time changes.
【００１５】図４のキは、図３のアとイが交差して出力
された差動増幅器２の非反転出力波形であり、図４のサ
は図３のアとカの波形が交差して出力された差動増幅器
６の非反転出力波形である。差動増幅器２〜６の非反転
出力波形は図４のキ〜サの順に早く出力される。なお、
図１で、差動増幅器１の出力を入力する差動増幅器は５
つ使用しているが、必要に応じて増減しても良い。FIG. 4 (g) shows the non-inverted output waveform of the differential amplifier 2 which is output when the waveforms (a) and (b) of FIG. 3 intersect. The waveform of FIG. 7 shows a non-inverted output waveform of the differential amplifier 6 output from the differential amplifier 6. The non-inverted output waveforms of the differential amplifiers 2 to 6 are output earlier in the order of the keys in FIG. In addition,
In FIG. 1, the differential amplifier to which the output of the differential amplifier 1 is input is 5
Are used, but may be increased or decreased as needed.
【００１６】[0016]
【発明の効果】この発明によれば、第１の差動増幅器の
出力を入力する複数の差動増幅器を備え、第１の差動増
幅器の一方の出力は複数の差動増幅器の一方の入力端子
に並列に接続し、第１の差動増幅器の他の一方の出力に
は、複数の抵抗を直列に接続したものを終端抵抗とし、
それぞれの終端抵抗間にそれぞれの複数の差動増幅器の
他の一方の入力端子と接続しているので、複数の差動増
幅器の出力タイミングをそれぞれずらすことができ、選
択回路により選択して出力することにより、動作タイミ
ングを変化させるスキュー補正回路をロジック回路だけ
で構成させることができる。According to the present invention, there are provided a plurality of differential amplifiers for inputting the output of the first differential amplifier, and one output of the first differential amplifier is connected to one input of the plurality of differential amplifiers. Connected in parallel to the terminal, and the other output of the first differential amplifier is connected to a plurality of resistors in series as a terminating resistor.
Since each of the plurality of differential amplifiers is connected to the other input terminal of each of the plurality of differential amplifiers between the respective terminating resistors, the output timings of the plurality of differential amplifiers can be respectively shifted, and selected and output by the selection circuit. Thus, the skew correction circuit that changes the operation timing can be configured only by the logic circuit.
【図１】この発明によるスキュー補正回路の構成図であ
る。FIG. 1 is a configuration diagram of a skew correction circuit according to the present invention.
【図２】従来技術によるスキュー補正回路の構成図であ
る。FIG. 2 is a configuration diagram of a skew correction circuit according to the related art.
【図３】差動増幅器２〜６の各入力波形である。FIG. 3 shows input waveforms of differential amplifiers 2 to 6;
【図４】差動増幅器２〜６の非反転出力波形である。FIG. 4 shows non-inverted output waveforms of differential amplifiers 2 to 6;
１〜６ 差動増幅器 ７ 終端抵抗 ８Ａ〜８Ｆ 終端抵抗 ９ 選択回路 １１・１２ 差動増幅器 １３ 終端抵抗 １４ Ｄ／Ａ変換器 1-6 Differential amplifier 7 Terminating resistor 8A-8F Terminating resistor 9 Selection circuit 11 ・ 12 Differential amplifier 13 Terminating resistor 14 D / A converter
Claims (2)
え、パターン信号を入力する第１の差動増幅器(1) と、 第１の差動増幅器(1) の一方の出力を一方の入力端子に
並列に入力する複数の差動増幅器と、 前記複数の差動増幅器の反転出力と非反転出力を入力と
し、前記複数の差動増幅器の出力の１出力を選択して出
力する選択回路(9) を備え、 第１の差動増幅器(1) の前記一方の出力に終端抵抗(7)
を接続するとともに、第１の差動増幅器(1) の他の一方
の出力は、複数の抵抗を直列に接続したものを終端抵抗
とし、それぞれの終端抵抗を介して前記複数の差動増幅
器の他の一方の入力端子に並列に入力する事を特徴とす
るスキュー補正回路。A first differential amplifier (1) having an inverting input / output terminal and a non-inverting input / output terminal and receiving a pattern signal, and one output of the first differential amplifier (1) is connected to one of the first differential amplifier (1). A plurality of differential amplifiers that are input in parallel to input terminals; a selection circuit that receives an inverted output and a non-inverted output of the plurality of differential amplifiers as inputs, and selects and outputs one of the outputs of the plurality of differential amplifiers And a terminating resistor (7) connected to the one output of the first differential amplifier (1).
And the other output of the first differential amplifier (1) is connected to a plurality of resistors connected in series as a terminating resistor. A skew correction circuit characterized in that a signal is input in parallel to another input terminal.
前記他の一方の出力側の複数の抵抗で形成される終端回
路は、第１の差動増幅器(1) の出力端子からみた一方の
出力側の終端抵抗(7) の抵抗値及び終端電圧に等価であ
る請求項１に記載のスキュー補正回路。2. A termination circuit formed by a plurality of resistors on the other output side as viewed from the output terminal of the first differential amplifier (1), the output terminal of the first differential amplifier (1). 2. The skew correction circuit according to claim 1, wherein the skew correction circuit is equivalent to a resistance value and a termination voltage of one of the output-side termination resistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35279793A JP3144199B2 (en) | 1993-12-29 | 1993-12-29 | Skew correction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35279793A JP3144199B2 (en) | 1993-12-29 | 1993-12-29 | Skew correction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07198785A JPH07198785A (en) | 1995-08-01 |
| JP3144199B2 true JP3144199B2 (en) | 2001-03-12 |
Family
ID=18426507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35279793A Expired - Fee Related JP3144199B2 (en) | 1993-12-29 | 1993-12-29 | Skew correction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3144199B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6882204B2 (en) | 2003-04-25 | 2005-04-19 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with differential output driver circuit, and system for semiconductor integrated circuit device |
-
1993
- 1993-12-29 JP JP35279793A patent/JP3144199B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6882204B2 (en) | 2003-04-25 | 2005-04-19 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with differential output driver circuit, and system for semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07198785A (en) | 1995-08-01 |
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Legal Events
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |