JPH09325822A - Multistage voltage generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make voltage of various levels selectable by performing ON/OFF control of (n) pieces of switch elements and securing the overlapping of the ON period of an optional switch element and the ON period of another switch element or the ON periods of plural switch elements. SOLUTION: Six resistance elements 1 to 6 are connected in series to each other, so that five voltage levels V1 to V5 (n=5) are extracted. The number (n) of extracted voltage is equal to the number of nodes (N1 to N5) existing among the elements 1 to 6. In other words, it's enough to prepare (n-1) and (n+1) pieces of resistance elements at the least and the most respectively to extract (n) levels of voltage V1 to Vn after dividing the potential difference between voltage VCC and VSS. One of both ends of switch elements 7 to 11 is connected to each of nodes N1 to N5, and the other end of each of elements 7 to 11 is connected to each node serving as a voltage output node. The conduction can be turned on and off between both ends of each of elements 7 to 11 and also can be controlled by a control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-stage voltage generating circuit which divides a potential difference between two potentials to generate multi-stage voltages and selects and outputs one of the potentials.
More specifically, the present invention relates to an improved multi-stage voltage generation circuit that allows the output voltage to be selected from among voltages higher than the original number of multi-stage voltages.

[0002]

2. Description of the Related Art In a certain electronic circuit, a plurality of voltages having different potentials are internally generated, and one of the voltages is selected and used at a predetermined timing. A display voltage generating circuit, a digital-analog converter, a pseudo sine wave generating circuit, etc. of the digital liquid crystal display device are examples thereof.

For example, in a display voltage generating circuit of a liquid crystal display device, a multi-stage voltage generating circuit utilizing resistance voltage division is used to generate a voltage of a type corresponding to the number of display gradations. In this configuration, a plurality of resistors are connected in series between two potentials, and one of a plurality of different potentials appearing at each connection node is taken out through a switch element. One switch element is turned on (the other switch is turned off) according to the combination of bits, and a voltage corresponding to the display gradation is selected from a plurality of voltages and written in the liquid crystal pixel of the display panel.

[0004]

However, in such a conventional multi-stage voltage generating circuit, since the number of multi-stage voltages and the number of nodes are in a one-to-one correspondence, for example,
In the case of a liquid crystal display device, even if the number of bits of a digital input signal increases by at most 1 bit in response to the demand for multiple gradations, the number of resistors doubles, so the scale of the multi-stage voltage generation circuit must be increased. There was a problem that I could not escape.

Therefore, an object of the present invention is to make it possible to select a larger voltage without increasing the number of original voltages or the number of elements, thereby avoiding an increase in circuit scale.

[0006]

The above object is to connect one end of each of n switch elements to each of n (n> 1) nodes having different potentials, and to connect each of the n switch elements to each other. In a multi-stage voltage generation circuit configured by connecting an end to one voltage output node, a control means for controlling ON / OFF of the n switch elements is provided, and the control means is an ON period of any one switch element. And a control mode in which one switch element other than the one switch element or the ON period of a plurality of other switch elements are overlapped with each other.

This is because, when the above control mode is selected, there is a period in which at least two switch elements are both turned on, and at least two voltages transmitted via these switch elements reach any of the potentials of the n nodes. This is because a new voltage that does not match is created, and the number of selection voltages substantially increases by the new voltage.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are diagrams showing an embodiment of a multi-stage voltage generating circuit according to the present invention, which is an application to a resistance voltage dividing circuit. In FIG. 1, one of VCC and VSS is a high-potential, and the other is a low-potential DC voltage. Typically V
CC = positive potential voltage, VSS = ground potential voltage, but not limited to these potentials and polarities. Generally, a resistance voltage divider circuit is used to extract an arbitrary voltage between two “DC voltages”. For example, one voltage changes linearly or is non-linear (stepwise or exponential). It may be changed to. Alternatively, one or both of the two voltages may be alternating current. in this way,
The potentials, polarities, and waveforms of VCC and VSS vary depending on the application, but in this specification, for convenience of description, VCC = DC positive potential voltage and VSS = ground potential voltage are unified.

Reference numerals 1 to 6 are resistance elements connected in series between VCC and VSS. These resistance elements 1 to 6 are generally normal resistance elements having a specific resistance value, but they may be active elements such as transistors (for example, in the case of MOS transistors, channel on resistance is Use), and impedance including reactance and inductance may be used. The point is that the ratio of the resistance values (DC-like resistance value or AC-like resistance value) can be specified, and the physical shape and properties of the resistance element do not matter.

The number of resistance elements 1 to 6 depends on the number (n) of voltages taken out from the resistance voltage dividing circuit. In the example of FIG. 1, V
Six resistance elements 1 to 6 are connected in series in order to extract five voltages (n = 5) from 1 to V5. The voltage extraction number (n) is the same as the number of nodes (N1 to N5) between the resistance elements 1 to 6, respectively. Note that V1 =
In the case of VCC, N1 becomes VCC, and the resistance element 1
Does not need Or N when V5 = VSS
5 is VSS and does not require the resistive element 6. That is, in order to divide the potential difference between VCC and VSS to take out the n voltages V1 to Vn, it is sufficient to provide at least n−1 resistance elements and at most n + 1 resistance elements. Needless to say, even if the resistance element between the nodes (or between the node and the power supply) is a series circuit, a parallel circuit, or a series-parallel circuit composed of a plurality of resistance elements, it is always counted as one.

A switch element 7 is provided at each of the nodes N1 to N5.
1 to 11 are connected to each other, and the other ends of the switch elements 7 to 11 are commonly connected to one node (for convenience, N6) which also serves as a voltage output node. Here, the requirements necessary for the switch elements 7 to 11 are as follows:
It is possible to turn on and off the electrical continuity between both ends.
First, the on / off operation can be controlled by a predetermined control signal. For example, MOS transistors meet these requirements. This is because, in the MOS transistor, a current channel is formed (corresponding to ON) or not (corresponding to OFF) depending on the potential of the gate electrode. Since MOS transistors are suitable for integration, they are particularly preferable when they are incorporated in an LSI. However, when sufficient space can be secured such as when they are mounted on a printed circuit board or equipment, for example, a relay switch or a lead is used. A switch or the like may be used.

Control terminals (MO of each switch element 7 to 11)
If it is an S-transistor, the control circuit 1
The individual control signals S1 to S5 are input from No. 2. The relationship between the control signals S1 to S5 and the on / off states of the switch elements 7 to 11 is as follows for convenience of description. That is, when the control signal Si becomes H level, the switch element 6 + i corresponding to the control signal is turned “on”, and the control signal Si becomes L level.
Switch element 6 corresponding to the control signal when the level reaches
+ I shall be "off". It should be noted that i is a substitution character that represents a number (1 to 5) attached to the sign of the control signal. For example, focusing on the switch element 7 connected to the top node N1 in FIG. 1, i = 1 and the switch element code is 6 + 1 = 7.

In such a structure, when Si is set to the H level, the switch element 6 + i is turned on, and the voltage Vi of the node Ni is taken out from the node N6 via the switch element. OUT is an output voltage taken out from N6, and OUT = Vi in this case. Now the control signal S
It is considered that 1 to S5 are sequentially set to H level one by one, that is, when one control signal is at H level, the remaining control signals are all set to L level. FIG. 2A is a graph showing the potential change of OUT in this case. In the graph, OUT goes out as time passes.
The potential of is rising in steps. This is "S5" →
This is because the H level is set in the order of “S4” → “S3” → “S2” → “S1”. As described above, when only one control signal is always set to the H level, in other words, when only one switch element is always turned on, only the same number of potentials (V1 to V5) as the node can be obtained. By providing the following characteristic control modes, a potential higher than the number of nodes can be obtained.

The basic form of the control mode is as follows: "S5" → "S5_4" → "S4" → "S4_3" →
"S3" → "S3_2" → "S2" → "S2_1" →
It is transformed into "S1". The code with an underscore (_) expresses the overlap of the H level periods of the control signals on both sides thereof, and the actual control signal is the signal on both sides thereof (for example, in the case of S5_4, S
5 and S4).

During the period of S5_4, two control signals S
Both 5 and S4 become H level. Therefore, the two adjacent switch elements 10 and 11 are turned on, and the node N6 on the OUT side is connected to the two nodes N4 and N5 through these switch elements 10 and 11. Node N at this time
The potential of 6 (potential of OUT) is the potential of node N4 (V
4) and the potential (V5) of the node N5, that is, V5 <OUT <V4.

This will be verified. During the period of S5_4, the two switch elements 10 and 11 connected to the node N4 and the node N5 are both turned on, so that the node N4 and the node N5 (both ends of the resistance element 5) are short-circuited. Now, assuming that the values of the six resistance elements 1 to 6 between VCC and VSS are R [Ω], the combined resistance value between VCC and VSS in this case is the sum of the five resistance values excluding the resistance element 5. (5
R), VCC = positive potential, and VSS = ground potential (0 V), the potential of OUT in this case is given by the following equation. The subscript of OUT represents the period.

OUT _{(5_4)} = (VCC / 5R) × R Under the same condition, OU of S5 and S4 (in H level period)
When T is calculated, OUT ₍₅₎ = (VCC / 6R) × R OUT ₍₄₎ = (VCC / 6R) × 2R Here, for the sake of simplicity, if R = 1Ω and VCC = 6V, then OUT _{(5_4)} = (6 [V] / 5 [Ω]) x 1 [Ω] =
1.2 [V] OUT ₍₅₎ = (6 [V] / 6 [Ω]) × 1 [Ω] =
1.0 [V] OUT ₍₄₎ = (6 [V] / 6 [Ω]) × 2 [Ω] =
It is 2.0 [V], and it is understood that the relationship of OUT ₍₅₎ <OUT _{(5_4)} <OUT ₍₄₎ is satisfied. This relationship is between S4 and S3, S3
Between S2 and S2, and between S2 and S1. For reference, the actual voltage values calculated under the same conditions as above are listed. Between S4 and S3 OUT _{(4_3)} = (6 [V] / 5 [Ω]) × 2 [Ω] =
2.4 [V] OUT ₍₄₎ = (6 [V] / 6 [Ω]) × 2 [Ω] =
2.0 [V] OUT ₍₃₎ = (6 [V] / 6 [Ω]) × 3 [Ω] =
3.0 [V] ∴ OUT ₍₄₎ <OUT _{(4_3)} <OUT ₍₃₎ Between S3 and S2 OUT _{(3_2)} = (6 [V] / 5 [Ω]) × 3 [Ω] =
3.6 [V] OUT ₍₃₎ = (6 [V] / 6 [Ω]) × 3 [Ω] =
3.0 [V] OUT ₍₂₎ = (6 [V] / 6 [Ω]) × 4 [Ω] =
4.0 [V] ∴ OUT ₍₃₎ <OUT _{(3_2)} <OUT ₍₂₎ Between S2 and S1 OUT _{(2_1)} = (6 [V] / 5 [Ω]) × 4 [Ω] =
4.8 [V] OUT ₍₂₎ = (6 [V] / 6 [Ω]) × 4 [Ω] =
4.0 [V] OUT ₍₁₎ = (6 [V] / 6 [Ω]) × 5 [Ω] =
5.0 [V] ∴ OUT ₍₂₎ <OUT _{(2_1)} <OUT ₍₁₎ As described above, according to the present embodiment, the five potentials V1 to V5 of the nodes N1 to N5 are further OUT _{(5_4).} , OUT
One potential can be selected from a total of nine potentials including four potentials _{(4_3)} , OUT _{(3_2)} and OUT _{(2_1)} (see FIG. 2B). On the other hand, in order to generate nine potentials only by resistance voltage division, as described above, at most n +
One resistance element must be provided, where n =
Since it is 9, a maximum of 10 resistance elements are required. However, in this embodiment, the number of resistances is not increased at all, and a simple procedure of devising control of each switch element 7 to 11 is used. Thus, it is possible to provide a very useful technique that is not available in the prior art in that the number of selection voltages can be substantially increased.

Although the ON periods of two adjacent switch elements are overlapped in the embodiment, the present invention is not limited to this. The ON periods of three or more switch elements may overlap, or the ON periods of non-adjacent switch elements may overlap. The point is that the ON period of any one switch element and the ON period of one other switch element or a plurality of other switch elements other than the one switch element may be overlapped.

3 to 5 are views showing another embodiment of the multi-stage voltage generating circuit according to the present invention, which is an application to a pseudo sine wave generating circuit. It should be noted that the pseudo sine wave is a waveform used for a sufficient purpose (a tone generation circuit of a telephone terminal, etc.) (stepwise along a sine curve) as long as it is a waveform close to a sine wave even if it is not ideal. Waveform that changes to).

In FIG. 3, 20 is a differential amplifier.
The non-inverting input (+ input) of the differential amplifier 20 is connected to the ground potential, and the inverting input (− input) is seven switch elements 21.
Is connected to one end of ~ 27. The other ends of the respective switch elements 21 to 27 are connected to the respective nodes N11 to N17 of the resistance voltage dividing circuit 28 (however, the right end switch element 27
The other end is connected via the resistance element 29), and the resistance voltage dividing circuit 28 uses the resistance elements 30 to 35 connected between the nodes N11 to N17 and the node N11 at the left end for potential switching. The resistor element 37 is connected between the switch element 36 and the switch element 36.

Reference numeral 38 denotes a control circuit, and this control circuit 38
Generates the control signals S11 to S17 corresponding to the seven switch elements 21 to 27 and the control signal Sc corresponding to the potential switching switch element 36, respectively.
The corresponding control signal of each of the switch elements 21 to 27 is H.
Switch element 36 that turns on at the level and switches the potential
Selects a predetermined high potential voltage V _Hi when the control signal Sc is at the H level, and a predetermined low potential voltage V _Hi when the control signal Sc is at the L level.
Select _LOW .

In such a structure, for simplification of description, the resistance values of all the resistance elements are set to "R", and Sc
= S11 = H level and S12 to S17 = L level, the differential amplifier 20 of FIG. 3 uses the resistance value (R) of the resistance element 37 as the input resistance, and the series combined resistance value of the resistance element 30 to the resistance element 35 ( 6R) constitutes an inverting amplifier circuit having a feedback resistance, the amplification factor ANF is given by the following equation.

ANF = -6R / R = -6 Under the same conditions, if S12 to S17 are respectively set to H level, the amplification factor ANF in the case of Sc = S12 = H level is ANF = -5R / 2R = -2. 5 Amplification factor ANF in the case of Sc = S13 = H level is ANF = -4R / 3R≈1.333 Amplification factor ANF in the case of Sc = S14 = H level is ANF = -3R / 4R = -0.75 The amplification factor ANF in the case of Sc = S15 = H level is ANF = -2R / 5R = -0.4 The amplification factor ANF in the case of Sc = S16 = H level is ANF = -R / 6R≈-0.166 When Sc = S17 = H level, the amplification factor ANF is ANF = −R / 7R≈−0.142.

That is, the seven switch elements 21 to 27
By sequentially setting the H level to H level, the amplification factor ANF of the differential amplifier 20 can be changed from "-6 times" to "-0.142 times" in seven steps. The number of change stages of the ANF is the same as the number of switch elements and the number of nodes, and these numbers correspond to n described in the gist of the invention. Figure 4 (a)
Is a timing chart of the control signal when seven switch elements 21 to 27 are sequentially turned on (only one is turned on at all times), and FIG.
_SIN ) waveform example. The period of Sc = H level is a positive half cycle, and the period of Sc = L level is a negative half cycle. Focusing on the timing of S11 to S17, the next control signal (see, for example, the enlarged waveform of S12) rises at the same time as the fall of one control signal (see, for example, the enlarged waveform of S11). That is, the H level periods of adjacent control signals do not overlap. With such a control signal, since only the same number of ANF stages as the number of nodes (n) can be obtained, the step of the pseudo sine wave (V _SIN ) is large, and therefore the waveform is rough, for example, in the tone generation circuit of a telephone terminal. When applied, there is the inconvenience that harmonic noise other than the repetition frequency of the pseudo sine wave becomes noticeable. To solve this, simply increasing "n" is not preferable because it causes an increase in circuit scale.

Therefore, in this embodiment, as shown in FIG. 5 (a), the H level periods of the control signals corresponding to the two adjacent switch elements are overlapped with each other, thereby increasing the circuit scale. Without changing the number of stages of ANF change to "n" or more, a smooth pseudo sine wave (V _SIN ) with few steps is obtained. Incidentally, the value of each resistance element in the pseudo sine wave generation circuit must be an appropriate value corresponding to the spatial angle of the sine wave. An example of the appropriate value is shown below.

Resistance element 29 → 30 KΩ resistance element 30 → 2.6 KΩ resistance element 31 → 8.17 KΩ resistance element 32 → 14.966 KΩ resistance element 33 → 24.264 KΩ resistance element 34 → 38.319 KΩ resistance element 35 → 61.681 KΩ Resistance element 37 → 150 KΩ The pseudo sine wave generating circuit described above is an inverting amplification type, but the same applies to a non-inverting amplification type. 6 is an example of the non-inverting type, and the difference from FIG. 3 is that the potential switching switch element 36 is connected to the non-inverting input (+ input) of the differential amplifier 20, that is, the inverting of the differential amplifier 20. The seven nodes N of the resistance voltage dividing circuit 49 including the input (-input) through the n switch elements 21 to 27 and the n + 1 resistance elements 41 to 48.
11 to N17, and the resistance voltage dividing circuit 4
9 is connected to the output of the differential amplifier 20 and the ground potential. By overlapping the H level periods of the control signals S11 to S17, the amplification factor ANF can be set to "n" or more, and a smooth pseudo sine wave can be obtained as in the inverting type.

[0027]

According to the present invention, more voltages can be selected without increasing the number of original voltages or the number of elements. Therefore, for example, a display voltage generating circuit or a digital analog circuit of a digital liquid crystal display device can be selected. It is possible to provide a very useful technique that can easily achieve performance improvement of a converter, a pseudo sine wave generation circuit, or the like at low cost.

[Brief description of drawings]

FIG. 1 is a configuration diagram of one embodiment.

FIG. 2 is a waveform diagram of one embodiment.

FIG. 3 is a configuration diagram (1) of another embodiment.

FIG. 4 is a waveform diagram of another embodiment (without overlap).

FIG. 5 is a waveform diagram (with overlap) of another embodiment.

FIG. 6 is a configuration diagram (2) of another embodiment. It is.

[Explanation of symbols]

 N1 to N5: n nodes N6: voltage output node 7 to 11: switch element 12: control circuit (control means) N11 to N17: n number of nodes 21 to 27: switch element 38: control circuit (control means)

Claims (1)

[Claims] 1. One end of each of n switch elements is connected to each of n (n> 1) nodes having different potentials,
In a multi-stage voltage generation circuit configured by connecting the other ends of the n switch elements to one voltage output node, a control means for controlling ON / OFF of the n switch elements is provided, the control means comprising: A multi-step having a control mode for overlapping an ON period of any one switch element and an ON period of another switch element or a plurality of other switch elements other than the one switch element Voltage generation circuit.