JPH1038928A - Attenuation circuit for oscilloscope - Google Patents

Attenuation circuit for oscilloscope

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Publication number
JPH1038928A
JPH1038928A JP19054396A JP19054396A JPH1038928A JP H1038928 A JPH1038928 A JP H1038928A JP 19054396 A JP19054396 A JP 19054396A JP 19054396 A JP19054396 A JP 19054396A JP H1038928 A JPH1038928 A JP H1038928A
Authority
JP
Japan
Prior art keywords
base
emitter
potential
transistors
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19054396A
Other languages
Japanese (ja)
Inventor
Akihiro Tawara
明宏 田原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP19054396A priority Critical patent/JPH1038928A/en
Publication of JPH1038928A publication Critical patent/JPH1038928A/en
Pending legal-status Critical Current

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  • Networks Using Active Elements (AREA)
  • Amplifiers (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress a change in the frequency characteristic and the square- wave characteristic of an attenuation circuit by a method wherein a voltage to be applied to the resistance network of the attenuation circuit is controlled by a voltage detected by a resistance in which range information is weighted by every input from a control input terminal used to select an attenuation range and a base potential is not changed. SOLUTION: An analog input waveform signal is input an input terminal 1. Transistors Q1 to Q8 are composed of transconductance stages Q11/Q12 which are called cascode amplifiers and of an amplifier in which base connection stages are combined and whose high-frequency characteristic is excellent. Transistors Q9, Q10 are emitter followers which are separated from a next stage, transistors Q11 to Q16 are cascode amplifiers and emitter followers whose configuration is identical, and a potential which is raised by an NPN transistor at a previous stage is lowered to 0V. An operational amplifier U1 stabilizes the common-mode potential of an output in a DC feedback route.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、オシロスコープ等
の波形観測装置に使用する信号減衰回路に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal attenuating circuit used for a waveform observation device such as an oscilloscope.

【0002】[0002]

【従来の技術】オシロスコープの入力回路は一般に入力
部インピーダンス変換回路の前段に設けた高インピーダ
ンス系の第1減衰回路と、インピーダンス変換回路以降
に設けた第2減衰回路に分けており、それらの減衰比率
の組み合わせで例えば40mVから40Vフルスケール
といった広範囲の信号を扱えるようになっている。第1
減衰回路は扱う信号の電圧が高く、高耐圧であるためリ
レーなどメカニカルスイッチを使うのが一般的である。
その減衰比は例えば1:1/10:1/100である。
一方、第2減衰回路はインピーダンスも低く、扱う電圧
も低いので図2の例に示すようにトランジスタなどによ
って電子スイッチ化し原価低減をはかっている。図2は
第1減衰回路は図示していない。
2. Description of the Related Art Generally, an input circuit of an oscilloscope is divided into a high-impedance first attenuator provided before the input section impedance converter and a second attenuator provided after the impedance converter. A wide range of signals such as 40 mV to 40 V full scale can be handled by combining the ratios. First
Since the voltage of the signal to be handled is high and the breakdown voltage is high, the damping circuit generally uses a mechanical switch such as a relay.
The attenuation ratio is, for example, 1: 1/10: 1/100.
On the other hand, since the second attenuating circuit has a low impedance and a low voltage to be handled, as shown in the example of FIG. FIG. 2 does not show the first attenuation circuit.

【0003】この従来例の動作を説明する。The operation of this conventional example will be described.

【0004】入力信号VINはトランスコンダクタンス
段トランジスタQ1/Q2で電流に変換し、ベース接地
対Q7/Q8、Q5/Q6、Q3/Q4のいずれかのベ
ース電位を高く上げることによりONさせ、ONとなっ
たコレクタ間につながる抵抗R11からR16の和によ
って、トランジスタQ9/Q10間に発生する電圧を制
御するようにしている。
The input signal VIN is converted into a current by the transconductance stage transistors Q1 / Q2, and turned on by raising the base potential of one of the common base pairs Q7 / Q8, Q5 / Q6, Q3 / Q4. The voltage generated between the transistors Q9 / Q10 is controlled by the sum of the resistors R11 to R16 connected between the changed collectors.

【0005】本例では(reはトランジスタのエミッタ
の動抵抗を意味する)、 (1)制御電圧源VLAを5V、VLBを0V、VLC
を0Vに設定したときは利得Avは最大となり、 Av=Vc/VIN=(R11+R12+R13+R1
4+R15+R16)/(R5+R6+2re)=40
0/(39+re)となる。
In this example (re means the dynamic resistance of the emitter of the transistor): (1) The control voltage source VLA is 5 V, VLB is 0 V, VLC
Is set to 0 V, the gain Av becomes maximum, and Av = Vc / VIN = (R11 + R12 + R13 + R1
4 + R15 + R16) / (R5 + R6 + 2re) = 40
0 / (39 + re).

【0006】(2)制御電圧源VLAを0V、VLBを
5V、VLCを0Vに設定したときは利得Avは中間と
なり、 Av=Vc/VIN=(R12+R13+R14+R1
5)/(R5+R6+2re)=200/(39+r
e)となる。
(2) When the control voltage source VLA is set to 0 V, VLB is set to 5 V, and VLC is set to 0 V, the gain Av is intermediate, and Av = Vc / VIN = (R12 + R13 + R14 + R1
5) / (R5 + R6 + 2re) = 200 / (39 + r)
e).

【0007】(3)制御電圧源VLAを0V、VLBを
0V、VLCを5Vに設定したときは利得Avは最小と
なり、 Av=Vc/VIN=(R13+R14)/(R5+R
6+2re)=100/(39+re)となる。
(3) When the control voltage source VLA is set to 0 V, VLB is set to 0 V, and VLC is set to 5 V, the gain Av becomes minimum, and Av = Vc / VIN = (R13 + R14) / (R5 + R
6 + 2re) = 100 / (39 + re).

【0008】この様に、最大時の利得を1とすると順に
減衰する比率1:1/2:1/4の減衰回路を実現でき
る。出力電圧VCはエミッタフォロアQ9/Q10及び
次段の増幅回路Q11からQ16でを経て出力端子2、
3に伝達される。
As described above, when the maximum gain is set to 1, an attenuating circuit having a ratio of attenuating in order of 1: 1/2: 1/4 can be realized. The output voltage VC passes through the emitter follower Q9 / Q10 and the next-stage amplifier circuits Q11 to Q16, and is output to the output terminal 2,
3 is transmitted.

【0009】[0009]

【発明が解決しようとする課題】ところが、実際には従
来例は減衰比切り換え時に後段の増幅回路の動作点が変
動する。このため、レンジによって方形波特性の形が変
化するという欠点がある。 方形波特性の形が変化する
原因は次段のトランスコンダクタンス段Q11/Q12
の熱歪みが原因で、動作点により自己発熱の量が変化
し、熱的な正帰還量が変化することによって生じ方形波
応答の立ち上がり部分の形が変化することが原因であ
る。
However, actually, in the conventional example, the operating point of the subsequent amplifier circuit fluctuates when the attenuation ratio is switched. For this reason, there is a disadvantage that the shape of the square wave characteristic changes depending on the range. The cause of the change in the shape of the square wave characteristic is the transconductance stage Q11 / Q12 of the next stage.
The amount of self-heating changes depending on the operating point due to the thermal distortion of the element, and the shape of the rising portion of the square wave response caused by the change in the amount of thermal positive feedback changes.

【0010】また、増幅回路の動作点の変動の原因はベ
ース接地対Q7/Q8、Q5/Q6、Q3/Q4のどれ
がONするかで回路のバイアス電流Icの流れる経路が
変化するので、例えば減衰比1の時はQ9のベース電圧
は+8VからR17、R13、R12、R11を経てQ
7に流れ込む電流で決まるが、減衰比1/4の時はR1
7、R13のみを経てQ7に流れ込む電流で決まるので
電位は減衰比1の時の時に比べIc・(R11+R1
2)だけ上がってしまうからである。
The operating point of the amplifier circuit varies because the path through which the bias current Ic of the circuit flows varies depending on which of the common base pair Q7 / Q8, Q5 / Q6, and Q3 / Q4 is turned on. When the damping ratio is 1, the base voltage of Q9 is changed from + 8V through R17, R13, R12 and R11 to Q
7, but when the damping ratio is 1/4, R1
7 and R13 are determined by the current flowing into Q7 only through R13, so that the potential is Ic · (R11 + R1
This is because only 2) goes up.

【0011】[0011]

【課題を解決するための手段】本発明は、減衰レンジを
選択する制御入力端子からレンジ情報を各々の入力によ
って重み付けされた抵抗によって検出し、追加したエミ
ッタフォロア回路のベースで電圧変化として取り出し、
それによって減衰回路の抵抗網にかける電圧を制御し、
前記エミッタフォロアQ9/Q10のベース電位が変動
しないようにするトランジスタと抵抗回路網を追加した
ものである。
According to the present invention, range information is detected from a control input terminal for selecting an attenuation range by a resistor weighted by each input, and is taken out as a voltage change at a base of an added emitter follower circuit.
This controls the voltage applied to the resistor network of the damping circuit,
A transistor and a resistor network are added to prevent the base potential of the emitter followers Q9 / Q10 from fluctuating.

【0012】その結果、減衰比切り替え時に補正電圧が
加わるため、後段の増幅回路の動作点の変動を小さくで
き、回路の周波数特性、方形波特性の変動を小さくでき
る。
As a result, since the correction voltage is applied when the attenuation ratio is switched, the fluctuation of the operating point of the subsequent amplification circuit can be reduced, and the fluctuation of the frequency characteristic and the square wave characteristic of the circuit can be reduced.

【0013】[0013]

【発明の実施の形態】以下この発明の一実施例を図1に
より説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.

【0014】1はアナログ入力波形信号の入力端子、ト
ランジスタQ1からQ8までで構成する増幅器は一般に
カスコード増幅器と呼ばれるトランスコンダクタンス段
Q11/Q12とベース接地段を組み合わせた高周波特
性の優れた差動増幅器である。トランジスタQ9、Q1
0は次段との分離のためのエミッタフォロアでトランジ
スタQ11からQ16までは同じ構成のカスコード増幅
器とエミッタフォロアで前段のNPNトランジスタで上
昇した電位をこの例ではPNPトランジスタで構成する
ことで0Vに下げている。
Reference numeral 1 denotes an input terminal for an analog input waveform signal, and an amplifier composed of transistors Q1 to Q8 is a differential amplifier having excellent high frequency characteristics in which a transconductance stage Q11 / Q12 generally called a cascode amplifier and a grounded base stage are combined. is there. Transistors Q9, Q1
Numeral 0 is an emitter follower for separating from the next stage. Transistors Q11 to Q16 are cascode amplifiers of the same configuration, and the emitter follower is an emitter follower. In this example, the potential increased by the NPN transistor is reduced to 0V by using a PNP transistor in this example. ing.

【0015】オペアンプU1は出力のコモンモード電位
を安定化するために設けた直流帰還経路である。
The operational amplifier U1 is a direct current feedback path provided for stabilizing the output common mode potential.

【0016】図2の従来例で説明したとおり、減衰比
(利得)はベース接地トランジスタ対Q7/Q8、Q5
/Q6、Q3/Q4のいずれかONしたトランジスタの
コレクタ間につながる抵抗値によって切り換えるが、こ
のときの回路のバイアス電流Icは追加したトランジス
タQAから供給するようにした。このトランジスタQA
エミッタ電位はベースにつながる抵抗 RD、RA、R
B、RCで決まる。制御入力端子A、B、Cの論理レベ
ルにによってQAのベース電位が最適に上下するように
RA、RB、RCの値を選び、最終的にQ9/Q10の
ベース電位が変動しないようにする。
As described with reference to the conventional example of FIG. 2, the attenuation ratio (gain) is determined based on the pair of common base transistors Q7 / Q8 and Q5.
Switching is performed by a resistance value connected between the collectors of the transistors turned on in one of / Q6 and Q3 / Q4. At this time, the bias current Ic of the circuit is supplied from the added transistor QA. This transistor QA
The emitter potential is the resistance connected to the base RD, RA, R
Determined by B and RC. The values of RA, RB, and RC are selected so that the base potential of QA fluctuates optimally according to the logic levels of the control input terminals A, B, and C, so that the base potential of Q9 / Q10 does not fluctuate finally.

【0017】この値の決定には、RDとQ9/Q10の
ベース電位を決めて各状態についての連立方程式をたて
れば容易に求められる。
This value can be easily determined by determining the RD and the base potential of Q9 / Q10 and establishing simultaneous equations for each state.

【0018】すなわち、これらの関係は、次のように選
択すればレベル変動を最小限に抑えることができる。
That is, these relations can be minimized if the following changes are made.

【0019】以下、図1を参照して説明する。Hereinafter, description will be made with reference to FIG.

【0020】Vcが与えられ、変動しないものとす
る。
It is assumed that Vc is given and does not change.

【0021】VLA、VLB、VLCは通上0vで、
いずれか1つが5vとなることで減衰比が決まることは
先に説明したとおりである。
VLA, VLB and VLC are generally 0 V,
As described above, the attenuation ratio is determined by setting any one to 5v.

【0022】今その関係は、VLAが5vのとき、減衰
比1/1、VLBが5vのとき、減衰比1/2、VLC
が5vのとき、減衰比1/4とする。
Now, when VLA is 5V, the attenuation ratio is 1/1, when VLB is 5V, the attenuation ratio is 1/2, VLC
Is 5v, the attenuation ratio is 1/4.

【0023】Vc、R11、R12、R13は減衰比
とバイアス条件から与えられるものとする。この場合た
とえば、R11=100Ω,R12=50Ω,R13=
50Ω,各状態に対して、Vcが一定となるVxを求め
ると次のようになる。
Vc, R11, R12, and R13 are given from the attenuation ratio and the bias condition. In this case, for example, R11 = 100Ω, R12 = 50Ω, R13 =
When Vx at which Vc is constant is determined for each state of 50Ω, the following is obtained.

【0024】減衰比1/1のとき、VxA=Vc+(R
11+R12+R13)Ie+VBE=6.5v 減衰比1/2のとき、VxB=Vc+(R12+R1
3)Ie+VBE=6.0v 減衰比1/4のとき、VxC=Vc+R13Ie+VB
E=5.75v VLA、VLB、VLCが各々の状態のとき、この条件
を満たすように式を立てると、 減衰比1/1のとき、(Vcc−VxA)/RD=(V
xA−5v)/RA+VxA/RB+VxA/RC 減衰比1/2のとき、(Vcc−VxB)/RD=Vx
B/RA+(VxB−5v)/RB+VxB/RC 減衰比1/4のとき、(Vcc−VxC)/RD=(V
xC−5v)/RA+VxC/RB+VxC/RC 例えば、RA=1として、RB、RCを連立方程式を求
めればそれぞれの比が求められる。
When the attenuation ratio is 1/1, VxA = Vc + (R
11 + R12 + R13) Ie + VBE = 6.5v When the attenuation ratio is 1/2, VxB = Vc + (R12 + R1)
3) Ie + VBE = 6.0V When the attenuation ratio is 1/4, VxC = Vc + R13Ie + VB
E = 5.75v When VLA, VLB, and VLC are in each state, an equation is established to satisfy this condition. When the attenuation ratio is 1/1, (Vcc-VxA) / RD = (V
xA-5v) / RA + VxA / RB + VxA / RC When the attenuation ratio is 1/2, (Vcc-VxB) / RD = Vx
B / RA + (VxB-5v) / RB + VxB / RC When the attenuation ratio is 1/4, (Vcc-VxC) / RD = (V
xC-5v) / RA + VxC / RB + VxC / RC For example, if RA = 1 and simultaneous equations are obtained for RB and RC, the respective ratios can be obtained.

【0025】以下はその一例である。The following is one example.

【0026】1.5/1=1.5/RD+6.5/RB
+6.5/RC 2.0/1=6.0/RD+1.0/RB+6.0/R
C 2.25/1=5.75/RD+5.75/RB+0.
75/RC このようして、レベル変動を最小限に抑える。
1.5 / 1 = 1.5 / RD + 6.5 / RB
+ 6.5 / RC 2.0 / 1 = 6.0 / RD + 1.0 / RB + 6.0 / R
C 2.25 / 1 = 5.75 / RD + 5.75 / RB + 0.
75 / RC In this way, level fluctuations are minimized.

【0027】[0027]

【発明の効果】以上説明したように、本発明によれば、
減衰比切り替えた時の方形波特性の形が変化する不具合
を減らすことができ、高品位なオシロスコープを提供で
きる。
As described above, according to the present invention,
The problem that the shape of the square wave characteristic changes when the attenuation ratio is changed can be reduced, and a high-quality oscilloscope can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す回路図。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

【図2】従来例を示す回路図。FIG. 2 is a circuit diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

1 入力端子、Q1〜Q16 トランジスタ、R1〜R
D抵抗、C1〜C4 コンデンサ、A,B,C 減衰レ
ンジ切換制御入力端子、2,3 出力端子、VIN,V
LA,VLB,VLC 電圧源、I1,I2 電流源
1 input terminal, Q1-Q16 transistor, R1-R
D resistance, C1 to C4 capacitors, A, B, C attenuation range switching control input terminals, 2, 3 output terminals, VIN, V
LA, VLB, VLC voltage source, I1, I2 current source

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】入力信号を電圧電流変換するエミッタ接地
差動トランジスタ対と、 該エミッタ接地差動トランジスタ対の各々のコレクタに
エミッタを共通接続した複数個のベース接地トランジス
タ対と、 該複数個のベース接地トランジスタ対のベースに接続さ
れた制御電圧源と、 前記複数個のベース接地トランジスタ対の各コレクタ間
に接続され任意の抵抗比で互いに直列接続され、その中
間点を固定電位に接続した複数の抵抗よりなる抵抗網
と、前記抵抗網に接続された前記複数個のベース接地ト
ランジスタ対の内1対のベース接地のベース電位を選択
的に高電位にすることでコレクタ出力間の前記抵抗網の
抵抗値を選択し、伝達利得を制御する回路において、 前記抵抗網の前記固定電位に接続端にエミッタを接続し
たエミッタフォロア回路を設け、さらに該エミッタフォ
ロア回路のベースと前記ベース接地トランジスタ対の各
々のベースの間と固定電位間に抵抗を設け、利得設定に
応じて前記エミッタフォロア回路のエミッタ電位を制御
することを特徴とするオシロスコープ用減衰回路。
1. An emitter-grounded differential transistor pair for converting an input signal into a voltage and a current, a plurality of grounded base transistor pairs having an emitter commonly connected to each collector of the pair of grounded emitter differential transistors, and a plurality of grounded base transistor pairs. A control voltage source connected to the bases of the common-base transistor pair, a plurality of control voltage sources connected between the collectors of the plurality of common-base transistor pairs, connected in series with each other at an arbitrary resistance ratio, and connected at an intermediate point to a fixed potential; And a resistance network between collector outputs by selectively increasing a base potential of a pair of common bases among a plurality of common base transistor pairs connected to the resistance network. A circuit for selecting a resistance value and controlling a transmission gain, wherein an emitter follower circuit in which an emitter is connected to a connection terminal of the resistor network at the fixed potential. A resistor between the base of the emitter follower circuit and each base of the pair of grounded base transistors and a fixed potential, and controls an emitter potential of the emitter follower circuit according to a gain setting. Oscilloscope attenuation circuit.
JP19054396A 1996-07-19 1996-07-19 Attenuation circuit for oscilloscope Pending JPH1038928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19054396A JPH1038928A (en) 1996-07-19 1996-07-19 Attenuation circuit for oscilloscope

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19054396A JPH1038928A (en) 1996-07-19 1996-07-19 Attenuation circuit for oscilloscope

Publications (1)

Publication Number Publication Date
JPH1038928A true JPH1038928A (en) 1998-02-13

Family

ID=16259838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19054396A Pending JPH1038928A (en) 1996-07-19 1996-07-19 Attenuation circuit for oscilloscope

Country Status (1)

Country Link
JP (1) JPH1038928A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102053172A (en) * 2009-11-10 2011-05-11 北京普源精电科技有限公司 High-resistance broadband attenuation circuit and oscilloscope using same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102053172A (en) * 2009-11-10 2011-05-11 北京普源精电科技有限公司 High-resistance broadband attenuation circuit and oscilloscope using same

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