JP3142746U - Semiconductor mounting board - Google Patents

Semiconductor mounting board Download PDF

Info

Publication number
JP3142746U
JP3142746U JP2008002197U JP2008002197U JP3142746U JP 3142746 U JP3142746 U JP 3142746U JP 2008002197 U JP2008002197 U JP 2008002197U JP 2008002197 U JP2008002197 U JP 2008002197U JP 3142746 U JP3142746 U JP 3142746U
Authority
JP
Japan
Prior art keywords
screw
mounting
substrate
semiconductor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2008002197U
Other languages
Japanese (ja)
Inventor
俊男 嶋田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Okaya Electric Industry Co Ltd
Original Assignee
Okaya Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Okaya Electric Industry Co Ltd filed Critical Okaya Electric Industry Co Ltd
Priority to JP2008002197U priority Critical patent/JP3142746U/en
Application granted granted Critical
Publication of JP3142746U publication Critical patent/JP3142746U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Led Device Packages (AREA)

Abstract

【課題】半導体を実装する基板として熱伝導の良い金属を使用する場合において、ネジ等で固定される際に基板とネジとが好適に電気的に絶縁状態を維持することができる半導体実装基板を提供する。
【解決手段】半導体を実装し表面に絶縁層を形成した金属製基板2の、基板2をネジ6で固定するためのネジ取り付け穴5の周囲に設けられたネジ取り付け部7には、ネジ6の締め付け時にネジ6と絶縁層3間の取り付け力を緩衝し、絶縁層3を保護するための緩衝部8を形成してなる。
【選択図】図3
A semiconductor mounting board capable of suitably maintaining an electrically insulated state between a board and a screw when being fixed with a screw or the like when a metal having a good thermal conductivity is used as a board for mounting a semiconductor. provide.
A screw mounting portion 7 provided around a screw mounting hole 5 for fixing a substrate 2 with a screw 6 of a metal substrate 2 on which a semiconductor is mounted and an insulating layer is formed on the surface is provided with a screw 6. A buffer portion 8 for protecting the insulating layer 3 is formed by buffering the mounting force between the screw 6 and the insulating layer 3 when tightening.
[Selection] Figure 3

Description

本考案は、半導体を実装する基板として熱伝導の良い金属を使用する場合において、半導体実装基板をネジ等で固定する際に、基板とネジとを好適に電気的に絶縁した状態に維持することができる半導体実装基板に関するものである。   In the case where a metal having good thermal conductivity is used as a substrate on which a semiconductor is mounted, the present invention keeps the substrate and the screw suitably electrically insulated when the semiconductor mounting substrate is fixed with a screw or the like. The present invention relates to a semiconductor mounting substrate that can be used.

高出力のLED光源等にあっては、放熱性を考慮してそれを実装する基板として熱伝導の良い金属が使用されており、例えば鉄、アルミニウム等の導電性の金属を基板として用い、その表面を絶縁ガラスで被膜を形成した後、回路パターンを銀で印刷形成し、最後に回路パターンの保護する部分をマスクガラスで被覆することが行われている。そして、この半導体部品を取り付ける際に、基板のネジ取り付け部にそのままネジを締め付けていった場合には、表面のマスクガラスがひび割れて、本来電気的に絶縁状態を維持したい基板において、ネジと接触して導通してしまい実装する半導体部品に影響を及ぼす恐れがあった。そこで、基板のネジ取り付け部に絶縁ワッシャーを介在させた上でネジを用いて固定することが行われている。
特開2003−264919号公報
In a high-power LED light source or the like, a metal with good thermal conductivity is used as a substrate for mounting it in consideration of heat dissipation. For example, a conductive metal such as iron or aluminum is used as a substrate. After forming a film with insulating glass on the surface, a circuit pattern is printed and formed with silver, and finally a portion to be protected of the circuit pattern is covered with mask glass. And when attaching this semiconductor component, if the screw is tightened as it is to the screw mounting part of the board, the mask glass on the surface will crack, and it will contact the screw on the board where you want to maintain the electrical insulation originally. As a result, there is a risk of affecting the semiconductor components to be mounted. In view of this, an insulating washer is interposed in the screw mounting portion of the substrate and the fixing is performed using a screw.
JP 2003-264919 A

しかしながら、ネジで取り付ける際に絶縁ワッシャーを用いることは、部品点数が増加することに加え、絶縁ワッシャーを付け忘れてしまうという人為的ミスが発生する恐れもあり、そのため絶縁ワッシャーを用いることなく半導体部品をネジ止めする手段の実現が望まれていた。   However, the use of insulating washers when mounting with screws increases the number of components and may cause human error to forget to install insulating washers, so semiconductor components can be used without using insulating washers. It has been desired to realize a means for screwing.

そこで本考案にあっては、半導体を実装する基板として熱伝導の良い金属を使用する場合において、ネジ等で固定される際に基板とネジとが好適に電気的に絶縁状態を維持することができる半導体実装基板の提供を目的とする。   Therefore, in the present invention, when using a metal having good thermal conductivity as a substrate on which a semiconductor is mounted, the substrate and the screw can be suitably electrically insulated when being fixed with a screw or the like. An object of the present invention is to provide a semiconductor mounting substrate that can be used.

上記目的を達成するため、本考案の半導体実装基板は半導体を実装し表面に絶縁層を形成してなる金属製基板のネジ取り付け部には、ネジ締め付け時にネジと絶縁層間の取り付け力を緩衝し絶縁層を保護するための緩衝部を形成してなることを特徴とする。   In order to achieve the above object, the mounting board between the screw and the insulating layer is buffered at the screw mounting part of the metal board formed by mounting the semiconductor and forming the insulating layer on the surface. A buffer portion for protecting the insulating layer is formed.

また、緩衝部は、金属製基板のネジ取り付け部表面に形成された絶縁層と一体的に形成してなることを特徴とする。   The buffer portion is formed integrally with an insulating layer formed on the surface of the screw attachment portion of the metal substrate.

また、緩衝部は、基板に実装される回路パターンと同一の導電材料を用いて上記基板のネジ取り付け部に形成し、半導体実装工程中に回路パターン形成作業と同一の工程で形成してなることを特徴とする。   The buffer portion is formed on the screw mounting portion of the substrate using the same conductive material as the circuit pattern mounted on the substrate, and is formed in the same process as the circuit pattern forming operation during the semiconductor mounting process. It is characterized by.

緩衝部の表面は、回路パターン表面を被覆する絶縁被覆膜と同一の絶縁被覆膜で被覆し、半導体実装工程中に回路パターン表面被覆作業と同一の工程で形成してなることを特徴とする。   The surface of the buffer portion is coated with the same insulating coating film as that covering the circuit pattern surface, and is formed in the same process as the circuit pattern surface coating operation during the semiconductor mounting process. To do.

本考案の半導体実装基板によれば、半導体を実装する絶縁被膜で覆われた金属製の基板において、半導体を実装し表面に絶縁層を形成してなる金属基板のネジ取り付け部には、ネジ締め付け時にネジと絶縁層間の取り付け力を緩衝し絶縁層を保護するための緩衝部を形成することにより、緩衝部がネジと絶縁層の間の取り付け力(トルク)を緩衝する作用を発揮して、ネジがネジ取り付け部の絶縁被膜を破壊することなくネジを締め付けることができ、これにより基板とネジとが好適に電気的に絶縁状態を維持するができる。また、緩衝部を設けることにより、従来のように絶縁ワッシャー等緩衝用の部材を別途取り付け留必要がなく、取り付け忘れの心配もない。   According to the semiconductor mounting substrate of the present invention, in the metal substrate covered with the insulating film for mounting the semiconductor, the screw mounting portion of the metal substrate formed by mounting the semiconductor and forming the insulating layer on the surface is screw-tightened. By buffering the mounting force between the screw and the insulating layer and forming the buffering part to protect the insulating layer, the buffering part exerts the action of buffering the mounting force (torque) between the screw and the insulating layer, The screw can be tightened without destroying the insulating film of the screw mounting portion, and thus the substrate and the screw can be suitably electrically insulated. Further, by providing the buffer portion, it is not necessary to separately attach a buffer member such as an insulating washer as in the prior art, and there is no worry of forgetting to attach it.

緩衝部は、金属製基板のネジ取り付け部表面に形成された絶縁層と一体的に形成してなることにより、緩衝部がしっかりと形成されネジと絶縁層の間の取り付け力(トルク)を緩衝する作用を充分に発揮することができる。また、ネジ取り付け部表面に形成された絶縁層に厚みをもたせて緩衝部とした場合には、別途緩衝用の部材を設ける必要がなく、半導体実装基板製造工程を簡略化し製造コストを抑えることができる。   The buffer part is formed integrally with the insulating layer formed on the surface of the screw mounting part of the metal substrate, so that the buffer part is firmly formed and the mounting force (torque) between the screw and the insulating layer is buffered. It is possible to sufficiently exert the effect of In addition, when the insulating layer formed on the surface of the screw mounting portion is provided with a thickness so as to be a buffer portion, it is not necessary to provide a buffer member separately, which simplifies the semiconductor mounting substrate manufacturing process and reduces the manufacturing cost. it can.

緩衝部は、基板に実装される回路パターンと同一の導電材料を用いて上記基板のネジ取り付け部に形成してなることにより、半導体実装工程中に回路パターン形成作業と同一の工程で形成することが可能で、別途緩衝用の部材を設ける必要がなく、基板製造工程を簡略化し製造コストを抑えることができる。すなわち、回路パターンの印刷工程時に緩衝部を同時に印刷形成し、半導体実装基板の製造工程を簡略化することができる。   The buffer part is formed on the screw mounting part of the board using the same conductive material as the circuit pattern mounted on the board, so that it is formed in the same process as the circuit pattern forming work during the semiconductor mounting process. This eliminates the need for a separate buffer member, simplifies the substrate manufacturing process, and reduces the manufacturing cost. That is, the buffer portion can be printed and formed simultaneously during the circuit pattern printing process, thereby simplifying the manufacturing process of the semiconductor mounting substrate.

緩衝部の表面は、回路パターン表面を被覆する絶縁被覆膜と同一の絶縁被覆膜で被覆してなることにより、半導体実装工程中に回路パターン表面被覆作業と同一の工程で形成することが可能で、別途緩衝部に絶縁被膜部材を被覆する必要がなく、基板製造工程を簡略化し製造コストを抑えることができる。すなわち、回路パターンの表面絶縁被覆膜形成時に緩衝部を同時に絶縁被覆膜により被覆し、半導体実装基板の製造工程を簡略化することができる。   The surface of the buffer portion can be formed in the same process as the circuit pattern surface covering operation during the semiconductor mounting process by covering with the same insulating coating film as the insulating coating film covering the circuit pattern surface. This is possible, and it is not necessary to separately cover the insulating coating member on the buffer portion, thereby simplifying the substrate manufacturing process and reducing the manufacturing cost. That is, when the surface insulating coating film of the circuit pattern is formed, the buffer portion can be covered with the insulating coating film at the same time, thereby simplifying the manufacturing process of the semiconductor mounting substrate.

図1及び図2は、本実施例の半導体実装基板1を示し、2は効率的な放熱を必要とする高出力LED等を実装するのに好適な熱伝導性に優れた鉄、アルミニウム等の金属からなる基板、3は基板2を電気的に絶縁状態とするために基板表面全体を被覆するガラスからなる絶縁層、4は絶縁層3の上面に印刷形成された銀被膜からなる回路パターン、5は半導体実装基板1をネジ6で固定するためのネジ取り付け穴、7はネジ取り付け穴5の周囲に位置するネジ取り付け部であり、この部位には回路パターン4と同じ銀被膜を被着して緩衝部8を形成している。9は銀被膜の回路パターン4を保護するために回路パターン4に被着形成するとともに、緩衝部8をも被覆する耐候性を有する絶縁被覆膜としてのマスクガラスである。   FIG. 1 and FIG. 2 show a semiconductor mounting substrate 1 of the present embodiment, 2 is an iron, aluminum or the like excellent in thermal conductivity suitable for mounting a high-power LED or the like that requires efficient heat dissipation. A substrate made of metal, 3 is an insulating layer made of glass that covers the entire surface of the substrate in order to electrically insulate the substrate 2, and 4 is a circuit pattern made of a silver film printed on the upper surface of the insulating layer 3, Reference numeral 5 denotes a screw attachment hole for fixing the semiconductor mounting substrate 1 with the screw 6, and 7 denotes a screw attachment portion located around the screw attachment hole 5. The same silver coating as that of the circuit pattern 4 is applied to this portion. Thus, the buffer portion 8 is formed. Reference numeral 9 denotes a mask glass as an insulating coating film having a weather resistance and covering the buffer pattern 8 while being deposited on the circuit pattern 4 in order to protect the circuit pattern 4 having a silver coating.

この様な構成からなる半導体実装基板1において、図3に示すごとく、基板2のネジ取り付け穴5にネジ6を挿入して締め付けていくと、ネジ6頭部の裏面がネジ取り付け部7のマスクガラス9に当接した状態で、ネジ6は回転しつつマスクガラス9とその下の緩衝部8を圧縮付勢していく。そしてネジの締め付けトルクにより緩衝部8の銀被膜が圧縮されてその力を緩衝し、基板2の絶縁被膜3が損傷することなく、ネジ6の締め付けが既定の締め付けトルクに達し、基板2はネジ6と絶縁した状態を維持して好適に固定されることとなる。   In the semiconductor mounting substrate 1 having such a configuration, as shown in FIG. 3, when the screw 6 is inserted into the screw mounting hole 5 of the substrate 2 and tightened, the back surface of the head of the screw 6 is a mask of the screw mounting portion 7. The screw 6 compresses and urges the mask glass 9 and the buffer portion 8 therebelow while the screw 6 rotates while being in contact with the glass 9. The silver film of the buffer 8 is compressed by the tightening torque of the screw to buffer the force, and the screw 6 reaches the predetermined tightening torque without damaging the insulating film 3 of the substrate 2. It will be suitably fixed maintaining the state insulated from 6.

実際の半導体実装基板の緩衝部8の形成は、半導体実装基板1上に回路パターン5を印刷する工程で同時にネジ取り付け部7に緩衝部8を形成し、回路パターン8にマスクガラス9を被着形成する工程で同時に、緩衝部8に対してもマスクガラス9を被覆し、ネジ6と当接する面が絶縁体からなる緩衝部8を形成している。   In the actual formation of the buffer portion 8 of the semiconductor mounting substrate, the buffer portion 8 is simultaneously formed on the screw mounting portion 7 in the process of printing the circuit pattern 5 on the semiconductor mounting substrate 1, and the mask glass 9 is attached to the circuit pattern 8. At the same time as the forming step, the buffer glass 8 is covered with the mask glass 9, and the buffer portion 8 made of an insulator is formed on the surface in contact with the screw 6.

本実施例の半導体実装基板の他の実施例としては、半導体実装基に被覆する絶縁層3を厚く、例えば凸部形成し、ここを緩衝部8としてもよい。この場合においては、絶縁層3の形成の工程と同時に緩衝部8を形成することができる。   As another embodiment of the semiconductor mounting substrate of this embodiment, the insulating layer 3 covering the semiconductor mounting base is thick, for example, a convex portion is formed, and this may be used as the buffer portion 8. In this case, the buffer portion 8 can be formed simultaneously with the step of forming the insulating layer 3.

本実施例の半導体実装基板のさらなる他の実施例としては、ネジ取り付け部7に形成する緩衝部を上述した回路パターンと同じ銀被膜で形成するのではなく、合成樹脂等の絶縁物で形成するものである。緩衝部を絶縁物とすることで、ネジと緩衝部、そして緩衝部と基板の何れも確実に電気的絶縁状態を維持することができて好適である。ただし、上述した実施例のごとく、緩衝部を形成する工程として回路パターンの形成工程とは別の工程として追加することが必要となるものである。   As still another embodiment of the semiconductor mounting substrate of this embodiment, the buffer portion formed on the screw mounting portion 7 is not formed of the same silver film as the circuit pattern described above, but is formed of an insulator such as a synthetic resin. Is. By using the buffer portion as an insulator, it is preferable that the screw and the buffer portion, and the buffer portion and the substrate can reliably maintain the electrically insulated state. However, as in the above-described embodiment, it is necessary to add the step of forming the buffer portion as a step different from the step of forming the circuit pattern.

本考案の半導体実装基板を示す平面図である。It is a top view which shows the semiconductor mounting board of this invention. 本考案の半導体実装基板の要部断面を示す説明図である。It is explanatory drawing which shows the principal part cross section of the semiconductor mounting board of this invention. 本考案の半導体実装基板をネジで締める状態を示す説明図である。It is explanatory drawing which shows the state which fastens the semiconductor mounting board of this invention with a screw.

符号の説明Explanation of symbols

1 半導体実装基板
2 基板
3 絶縁被膜
4 回路パターン
5 ネジ取り付け穴
6 ネジ
7 ネジ取り付け部
8 緩衝部
9 マスクガラス
DESCRIPTION OF SYMBOLS 1 Semiconductor mounting board 2 Board | substrate 3 Insulation film 4 Circuit pattern 5 Screw attachment hole 6 Screw 7 Screw attachment part 8 Buffer part 9 Mask glass

Claims (4)

半導体を実装し表面に絶縁層を形成した金属製基板のネジ取り付け部には、ネジ締め付け時にネジと絶縁層間の取り付け力を緩衝し絶縁層を保護するための緩衝部を形成してなることを特徴とする半導体実装基板。   The screw mounting part of the metal substrate with the semiconductor layer mounted and the insulating layer formed on the surface shall be provided with a buffer part to buffer the mounting force between the screw and the insulating layer and protect the insulating layer when tightening the screw. A featured semiconductor mounting board. 緩衝部は、金属製基板のネジ取り付け部表面に形成された絶縁層と一体的に形成してなることを特徴とする請求項1記載の半導体実装基板。   2. The semiconductor mounting substrate according to claim 1, wherein the buffer portion is formed integrally with an insulating layer formed on the surface of the screw mounting portion of the metal substrate. 緩衝部は、基板に実装される回路パターンと同一の導電材料を用いて上記基板のネジ取り付け部に形成し、半導体実装工程中に回路パターン形成作業と同一の工程で形成してなることを特徴とする請求項1または2に記載の半導体実装基板。   The buffer portion is formed on the screw mounting portion of the substrate using the same conductive material as the circuit pattern mounted on the substrate, and is formed in the same process as the circuit pattern forming operation during the semiconductor mounting process. The semiconductor mounting substrate according to claim 1 or 2. 緩衝部の表面は、回路パターン表面を被覆する絶縁被覆膜と同一の絶縁被覆膜で被覆し、半導体実装工程中に回路パターン表面被覆作業と同一の工程で形成してなることを特徴とする請求項1乃至3のいずれかに記載の半導体実装基板。   The surface of the buffer portion is coated with the same insulating coating film as that covering the circuit pattern surface, and is formed in the same process as the circuit pattern surface coating operation during the semiconductor mounting process. The semiconductor mounting substrate according to claim 1.
JP2008002197U 2008-04-08 2008-04-08 Semiconductor mounting board Expired - Lifetime JP3142746U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008002197U JP3142746U (en) 2008-04-08 2008-04-08 Semiconductor mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008002197U JP3142746U (en) 2008-04-08 2008-04-08 Semiconductor mounting board

Publications (1)

Publication Number Publication Date
JP3142746U true JP3142746U (en) 2008-06-26

Family

ID=43292729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008002197U Expired - Lifetime JP3142746U (en) 2008-04-08 2008-04-08 Semiconductor mounting board

Country Status (1)

Country Link
JP (1) JP3142746U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010034346A (en) * 2008-07-30 2010-02-12 Sanyo Electric Co Ltd Circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010034346A (en) * 2008-07-30 2010-02-12 Sanyo Electric Co Ltd Circuit device

Similar Documents

Publication Publication Date Title
JP4279144B2 (en) Power semiconductor module
TW200503192A (en) Packaging component and semiconductor package
US20120092842A1 (en) Encapsulated circuit device for substrates having an absorption layer, and method for the manufacture thereof
JP3713088B2 (en) Display device
JP2009123812A (en) Electronic control device of heat radiating structure
JP4967701B2 (en) Power semiconductor device
JP3142746U (en) Semiconductor mounting board
JP4089300B2 (en) Substrate storage box
JP2016122787A (en) Electronic device and substrate
JP2002171087A (en) Electronic equipment
JP2002057483A5 (en)
JP2011009475A (en) Heat radiating component integrated circuit board
JP2593524Y2 (en) Hybrid IC
JP2004289017A (en) Resin sealed semiconductor device
JP2005228799A (en) Circuit structure and its manufacturing method
JP2003031978A (en) Control unit and manufacturing method therefor
JPH0121524Y2 (en)
JP2018113311A (en) Circuit structure
JPH0653681A (en) Coating method for resin of board mounted with electronic component and coating product
WO2005101490A3 (en) Component that is situated on a cooling fin
JP4026627B2 (en) Electronic control unit
KR950001199B1 (en) Thermal heating device
JP2000299577A (en) Structure and method for mounting printed wiring board
JPS6334933Y2 (en)
JPH01268183A (en) Metal base printed circuit board with radiation fin

Legal Events

Date Code Title Description
A623 Registrability report

Free format text: JAPANESE INTERMEDIATE CODE: A623

Effective date: 20080408

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110604

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120604

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130604

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140604

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term