JP3135620B2 - CRT device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

(Table of Contents) Industrial Application Field Conventional Technology (FIG. 8) Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action Embodiment (a) Description of One Embodiment (FIG. 2) To FIG. 7) (b) Description of Another Embodiment Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT device which displays display data at the center of a display screen even when a CRT unit having a predetermined timing is driven by a CRT control circuit having various characteristics.

[0003] With the development of personal computers in recent years, various compatible CRT units have been provided, and the specifications of drive signals have been determined. If such a CRT unit is used, the device can be constructed at a low cost, and a compatible CRT control circuit is correspondingly required.
Numerous products are provided in the form of an LSI or the like.

However, such compatible CRTs
The control circuit is a CRT unit having a predetermined timing circuit that is compatible with a predetermined timing circuit in which the timing of the video signal is not constant, is slightly different due to its circuit design, etc.
When displayed, it is not necessarily displayed at the center of the screen. Therefore, it is necessary to adjust the timing of the CRT unit according to the CRT control circuit used.

[0005]

2. Description of the Related Art FIG. 8 is an explanatory diagram of the prior art. FIG.
As shown in FIG. 1A, the CRT unit 2 has a deflection signal generating circuit 3 and a CRT tube 4, and receives a vertical synchronizing signal VS, a horizontal synchronizing signal HS, and a video signal VD of the CRT control circuit 1, and Deflection control is performed in synchronization with the synchronization signal VS and the horizontal synchronization signal HS to display the video signal VD.

As shown in FIGS. 8B and 8C, the vertical synchronizing signal VS has an interval of one frame (for example, 16.
7 ms), during which a number of horizontal synchronizing signals HS are provided, and one line of video signal VD exists between the horizontal synchronizing signals HS.

The time relationship of the video signal VD with the horizontal synchronization signal HS (period A in FIG. 8B) and the time relationship with the vertical synchronization signal are slightly different depending on the type of the CRT control circuit 1. I do.

[0008] Due to this difference, the video signal VD is displayed shifted in the horizontal direction and the vertical direction of the screen, and is not displayed in the center of the screen. For this reason, conventionally, a horizontal position adjustment volume and a vertical position adjustment volume are provided inside the CRT unit 2, and when combined with each CRT control circuit 1, the user is made to make adjustments and displayed in the center of the screen. Was like that.

In a CRT unit which is expected to be connected to several types of CRT control circuits 1, the volume position adjusted by the user is stored, called up and reproduced by a simple operation. I was

[0010]

However, the prior art has the following problems. Each time it is combined with an individual CRT control circuit 1,
Adjustment of the vertical position is required, and complicated and troublesome work is required.

It is necessary to provide a horizontal and vertical adjustment volume in the CRT unit 2, which makes the apparatus larger and more expensive. Therefore, an object of the present invention is to provide a CRT device capable of automatically performing horizontal and vertical position adjustments based on a signal from a CRT control circuit.

[0012]

FIG. 1 is a diagram illustrating the principle of the present invention. In the present invention , the vertical synchronizing signal VS and the horizontal synchronizing signal HS
And a CRT control circuit 1 for generating a video signal VD, and synchronizing with the vertical synchronizing signal VS and the horizontal synchronizing signal HS,
In the CRT device having the deflection signal generating circuit 3 for controlling the deflection of the T tube 4, the timing of the video signal VD from the vertical synchronizing signal VS and the horizontal synchronizing signal HS is measured. Signal VD
But it provided a control unit 5 for controlling the deflection signal generating circuit 3 to be displayed in the center of the screen of the CRT tube 4, the C
The RT control circuit 1 controls the horizontal synchronization signal without the vertical synchronization signal VS.
Signal HS and video signal VD, and the horizontal synchronization signal.
Generates vertical synchronization signal VS and video signal VD without signal HS
The control unit 5 determines that the vertical synchronization signal VS is
Is detected, the video signal is detected from the horizontal synchronization signal HS.
The timing of the signal VD is measured, and the horizontal synchronizing signal HS
Detects that there is no,該Bi de o from the vertical synchronization signal VS
The timing of the signal VD is measured .

[0013]

[0014]

[0015]

According to the present invention, the timing of the video signal VD from the vertical synchronization signal VS and the horizontal synchronization signal HS is measured,
According to the measured timing, the video signal VD
Since the control unit 5 for controlling the deflection signal generation circuit 3 is provided so as to be displayed at the center of the screen of the tube 4, any CRT
Even if a control circuit is combined, the position adjustment operation can be automated, and an adjustment volume or the like is not required.

[0016]

In the present invention, the CRT control circuit 1
Since a period for generating the horizontal synchronization signal HS and the video signal VD without the vertical synchronization signal VS and a period for generating the vertical synchronization signal VS and the video signal VD without the horizontal synchronization signal HS are provided, the control unit 5 The video signal VD is detected from the horizontal synchronization signal HS by detecting that the vertical synchronization signal VS is not present.
Is detected, the absence of the horizontal synchronization signal HS is detected, and the video signal VD is detected from the vertical synchronization signal VS.
Can be measured without the need for a signal line instructing special adjustment, and without changing the same interface as in the past.

[0018]

【Example】

(a) Description of one embodiment FIG. 2 is a block diagram of one embodiment of the present invention. In the figure, FIG.
And the same thing as what was shown in FIG. 8 is shown by the same symbol. In FIG. 2, the deflection signal generating circuit 3 includes a CR
The video signal VD from the T control circuit 1 is amplified by a video amplifier, output to the electron gun of the CRT tube 4, and a vertically increasing vertical deflection voltage is applied to the deflection yoke of the CRT tube 4 by a vertical timing signal, and the horizontal timing In response to the signal, a horizontally increasing horizontal deflection voltage is applied to the deflection yoke of the CRT tube 4.

Reference numeral 50 denotes a control circuit of the control unit 5, which is composed of a one-chip CPU and has a video signal VD shown in FIGS.
, And calculates the vertical and horizontal phase shift amounts. Reference numeral 51 denotes a vertical PLL circuit,
A horizontal PLL circuit 52 for generating a vertical timing signal with a set vertical phase shift amount with respect to S, and a horizontal PLL circuit for generating a horizontal timing signal with a set horizontal phase shift amount with respect to the horizontal synchronizing signal HS It is.

FIG. 3 is a processing flow chart of a CRT control circuit according to one embodiment of the present invention. Immediately after power-on, the CRT control circuit 1 performs initialization for determining horizontal and vertical frequencies and resolution. Next, the CRT control circuit 1 starts the video output of the screen display position correction data for displaying the entire effective screen solid.

The CRT control circuit 1 has a horizontal synchronizing signal HS
Is started for 60 cycles. Therefore, the horizontal adjustment period of the horizontal synchronization signal HS and the video signal VD, which does not include the vertical synchronization signal VS, lasts for 60 periods of the horizontal synchronization signal. As described later, the control circuit 50 of the CRT unit 2 uses the vertical adjustment signal. The absence of the synchronization signal VS is detected, and the horizontal phase shift is measured.

The CRT control circuit 1 has a vertical synchronizing signal VS
Is started, the horizontal synchronizing signal HS is stopped, and this is performed for 60 cycles. Therefore, the vertical adjustment period between the vertical synchronization signal VS and the video signal VD, which do not include the horizontal synchronization signal HS, lasts for 60 periods of the vertical synchronization signal.
The control circuit 50 of the CRT unit 2 detects the absence of the horizontal synchronizing signal HS and measures the vertical phase shift.

Then, the CRT control circuit 1 starts the horizontal synchronizing signal HS and proceeds to a normal business screen. In this way, the CRT control circuit 1 sets the horizontal adjustment cycle immediately after power-on, and in the horizontal adjustment, since the vertical synchronization signal VS is unnecessary, the CRT control circuit 1 does not insert the vertical synchronization signal VS as an identifier, and then sets the vertical adjustment cycle. In the vertical adjustment, since the horizontal synchronizing signal HS is unnecessary, the signal is output as an identifier without the horizontal synchronizing signal HS, and the normal operation starts.

FIG. 4 is a flowchart of a process on the CRT unit side in one embodiment of the present invention, FIG. 5 is a flowchart of a horizontal phase shift correcting process in one embodiment of the present invention, and FIG. 6 is a vertical phase shift correction in one embodiment of the present invention. FIG. 7 is a processing flow diagram, and FIG.

In FIG. 4, the control circuit 50 checks whether or not the horizontal synchronizing signal HS is active. If the horizontal synchronizing signal HS is not active, the control circuit 50 performs the vertical phase shift correction processing of FIG. 6 and returns. It is checked whether it is active. If it is not active, the horizontal phase shift correction processing of FIG.

Next, the horizontal phase shift correction processing will be described with reference to FIGS. The control circuit (hereinafter referred to as CPU) 50 detects the rising of the horizontal synchronization signal HS and starts a built-in timer.

The CPU 50 detects the rise of the video signal VD, stops the timer, and transfers the timer count value to the ThA register. As shown in FIG. 7A, the timer count value indicates a period ThA from the rise of the horizontal synchronization signal HS to the rise of the video signal VD.

Next, as shown in FIG. 7A, the CPU 50 determines the period Thc of the horizontal synchronizing signal HS which is known in advance.
, The period Thv of the video signal VD, and the period ThA described above.
From the above, (Thc-Thv-ThA) is calculated, and ThB is calculated.
Add to the contents of the register. (Thc-Thv-Th
FIG. 7A shows a period ThB from the rise of the video signal VD to the rise of the next horizontal synchronization signal HS, as shown in FIG. The CPU 50 checks whether or not the measurement has been performed 30 times. If the measurement has not been performed 30 times, the process returns to the step.

When the operation is performed 30 times, the ThB register stores the measured period ThB for 30 times.
The CPU 50 divides the content of the ThB register by 1/30 to obtain an average value, and then calculates the horizontal phase shift amount Δt,
(Thc / 2-Thv / 2-ThB), set in the horizontal PLL circuit 52, and return.

Next, the vertical phase shift correction processing will be described with reference to FIGS. 6 and 7B. The CPU 50 detects the rising of the vertical synchronization signal VS and starts a built-in timer.

The CPU 50 detects the rise of the video signal VD, stops the timer, and transfers the timer count value to the TvA register. As shown in FIG. 7B, the timer count value indicates a period TvA from the rise of the vertical synchronization signal VS to the rise of the video signal VD.

Next, as shown in FIG. 7B, the CPU 50 determines the period Tvc of the vertical synchronizing signal VS which is known in advance.
, The period Tvv of the video signal VD, and the period TvA described above.
From the above, (Tvc-Tvv-TvA) is calculated, and TvB
Add to the contents of the register. (Tvc-Tvv-Tv
FIG. 7A shows a period TvB from the fall of the video signal VD to the rise of the next vertical synchronization signal VS, as shown in FIG. 7B. The CPU 50 checks whether or not the measurement has been performed 30 times. If the measurement has not been performed 30 times, the process returns to the step.

When the operation is performed 30 times, the TvB register stores the measured period TvB for 30 times.
The CPU 50 divides the content of the TvB register by 1/30 to obtain an average value, and then calculates the vertical phase shift amount Δt by:
(Tvc / 2−Tvv / 2−TvB), the result is set in the vertical PLL circuit 51, and the process returns.

In this manner, the time from the vertical synchronizing signal VS and the horizontal synchronizing signal HS to the rise of the video signal VD is measured, and the vertical phase shift amount and the horizontal phase shift amount such that the video signal VD is displayed at the center of the screen. The phase shift amount is calculated and set as a set phase shift amount in each of the PLL circuits 51 and 52, and the phases of the vertical and horizontal timing signals (retrace signals) of the PLL circuits 51 and 52 are controlled. Is controlled to be displayed in the center of.

(B) Description of Other Embodiments In addition to the above-described embodiments, the present invention can be modified as follows. In the above-described embodiment, ThB and TvB are calculated. However, the phase shift amount may be calculated using ThA and TvA, and the measured ThA and TvA and the ideal values ThA and TvB may be calculated.
The phase shift amount may be calculated based on the difference from A.

Although the example of the same horizontal and vertical deflection frequencies has been described, the present invention may be applied to ones having different deflection frequencies. As described above, the present invention has been described with reference to the embodiments. However, various modifications can be made within the scope of the present invention, and these are not excluded from the scope of the present invention.

[0037]

As described above, according to the present invention, the following effects can be obtained. The timing of the video signal VD from the vertical synchronization signal VS and the horizontal synchronization signal HS is measured, and the deflection signal generation circuit 3 is controlled based on the measured timing so that the video signal VD is displayed at the center of the screen of the CRT tube 4. Since the control unit 5 is provided, the position adjustment operation can be automated with any combination of CRT control circuits, and the adjustment work is not required. In addition, since it can be realized without requiring an adjustment volume or the like, the unit can be configured at a low cost without increasing the size.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of one embodiment of the present invention.

FIG. 3 is a processing flowchart of a CRT control circuit according to an embodiment of the present invention.

FIG. 4 is a processing flowchart on the CRT unit side according to the embodiment of the present invention.

FIG. 5 is a flowchart illustrating a horizontal phase shift correction process according to an embodiment of the present invention;

FIG. 6 is a flowchart illustrating a vertical phase shift correction process according to an embodiment of the present invention;

FIG. 7 is an operation explanatory diagram of one embodiment of the present invention.

FIG. 8 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 CRT control circuit 2 CRT unit 3 deflection signal generation circuit 4 CRT tube 5 control unit 50 control circuit 51 vertical PLL circuit 52 horizontal PLL circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 1/00 G09G 1/16 H04N 3/227

Claims (1)

(57) [Claims] 1. A CRT control circuit (1) for generating a vertical synchronizing signal (VS), a horizontal synchronizing signal (HS), and a video signal (VD), and a vertical synchronizing signal (VS) and a horizontal synchronizing signal (HS). A CRT device having a deflection signal generating circuit (3) for controlling deflection of a CRT tube (4) in synchronization with the video signal (VD) from the vertical synchronization signal (VS) and the horizontal synchronization signal (HS). ) Is measured, and based on the measured timing, the video signal (VD)
Control unit for controlling the deflection signal generating circuit (3) to be displayed in the center of the screen of the RT tube (4) and (5) is provided, the CRT control circuit (1) is a vertical synchronization signal (VS)
No horizontal sync signal (HS) and video signal (VD)
And the vertical synchronization signal without the horizontal synchronization signal (HS)
(VS) and a period for generating the video signal (VD) are provided, and the control unit (5) checks that the vertical synchronizing signal (VS) is not present.
And the video signal is detected from the horizontal synchronizing signal (HS).
(VD) timing is measured, and the horizontal synchronizing signal (H
S), the absence of the vertical synchronization signal (VS) is detected.
Measuring the timing of the video signal (VD).
Characteristic CRT device.