JP2567120B2 - Horizontal sync signal measuring circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal synchronizing signal measuring circuit, and more particularly to a horizontal synchronizing signal measuring circuit which is important in the processing of synchronizing image signals.

[Conventional technology]

Conventionally, for example, in an IC circuit such as a CRT character generator that displays characters etc. at any position on the CRT, the CRT
The upper vertical position is set by measuring the number of horizontal synchronizing signals after the vertical synchronizing signal is generated.

FIG. 4 is a block diagram showing one of the conventional examples,
Arbitrary m T flip-flops TF1, TF2, ... A horizontal sync signal measuring circuit is shown in which a horizontal sync signal is connected to the input terminal I11.

FIG. 5 is a timing chart of the conventional horizontal synchronizing signal measuring circuit of FIG. 4 and shows the relationship between the horizontal synchronizing signal and the vertical synchronizing signal. In state A, that is, when the vertical synchronizing signal I11 rises before the horizontal synchronizing signal I12, the horizontal synchronizing signal I12 is counted. On the other hand, in the state B, the vertical synchronization signal I11
Is a time point after the horizontal synchronizing signal I12 rises, the measured value of the horizontal synchronizing signal I12, which is not counted, differs from that in the state A.

When the above-mentioned conventional example is used for a TV receiver, the relationship between the horizontal synchronizing signal and the vertical synchronizing signal is not limited to the state A as shown in FIG.

[Problems to be Solved by the Invention]

When such a horizontal sync signal measuring circuit is used as a detection circuit for detecting the position where characters are displayed on the CRT, there is a possibility that the display of characters for about 1H may shift during non-interlacing. State. Comparing the case of ideal non-interlace shown in FIG. 6 (a) and the case of realistic non-interlace shown in FIG. 6 (b), in the ideal case, the first field is also In the second field, both horizontal sync signals of A are counted as the first. On the other hand, in a realistic case, the horizontal sync signals of the first field and the second field are displaced from each other by the falling edge of the vertical sync signal, and therefore, the second field emits one b. It counts as eyes, and there is a difference of about 1H in the display position, and the display vibrates up and down, making it very unsightly.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to provide a horizontal synchronizing signal measuring circuit in which there is no output fluctuation due to the positional relationship between the vertical synchronizing signal and the horizontal synchronizing signal.

[Means for solving the problem]

According to the configuration of the present invention, in a horizontal sync signal measuring circuit that resets with a vertical sync signal and then measures the number of pulses of the horizontal sync signal, a horizontal count that is reset by the sync pulse of the horizontal sync signal and counts an arbitrary clock. A circuit, and a reference timing generation circuit that divides the horizontal count number into two from the output of the horizontal count circuit,
A dummy pulse generation circuit that outputs a pulse from the output of the horizontal count circuit to one area within two divisions, a register circuit that uses the output of the reference timing generation circuit as data, and a vertical synchronization signal as a clock, and the register circuit. And a horizontal / dummy switching circuit for switching between the horizontal synchronizing signal and the dummy pulse output of the dummy pulse generating circuit, and a horizontal synchronizing signal measuring circuit for resetting the vertical synchronizing signal using the output of the horizontal / dummy switching circuit as a clock. And a main body.

〔Example〕

The present invention will now be described in more detail with reference to the drawings.

FIG. 1 is a block diagram showing a horizontal synchronizing signal measuring circuit according to an embodiment of the present invention. In FIG. 1, this embodiment is
A horizontal count circuit 1 that is reset by the sync pulse of the horizontal sync signal I12 and counts an arbitrary clock I13
A reference timing generation circuit 2 for dividing the horizontal count number from the output of the horizontal count circuit 1 into two; and a dummy pulse generation circuit 3 for outputting a pulse from the output of the horizontal count circuit 1 into one area within the two divisions. A register circuit 5 which uses the reference timing generating circuit 2 as data and a vertical synchronizing signal I11 as a clock, and a horizontal circuit which switches the horizontal synchronizing signal I12 and the dummy pulse output of the dummy pulse generating circuit 3 by the output of the register circuit 5. / Dummy switching circuit 4 and a horizontal synchronizing signal measuring circuit body 6 for resetting the vertical synchronizing signal I11 using the output of the horizontal / dummy switching circuit 4 as a clock.

Next, the operation of the present invention will be described with reference to the timing chart of FIG. The horizontal counting circuit 1 resets the horizontal synchronizing signal I12 and counts it by an arbitrary clock I13, which is 0 to 15 in the example of FIG. The reference timing generation circuit 2 creates a timing so as to be divided into two regions A and B according to the count number of the horizontal count circuit 1, and divides the region B into a synchronization part of the horizontal synchronization signal I12 and a next synchronization part. The range from the position 2 to about 1/3 of the cycle of the horizontal synchronizing signal is from 8 to 12 in the example in the figure, and the others are area A.

The dummy pulse generation circuit 3 generates a dummy pulse before the synchronizing part of the horizontal synchronizing signal I12 in the area A by the count output of the horizontal counting circuit 1.

The register circuit 5 uses the output of the reference timing generation circuit 2 as data and captures it at the rising edge of the vertical synchronization signal I11.

If the output of the register circuit 5 indicates the area A, the horizontal / dummy switching circuit 4 outputs a dummy pulse in the next area A, and then switches to the horizontal synchronizing signal and outputs it.

If the region B is shown, the dummy pulse is not output in the next region A and the horizontal synchronizing signal is output.

The horizontal synchronizing signal measuring circuit 8 receives the vertical synchronizing signal I11 as it is as a reset input, and uses the output of the horizontal / dummy switching circuit 4 as a clock.

In FIG. 2, when the vertical synchronizing signal I11 rises before the horizontal synchronizing portion of the area A, the dummy pulse A is output to compensate and measure the horizontal synchronizing portion of the area A.

In the next step, the vertical synchronizing signal I11 rises after the horizontal synchronizing portion in the area A, and in this case also, the horizontal synchronizing portion is compensated by the dummy pulse A. Then, when the vertical synchronizing signal I11 rises in the area B, the compensation by the dummy pulse is not performed,
The horizontal synchronizing signal I12 becomes a.

This embodiment is particularly effective when used in a device for displaying characters and the like on a CRT, and when the vertical synchronizing signal is arbitrarily input with respect to the horizontal synchronizing signal, the nearest horizontal synchronizing portion is set to 1
Count as a claw.

For example, as shown in FIG.
Even when the horizontal sync signals of the field A and the field A of the second field are offset from each other by the rising edge of the vertical sync signal, both the horizontal sync signals of the field A are counted as the first shot. As a result, the difference in the display position due to the measurement error of the horizontal sync signal measuring circuit is reduced to less than 1 / 2H, and the vertical vibration is inconspicuous and stable display can be obtained.

〔The invention's effect〕

As described above, according to the present invention, since the counting is performed by the dummy pulse, the display position difference is H /
There is an effect that vertical vibration is negligible.

[Brief description of drawings]

FIG. 1 is a block diagram of a horizontal synchronizing signal measuring circuit according to an embodiment of the present invention, FIGS. 2 and 3 are timing charts showing the operation of the embodiment of FIG. 1, and FIG. 4 is a conventional example. The block diagram showing the horizontal synchronizing signal measuring circuit of FIG. 5, FIG. 5, FIG. 6 (a), and FIG. 6 (b) are all timing charts showing the operation of the conventional method. 1 ... Horizontal count circuit, 2 ... Reference timing generation circuit, 3 ... Dummy pulse generation circuit, 4 ... Horizontal / dummy switching circuit, 5 ... Register circuit, 6 ... Horizontal synchronization signal measurement circuit, TF1 to m ...... Toggle flip-flop with reset, I11 …… Vertical sync signal, I12 …… Horizontal sync signal, I13 …… Clock.

Claims (1)

(57) [Claims] 1. A horizontal synchronizing signal measuring circuit which resets with a vertical synchronizing signal and measures the number of pulses of the horizontal synchronizing signal thereafter, which counts an arbitrary clock which is reset by the synchronizing pulse of the horizontal synchronizing signal. A reference timing generation circuit for dividing the horizontal count number from the output of the horizontal count circuit into two; a dummy pulse generation circuit for outputting a pulse from the output of the horizontal count circuit into one area within the two divisions; A register circuit that uses the output of the timing generating circuit as data and a vertical synchronizing signal as a clock; a horizontal / dummy switching circuit that switches between the horizontal synchronizing signal and the dummy pulse output of the dummy pulse generating circuit according to the output of the register circuit; / Vertical synchronization signal using the output of the dummy switching circuit as a clock Horizontal synchronizing signal measurement circuit comprising the horizontal synchronizing signal measurement circuit body to reset.