JP3130826B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3130826B2
JP3130826B2 JP10436797A JP10436797A JP3130826B2 JP 3130826 B2 JP3130826 B2 JP 3130826B2 JP 10436797 A JP10436797 A JP 10436797A JP 10436797 A JP10436797 A JP 10436797A JP 3130826 B2 JP3130826 B2 JP 3130826B2
Authority
JP
Japan
Prior art keywords
semiconductor element
package
package body
semiconductor device
main body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10436797A
Other languages
Japanese (ja)
Other versions
JPH10294412A (en
Inventor
かおり 西岡
Original Assignee
九州日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 九州日本電気株式会社 filed Critical 九州日本電気株式会社
Priority to JP10436797A priority Critical patent/JP3130826B2/en
Publication of JPH10294412A publication Critical patent/JPH10294412A/en
Application granted granted Critical
Publication of JP3130826B2 publication Critical patent/JP3130826B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the manufacturing cost, entire thickness, and external size of a semiconductor device and, at the same time, to improve the productivity of the device. SOLUTION: A package main body 1 is formed in a molded article having a recessed section 11 for housing semiconductor element at the central part. A semiconductor element 2 is bonded and fixed to the recessed section 11 of the main body 1. Lead wires 4 having prescribed shapes are respectively connected to the electrode pads 21 of the element 2. In an insulating coating section 5 is provided to cover the surface of the main body 1 in the peripheral area of the recessed section and the sections from the front ends of the connecting sections between the lead wires and pads 21 to the peripheral area of the recessed sections 11.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特に半導体素子を内部に封入するパッケージを備えた半
導体装置に関する。
The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a package for enclosing a semiconductor element therein.

【0002】[0002]

【従来の技術】従来のこの種の代表的な半導体装置とし
ては、半導体素子を直接内部にモールド封入する樹脂封
止型のものや、セラミックパッケージに封入するセラミ
ックパッケージ型のものなどがある。
2. Description of the Related Art Conventional typical semiconductor devices of this type include a resin-sealed type in which a semiconductor element is directly molded and sealed therein, and a ceramic package type in which a semiconductor element is sealed in a ceramic package.

【0003】樹脂封止型の半導体装置の一例(第1の
例)を図2に示す。
FIG. 2 shows an example (first example) of a resin-sealed semiconductor device.

【0004】この第1の例の半導体装置は、素子搭載部
41及び複数のリードワイヤ4aから成るリードフレー
ムと、このリードフレームの素子搭載部41に第1の面
を接着固定し第2の面に複数の電極パッド21を備えた
半導体素子2と、この半導体素子2の複数の電極パッド
21それぞれと対応するリードワイヤ4aとを接続する
複数のボンディング線6と、半導体素子2、リードフレ
ームの素子搭載部41及び複数のリードフレームそれぞ
れの所定の部分、並びに複数のボンディング線6を直接
内部にモールド封入する封止樹脂パッケージ7とを有す
る構成となっている。
The semiconductor device of the first example has a lead frame comprising an element mounting portion 41 and a plurality of lead wires 4a, and a first surface adhered and fixed to the element mounting portion 41 of the lead frame. Semiconductor element 2 having a plurality of electrode pads 21, and a plurality of bonding wires 6 connecting lead wires 4a corresponding to the plurality of electrode pads 21 of semiconductor element 2, semiconductor element 2 and elements of the lead frame. The mounting portion 41 and a predetermined portion of each of the plurality of lead frames, and the sealing resin package 7 for directly molding and sealing the plurality of bonding wires 6 therein are provided.

【0005】この第1の例では、素子搭載部41の下側
の部分や、この素子搭載部41の上側の半導体素子2及
びボンディング線6に対し、所定の厚さの封止樹脂が必
要となるため、半導体装置全体の厚さが厚く、また外形
寸法も大きくなるという問題点がある。
In the first example, a sealing resin having a predetermined thickness is required for the lower part of the element mounting part 41 and the semiconductor element 2 and the bonding wire 6 above the element mounting part 41. Therefore, there is a problem that the thickness of the entire semiconductor device is large and the external dimensions are also large.

【0006】また、第2の例の半導体装置は、図3に示
すように(例えば特開平4−127558号公報参
照)、中央部にデバイスホール81が設けられ、第1の
面のデバイスホール81の周辺に薄膜配線82が形成さ
れ、第1の面より一段下った第2の面に、内部配線83
を介して薄膜配線82と接続する複数のリードピン12
が設けられたセラミックパッケージ8と、第1の面に複
数の電極パッド21が形成されこれら複数の電極パッド
21と薄膜配線82とがTAB(Tape Autom
ated Bonding)テープ10で接続されてデ
バイスホール81に収納された半導体素子2と、この半
導体素子2の第2の面と接合すると共にセラミックパッ
ケージ8の第3の面に接合するヒートシンク9と、セラ
ミックパッケージ8の第1の面、半導体素子2の第1の
面、及びTABテープ10を覆うように形成されたキャ
ップ13とを有する構成となっている。
Further, in the semiconductor device of the second example, as shown in FIG. 3 (for example, see Japanese Patent Application Laid-Open No. 4-127558), a device hole 81 is provided at the center, and the device hole 81 on the first surface is provided. , A thin film wiring 82 is formed on the second surface which is one step lower than the first surface.
Lead pins 12 connected to thin film wiring 82 through
Is provided, and a plurality of electrode pads 21 are formed on the first surface, and the plurality of electrode pads 21 and the thin film wiring 82 are TAB (Tape Automated).
a semiconductor chip 2 connected by an attached bonding tape 10 and housed in a device hole 81; a heat sink 9 joined to the second surface of the semiconductor element 2 and joined to a third surface of the ceramic package 8; The configuration includes a first surface of the package 8, a first surface of the semiconductor element 2, and a cap 13 formed so as to cover the TAB tape 10.

【0007】この第2の例の半導体装置では、薄膜配線
82とTABテープ10とが良好な一括ボンディングが
できるように、セラミックパッケージ8の第1の面は平
滑、かつ緻密な表面とする必要があり、セラミックパッ
ケージ8は、焼成後、研磨されて薄膜配線82が形成さ
れる。一方、第2の面に設けられた複数のリード・ピン
12は、その引っ張り強度等を強くするために、焼成メ
タライズ形成された電極パッドに接続固定されるように
なっており、セラミックパッケージ8の第1の面を研磨
するときに、焼成メタライズ形成された電極パッドも研
磨されてしまうのを防止するため、第2の面は、第1の
面より一段下った面となっている。
In the semiconductor device of the second example, the first surface of the ceramic package 8 needs to be smooth and dense so that the thin film wiring 82 and the TAB tape 10 can be bonded well. In addition, the ceramic package 8 is baked and polished to form the thin film wiring 82. On the other hand, the plurality of lead pins 12 provided on the second surface are connected and fixed to electrode pads formed by firing metallization in order to increase the tensile strength and the like. When the first surface is polished, the second surface is one surface lower than the first surface in order to prevent the electrode pad formed by firing metallization from being polished.

【0008】[0008]

【発明が解決しようとする課題】上述した従来の半導体
装置は、第1の例では、素子搭載部41の下側部分や、
半導体素子2及びボンディング線6上に、所定の厚さの
封止樹脂が必要となるため、全体の厚さが厚く、外形寸
法も大きくなるという問題点があり、第2の例では、セ
ラミックパッケージ8が、複雑な形状でかつ高精度な研
磨等を必要とするため加工工数がかかる上、素材がセラ
ミックであるため高価になるという問題点があり、また
TABテープ10も、ポリイミド系樹脂の表面に配線を
狭ピッチで形成するという複雑な構成であるため、高価
になる上、TABテープ10の配線と半導体素子2の電
極パッド21及び薄膜配線82との間で高精度の合せ作
業が要求されるため生産性が悪いという問題点がある。
In the first example, the conventional semiconductor device described above has a lower portion,
Since a sealing resin having a predetermined thickness is required on the semiconductor element 2 and the bonding wires 6, there is a problem that the overall thickness is large and the external dimensions are large. 8 is a complicated shape and requires high-precision polishing or the like, which requires a lot of processing man-hours, and is expensive because the material is ceramic. This is a complicated structure in which the wiring is formed at a narrow pitch, so that it is expensive and requires high-precision alignment work between the wiring of the TAB tape 10 and the electrode pads 21 and the thin-film wiring 82 of the semiconductor element 2. Therefore, there is a problem that productivity is poor.

【0009】本発明の目的は、安価で生産性も高く、か
つ全体の厚さを薄く、外形寸法を小さくすることができ
る半導体装置を提供することにある。
An object of the present invention is to provide a semiconductor device which is inexpensive, has high productivity, and can be reduced in overall thickness and external dimensions.

【0010】[0010]

【課題を解決するための手段】本発明の半導体装置は、
第1の面の中央部に予め設定された広さ及び深さの凹部
が設けられてモールド成形された所定の形状のパッケー
ジ本体と、第1の面の所定の位置に複数の電極パッドが
形成された半導体素子で、前記半導体素子の第1の面の
裏側の第2の面を前記パッケージ本体の凹部の底面に
記半導体素子の第1の面と前記パッケージ本体の第1の
面とがほぼ同一面になるように接着固定する前記半導体
素子と、前記半導体素子の複数の電極パッドそれぞれと
対応接続し所定の形状に形成された複数のリードワイヤ
と、これら複数のリードワイヤが接続された前記半導体
素子の第1の面全面、前記パッケージ本体の少なくとも
凹部周辺部分、及び前記複数のリードワイヤそれぞれの
対応する電極パッドとの接続部分の先端から前記パッケ
ージ本体の少なくとも凹部周辺部分にかけての全面を覆
うように絶縁材料で形成された絶縁被覆部とを有してい
る。
According to the present invention, there is provided a semiconductor device comprising:
A package body having a predetermined shape formed by providing a concave portion having a preset width and depth at a central portion of the first surface, and a plurality of electrode pads formed at predetermined positions on the first surface. A second surface on the back side of the first surface of the semiconductor device, the front surface of the semiconductor device being in front of the bottom surface of the concave portion of the package body.
Wherein a semiconductor element, a plurality of respective electrode pads and the corresponding connection a predetermined shape of the semiconductor device in which the first face of the serial semiconductor element and the first surface of the package body is adhesively fixed to be approximately in the same plane Lead wires formed on the semiconductor device, the entire first surface of the semiconductor element to which the plurality of lead wires are connected, at least a peripheral portion of the package body, and corresponding electrode pads of each of the plurality of lead wires And an insulating coating portion formed of an insulating material so as to cover the entire surface from the end of the connection portion to at least the periphery of the concave portion of the package body.

【0011】そして、前記複数のリードワイヤそれぞれ
を、対応する前記電極パッドとの接続部分から前記パッ
ケージ本体の第1の面に沿ってこの第1の面と側面との
第1の辺まで延び、この第1の辺で屈曲してこの側面に
沿ってこの側面と前記パッケージ本体の第1の面の裏側
第2の面との第2の辺まで延び、この第2の辺で前記
パッケージ本体の外側へ屈曲して所定の長さだけ延びた
形状とし、前記パッケージ本体の外側へ屈曲した部分
が、前記パッケージ本体の第2の面の延長面と同一かこ
の延長面よりわずかに突出するようにしたことを特徴と
する。
[0011] Each of the plurality of lead wires extends from a connection portion with a corresponding one of the electrode pads along a first surface of the package body to a first side of the first surface and the side surface, Bent along the first side and along the side surface and the back side of the side surface and the first surface of the package body
The second extends to the second side of the plane, the second in the side bent to the outside of the package body to a predetermined by the length extending shape, the portion that is bent to the outside of the package body is, It is characterized in that it is the same as or slightly protrudes from the extension surface of the second surface of the package body.

【0012】[0012]

【発明の実施の形態】次に本発明の実施の形態について
図面を参照して説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0013】図1(a),(b)は本発明の一実施の形
態を示す側面断面図及び斜視図である。
FIGS. 1A and 1B are a side sectional view and a perspective view showing an embodiment of the present invention.

【0014】この実施の形態は、第1の面の中央部に予
め設定された広さ及び深さの凹部11が設けられてモー
ルド成形された四角形状のパッケージ本体1と、第1の
面の周辺部分に複数の電極パッド21が形成されこの第
1の面の裏側の第2の面をパッケージ本体1の凹部11
の底面に、この第1の面とパッケージ本体1の第1の面
とがほぼ同一面となるように、接着剤3により接着固定
する半導体素子2と、この半導体素子2の複数の電極パ
ッド21それぞれと対応接続し所定の形状に形成された
複数のリードワイヤ4と、これらリードワイヤ4が接続
された半導体素子2の第1の面全面、パッケージ本体1
の凹部11の周辺部分、及び複数のリードワイヤそれぞ
れの対応する電極パッド(21)との接続部分の先端か
らパッケージ本体1の凹部11の周辺部分にかけての全
面を覆うように絶縁材料で形成された絶縁被覆部5とを
有する構成となっている。
In this embodiment, a rectangular package body 1 molded with a recess 11 having a preset width and depth at the center of the first surface is provided. A plurality of electrode pads 21 are formed in a peripheral portion, and a second surface on the back side of the first surface is formed in the concave portion 11 of the package body 1.
And a plurality of electrode pads 21 of the semiconductor element 2 adhered and fixed on the bottom surface of the semiconductor element 2 so that the first surface and the first surface of the package body 1 are substantially flush with each other. A plurality of lead wires 4 correspondingly connected to each other and formed into a predetermined shape; a first surface of the semiconductor element 2 to which these lead wires 4 are connected;
The package body 1 is formed of an insulating material so as to cover the entire peripheral portion of the concave portion 11 and a portion from the tip of the connection portion of each of the plurality of lead wires to the corresponding electrode pad (21) to the peripheral portion of the concave portion 11 of the package body 1. It has a configuration having an insulating coating portion 5.

【0015】なお、複数のリードワイヤ4それぞれは、
対応する電極パッド21との接続部分からパッケージ本
体1の第1の面に沿ってこの第1の面と側面との交点の
第1の辺まで延び、この第1の辺で屈曲してこの側面に
沿ってこの側面と第2の面との交点の第2の辺まで延
び、この第2の辺でパッケージ本体1の外側へ屈曲して
所定の長さだけ延びた形状となっており、また、外側へ
延長した部分の実装用基板との接触面が、パッケージ本
体1の第2の面と同一面かこの第2の面よりわずかに突
出するようにした形状となっている。
Each of the plurality of lead wires 4 is
A portion extending from the connection portion with the corresponding electrode pad 21 extends along the first surface of the package body 1 to a first side at the intersection of the first surface and the side surface, and bends at the first side to form the side surface. Along the second side of the intersection of the side surface and the second surface, and is bent outside the package body 1 at the second side to extend by a predetermined length. The contact surface with the mounting substrate of the portion extended outward has the same shape as the second surface of the package main body 1 or slightly protrudes from the second surface.

【0016】また、パッケージ本体1の凹部11の深さ
は、半導体素子2の第1の面がパッケージ本体1の第1
の面とほぼ同一面となるように、半導体素子2の厚さと
接着剤3の厚さとの和程度の厚さ、実際には接着剤の厚
さは極めて薄いので、半導体素子2の厚さと同程度の寸
法となっている。
The depth of the recess 11 of the package body 1 is such that the first surface of the semiconductor element 2 is the first surface of the package body 1.
The thickness of the semiconductor element 2 and the thickness of the adhesive 3 are substantially the same as the surface of the semiconductor element 2, and the thickness of the adhesive is actually extremely small. The dimensions are of the order.

【0017】パッケージ本体1は、予め製品出来上り寸
法に合わせて製作された金型に絶縁樹脂を注入してモー
ルド成形する。このパッケージ本体1は、形状も単純で
かつ製造工程も単純である上、素材も安価であるので、
コストを低く抑えることができる。また、凹部11の底
面と第2の面との厚さ、及び側面部分の厚さは、リード
ワイヤ4の取付け時の力や、リードワイヤ4による実装
用基板への実装時の力に耐えられる寸法とすればよく、
また、絶縁被覆部5の厚さも耐湿性が得てる程度の寸法
であればよいので、半導体装置全体の厚さを従来の第1
の例より薄く、かつ外形寸法も小さくすることができ
る。また、リードワイヤ4は、予め所定の形状に加工し
ておけば、その屈曲による力が半導体素子2やパッケー
ジ本体1に加わることはない。
The package body 1 is molded by injecting an insulating resin into a mold previously manufactured according to the finished product dimensions. The package body 1 has a simple shape and a simple manufacturing process, and is inexpensive.
Costs can be kept low. The thickness of the bottom surface and the second surface of the concave portion 11 and the thickness of the side surface portion can withstand the force when the lead wire 4 is attached and the force when the lead wire 4 is mounted on the mounting board. It should be just the dimensions,
In addition, the thickness of the insulating coating portion 5 may be a dimension enough to obtain moisture resistance.
And the external dimensions can be reduced. If the lead wire 4 is processed into a predetermined shape in advance, a force due to its bending will not be applied to the semiconductor element 2 or the package body 1.

【0018】なお、リードワイヤ4の半導体素子2の電
極パッド21への接続は、ボンディングツールにより、
超音波と熱及び荷重を同時にかけながら行う。この接続
後、絶縁材料により絶縁被覆部5を形成する。
The connection of the lead wire 4 to the electrode pad 21 of the semiconductor element 2 is performed by a bonding tool.
This is performed while simultaneously applying ultrasonic waves, heat and load. After this connection, the insulating coating portion 5 is formed with an insulating material.

【0019】[0019]

【発明の効果】以上説明したように本発明は、パッケー
ジ本体を、中央部に半導体素子収納用の凹部を有するモ
ールド成形品とし、この凹部に半導体素子を接着固定し
て所定の形状のリードワイヤを半導体素子の電極パッド
に接続し、半導体素子の全面、パッケージ本体の少なく
とも凹部周辺、及びリードワイヤのこれら部分と対応す
る部分を覆うように絶縁被覆部を形成する構成とするこ
とにより、パッケージ本体を含む各部の構造及び製造工
程を単純化することができ、かつ安価な素材が使用でき
るので、コストを低減することができると共に生産性を
向上させることができ、また、パッケージ本体や絶縁被
覆部の厚さを薄くすることができるので、半導体装置全
体の厚さを薄く、かつ外形寸法を小さくすることができ
る効果がある。
As described above, according to the present invention, the package body is a molded product having a concave portion for accommodating a semiconductor element in the center, and the semiconductor element is bonded and fixed to the concave portion to form a lead wire having a predetermined shape. Is connected to the electrode pads of the semiconductor element, and an insulating coating portion is formed so as to cover the entire surface of the semiconductor element, at least the periphery of the concave portion of the package body, and a portion corresponding to these portions of the lead wire, Can simplify the structure and manufacturing process of each part, and can use an inexpensive material, so that the cost can be reduced and the productivity can be improved. Since the thickness of the semiconductor device can be reduced, there is an effect that the thickness of the entire semiconductor device can be reduced and the external dimensions can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態を示す側面断面図及び斜
視図である。
FIG. 1 is a side sectional view and a perspective view showing an embodiment of the present invention.

【図2】従来の半導体装置の第1の例の側面断面図であ
る。
FIG. 2 is a side sectional view of a first example of a conventional semiconductor device.

【図3】従来の半導体装置の第2の例の側面断面図であ
る。
FIG. 3 is a side sectional view of a second example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 パッケージ本体 2 半導体素子 3 接着剤 4,4a リードワイヤ 5 絶縁被覆部 6 ボンディング線 7 封止樹脂パッケージ 8 セラミックパッケージ 9 ヒートシンク 10 TABテープ 12 リードピン 13 キャップ 21 電極パッド DESCRIPTION OF SYMBOLS 1 Package main body 2 Semiconductor element 3 Adhesive 4, 4a Lead wire 5 Insulation coating part 6 Bonding wire 7 Sealing resin package 8 Ceramic package 9 Heat sink 10 TAB tape 12 Lead pin 13 Cap 21 Electrode pad

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/02,23/28,23/12 H01L 23/50,21/60 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23 / 02,23 / 28,23 / 12 H01L 23 / 50,21 / 60

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1の面の中央部に予め設定された広さ
及び深さの凹部が設けられてモールド成形された所定の
形状のパッケージ本体と、第1の面の所定の位置に複数
の電極パッドが形成された半導体素子で、前記半導体素
子の第1の面の裏側の第2の面を前記パッケージ本体の
凹部の底面に前記半導体素子の第1の面と前記パッケー
ジ本体の第1の面とがほぼ同一面になるように接着固定
する前記半導体素子と、前記半導体素子の複数の電極パ
ッドそれぞれと対応接続し所定の形状に形成された複数
のリードワイヤと、これら複数のリードワイヤが接続さ
れた前記半導体素子の第1の面全面、前記パッケージ本
体の少なくとも凹部周辺部分、及び前記複数のリードワ
イヤそれぞれの対応する電極パッドとの接続部分の先端
から前記パッケージ本体の少なくとも凹部周辺部分にか
けての全面を覆うように絶縁材料で形成された絶縁被覆
部とを有し、前記複数のリードワイヤそれぞれを、対応
する前記電極パッドとの接続部分から前記パッケージ本
体の第1の面に沿ってこの第1の面と側面との第1の辺
まで延び、この第1の辺で屈曲してこの側面に沿ってこ
の側面と前記パッケージ本体の第1の面の裏側の第2の
面との第2の辺まで延び、この第2の辺で前記パッケー
ジ本体の外側へ屈曲して所定の長さだけ延びた形状と
し、前記パッケージ本体の外側へ屈曲した部分が、前記
パッケージ本体の第2の面の延長面と同一かこの延長面
よりわずかに突出するようにしたことを特徴とする半導
体装置。
1. A package body having a predetermined shape provided with a recess having a predetermined width and depth at a center portion of a first surface, and a plurality of package bodies having a predetermined shape at a predetermined position on the first surface. A first surface of the semiconductor device and a first surface of the package body, the second surface of the semiconductor device being provided on the bottom surface of the concave portion of the package body. The semiconductor element which is bonded and fixed so that the surface of the semiconductor element is substantially the same as a surface of the semiconductor element; a plurality of lead wires formed in a predetermined shape which are respectively connected to a plurality of electrode pads of the semiconductor element; From the entire first surface of the semiconductor element to which the package is connected, at least the periphery of the concave portion of the package body, and the tip of the connection portion of each of the plurality of lead wires with the corresponding electrode pad. An insulating coating portion formed of an insulating material so as to cover the entire surface of at least the periphery of the concave portion of the main body, wherein each of the plurality of lead wires is connected to a corresponding one of the electrode pads through a third portion of the package main body. The first side extends along the first side to the first side of the first side and the side, and is bent at the first side to extend along the side of the first side and the back side of the first side of the package body . The second side extends to a second side with the second surface, and the second side is bent to the outside of the package main body to extend by a predetermined length, and the portion bent to the outside of the package main body is A semiconductor device characterized in that it is the same as or slightly protrudes from an extension of the second surface of the package body.
JP10436797A 1997-04-22 1997-04-22 Semiconductor device Expired - Fee Related JP3130826B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10436797A JP3130826B2 (en) 1997-04-22 1997-04-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10436797A JP3130826B2 (en) 1997-04-22 1997-04-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH10294412A JPH10294412A (en) 1998-11-04
JP3130826B2 true JP3130826B2 (en) 2001-01-31

Family

ID=14378850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10436797A Expired - Fee Related JP3130826B2 (en) 1997-04-22 1997-04-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3130826B2 (en)

Also Published As

Publication number Publication date
JPH10294412A (en) 1998-11-04

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