JP3128917B2 - Integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device used for evaluating software under development.

[0002]

2. Description of the Related Art In a microcontroller (MCU) in which a CPU and a program memory are integrated, an apparatus called an in-circuit emulator (ICE) is used to evaluate software under development. This device uses a special integrated circuit device with an external interface that can use the memory in the ICE instead of the built-in memory, and enables easy change of program code and tracing of instruction execution. It is.

FIG. 3 shows a block diagram of a general microcontroller (MCU) 30. In this figure, a CPU 31, a program memory (ROM) 32, a work memory (RAM) 33, and a peripheral circuit 34 are integrated. The CPU 31 and a program memory (RO)
M) 32, work memory (RAM) 33 and peripheral circuit 3
4 between the data bus 35 and the address bus 36
And connected.

[0004] Such a microcontroller (MC)
U) 30, the integrated circuit device 40 for evaluation described above
Is configured, for example, as shown in FIG. In the figure, CP
U41, work memory (RAM) 42 and peripheral circuit 43
Are accumulated. The CPU 41, the work memory (RAM) 42 and the peripheral circuit 43 are connected to each other via a data bus 44 and an address bus 45. At the same time, the data bus 44, the address bus 45, and the CP
A control bus 46 for controlling the U 41 is connected to the external interface 47.

Therefore, by connecting an in-circuit emulator (ICE) to the external interface 47, a memory or the like in the in-circuit emulator (ICE) is connected instead of the program memory (ROM) 32 described above. By providing the software under development in the memory or the like, it is possible to evaluate the software, easily change the program code, and trace the execution of the instruction.

Incidentally, the above-mentioned microcontroller (M
CU), a device incorporating a plurality of CPUs is implemented. That is, FIG. 5 shows a block diagram of such a microcontroller (MCU) 50. In this figure, CPUs 51 and 52 are provided. Further, a program memory (ROM) 53, a work memory (RAM) 54, and peripheral circuits 55 and 56 are provided. And the above-mentioned CPU
51, 52 and their program memory (ROM) 5
3. Work memory (RAM) 54 and peripheral circuits 55, 5
6 are connected by data buses 57 and 58 and address buses 59 and 60, respectively.

However, in such an apparatus, when an integrated circuit device for evaluation described above is formed, data buses 57 and 58, address buses 59 and 60, and a CPU
The bit width of the external interface connected to the control bus for controlling the controllers 51 and 52 is twice as large as that of the single CPU 41 described above, and it is necessary to provide a large interface device.

However, the above-described integrated circuit device for evaluation may be mounted on a device having the same configuration as that of a product, for example, and the evaluation may be performed. In this case, the integrated circuit device is the same as an LSI constituting a microcontroller (MCU). It needs to be formed in size. In this case, the interface device is provided, for example, on the upper surface of the LSI. However, a very large interface device cannot be provided here, and therefore, it is difficult to realize the interface device.

[0009]

The problem to be solved is that, when an integrated circuit device for evaluation is formed for a device having a plurality of CPUs, it is necessary to provide a large interface device, and this is not realized. It will be difficult.

[0010]

According to the present invention, a plurality of CPUs are provided.
And a memory (a RAM corresponding to a program memory (ROM)) accessed by the plurality of CPUs.
(EPROM, EEPROM) 3), a first interface (external interface 15) for externally controlling this memory, and a second interface (external interface 24) for externally controlling the plurality of CPUs. And first switching means (switches 11, 12, 13, and 14) for switching, for each of the plurality of CPUs, whether to access the memory or to access an external memory through the first interface.
14, switches 16, 17, 18, 19) and the second
And second switching means (switches 22 and 23) for switching whether the control of the plurality of CPUs by the interface is enabled or disabled. )
An integrated circuit device characterized in that the integrated circuit device can be controlled from the integrated circuit device.

[0011]

According to this, it is possible to form an integrated circuit device for evaluating a device having a plurality of CPUs without increasing the bit width of the external interface.

[0012]

FIG. 1 shows the configuration of an integrated circuit device 100 according to the present invention. In this figure, CPUs 1 and 2 are provided. RAM corresponding to program memory (ROM)
(EPROM, EEPROM) 3, work memory (RA
M) 4 and peripheral circuits 5 and 6 are provided. And CPU
1, 2 and their RAM 3, work memory (RAM) 4
And the peripheral circuits 5 and 6 are connected to the data bus 7,
8 and address buses 9 and 10.

The data buses 7, 8 and the address bus 9,
10 are connected to an external interface 15 through switches 11, 12, 13, and 14, respectively. The data buses 7 and 8 and the address buses 9 and 10 are connected to a RAM 3 corresponding to a program memory (ROM) through switches 16, 17, 18 and 19, respectively. Further C
Control buses 20 and 21 for controlling the PUs 1 and 2 are connected to external interfaces 24 through switches 22 and 23, respectively.
Connected to. Here, external interfaces 15 and 2
4 have data buses 7 and 8, address buses 9 and 1
0 and one of the CPUs 1 and 2 suffices, and the bit width is equivalent to that of a single CPU.

On the other hand, switches 11, 12, 13,
14, switch 16, 17, 18, 19, switch 2
A control signal path for switching control between 2 and 23 is connected to the external interface 25. And in this case,
Switches 11, 12, 13, 14, switches 16, 1,
The switching of the switches 7, 18, 19 and the switches 22, 23 is performed, for example, as shown in FIG.

That is, in the figure, state 1 is CPU1,
2 is driven by a RAM 3 corresponding to a built-in program memory (ROM). State 2 is CPU1
Is driven by a memory or the like in an in-circuit emulator (ICE), and a CPU 2 has a built-in program memory (RO).
M) is a case of driving with the RAM 3 corresponding to M). Further, the state 3 is a program memory (ROM) having the CPU 1 built therein.
And the CPU 2 is driven by a memory or the like in an in-circuit emulator (ICE).

For each of these states 1 to 3, switches 11, 12, 13, 14, switches 16, 17,
Switching of the switches 18 and 19 and the switches 22 and 23 is performed as shown. Here, switches 11 and 13, 12 and 1
4, 16 and 18, and 17 and 19 are switched in conjunction with each other. Therefore, in this device, the number of control signal paths connected to the external interface 25 is 6, and the number of bits to be interfaced is 6 bits.

That is, in this device, the bit width of the external interfaces 15 and 24 can be made equal to that of a single CPU only by providing 6 bits for switching. For example, the bit width of the data bus is 8 bits, the bit width of the address bus is 16 bits, and the bit width of the control bus is 8 bits.
Is a bit. On the other hand, by providing only 6 bits for switching the switch, it is possible to avoid that these are doubled.

Thus, according to the above-described device, an integrated circuit device for evaluating a device having a plurality of CPUs 1 and 2 can be formed without increasing the bit width of the external interfaces 15 and 24. .

In the above apparatus, the switch 11,
13 and 16, 18 and switches 12, 14 and 17, 1
Reference numerals 9 are inverted and switched. Therefore, by providing a switching signal inverting means in the apparatus, these interfaces can be performed with 2 bits. If other combinations are determined,
By providing the decoding means in the device, the bits of these interfaces can be reduced.

Further, in the above-described device, the built-in C
The number of PUs may be three or more. In this case, the number of bits of the interface of the switch switching signal increases, but the bit width of the external interfaces 15 and 24 does not increase, and the bit width of the entire interface can be reduced.

[0021]

According to the present invention, it is possible to form an integrated circuit device for evaluating a device incorporating a plurality of CPUs without increasing the bit width of the external interface.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of an integrated circuit device according to the present invention.

FIG. 2 is a table for explaining the operation.

FIG. 3 is a configuration diagram of a microcontroller (MCU) containing a single CPU.

FIG. 4 is a configuration diagram of a conventional integrated circuit device.

FIG. 5 is a configuration diagram of a microcontroller (MCU) including a plurality of CPUs.

[Explanation of symbols]

1, 2 CPU 3 RAM equivalent to program memory (ROM) 4 Work memory (RAM) 5, 6 Peripheral circuit 7, 8 Data bus 9, 10 Address bus 11, 12, 13, 14, 16, 17, 18, 19 , 2
2,23 switch 15,24,25 external interface 20,21 control bus 100 integrated circuit device

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-82377 (JP, A) JP-A-63-85957 (JP, A) JP-A-63-167939 (JP, A) 270058 (JP, A) JP-A-61-151776 (JP, A) JP-A-60-233757 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/22-11 / 34 G06F 15/16-15/177 G06F 15/78

Claims (1)

(57) [Claims] A plurality of CPUs; a memory accessed by the plurality of CPUs; a first interface for externally controlling the memory; and a first interface for externally controlling the plurality of CPUs. A first switching means for switching, for each of the plurality of CPUs, whether to access the memory or to access an external memory through the first interface; and An integrated circuit device provided with second switching means for switching whether control of a plurality of CPUs is enabled or disabled, and wherein the first and second switching means can be externally controlled; .