JPS63262739A - Device with cpu - Google Patents

Device with cpu

Info

Publication number
JPS63262739A
JPS63262739A JP9778287A JP9778287A JPS63262739A JP S63262739 A JPS63262739 A JP S63262739A JP 9778287 A JP9778287 A JP 9778287A JP 9778287 A JP9778287 A JP 9778287A JP S63262739 A JPS63262739 A JP S63262739A
Authority
JP
Japan
Prior art keywords
roms
control circuit
selecting
address
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9778287A
Other languages
Japanese (ja)
Inventor
Yoshinori Matsuura
松浦 芳則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9778287A priority Critical patent/JPS63262739A/en
Publication of JPS63262739A publication Critical patent/JPS63262739A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To change a program started by the same absolute address, in an unmanned state, by providing plural pieces of ROMs, and resetting a CPU by selecting the ROM corresponding to set information from the outside. CONSTITUTION:In ROMs 3-5, each different program is stored from an absolute address 0000H. Also, address lines A0-A15 are connected to other memory system, as well. A control circuit 2 is a circuit for selecting the ROMs 3-5, and constituted of an EEPROM 10 and a one-chip microcomputer 11. In this state, OR of set information from an external apparatus or a front panel operating part, and the address line A15 is taken, and a chip selecting signal for selecting the ROMs 3-5 is generated. Accordingly, in case of changing a control program, when the set information is inputted to the control circuit 2, a desired ROM can be selected automatically by the control circuit 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はCPU、ROM、RAM1F!、有する装置に
関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention applies to CPU, ROM, RAM 1F! , relates to an apparatus having.

〔従来の技術〕[Conventional technology]

従来、CPUで割り当てられるプログラム領域には制限
があり、プログラム領域の大部分を制御プログラムが占
めている装置においては、大規模な装置動作試験プログ
ラムやハードウェアは同じだが全く別個の大規模なプロ
グラムで動作させることが必要な場合にはROMを交換
する必要があった。
Conventionally, there is a limit to the program area that can be allocated by the CPU, and in devices where the control program occupies most of the program area, it is difficult to create a large-scale device operation test program or a large-scale program that uses the same hardware but is completely different. If it was necessary to operate the device, the ROM had to be replaced.

【発明が解決しようとする問題点〕[Problem that the invention attempts to solve]

上述した従来の装置は、大規模な装置動作試験プログラ
ムや別個のプログラムで動作させるためには、装置の電
源を切り、ROMが搭載されているユニットを抜き出し
、日OrV’l交換した後にユニットを装置へ戻し、装
置の電源を入れるという手順が必要なので無人化するこ
とができないという欠点がある。
In order to operate the above-mentioned conventional device with a large-scale device operation test program or a separate program, it is necessary to turn off the power of the device, remove the unit with the ROM installed, and replace the unit after replacing the ROM. It has the disadvantage that it cannot be unmanned because it requires the steps of returning it to the device and turning on the power to the device.

(問題点を解決するための手段) 本発明のCPU付装置は、複数のROMと、外部インタ
ーフェースから設定情報を入力し、CPUをリセットす
るとともに複数のROMから該設定情報に対応するいず
れか1つの日0rl1選択する制御回路とを有する。
(Means for Solving the Problems) The CPU-equipped device of the present invention inputs setting information from a plurality of ROMs and an external interface, resets the CPU, and selects one of the plurality of ROMs corresponding to the setting information. It has a control circuit that selects 0rl1 on one day.

〔作用〕[Effect]

したがって、これらのROMに同じ先頭番地から異なっ
たプログラムを予め格納しておけば、ROMを交換する
ことなく別のプログラムで装Mを動作させることかでき
る。
Therefore, if different programs are stored in advance in these ROMs from the same starting address, the device M can be operated with different programs without replacing the ROMs.

〔実施例〕〔Example〕

次に、本発明の実施例についで図面を参照しで説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明のCPU付装百の一実施例のブロック図
、第2図は第1図中の制御回路2と外部インターフェー
ス9の詳細図である。
FIG. 1 is a block diagram of a CPU-equipped embodiment of the present invention, and FIG. 2 is a detailed diagram of the control circuit 2 and external interface 9 in FIG.

本実施例は通信回線の監視および切替を行なう通信回線
切替装置で、CPU 1と、制御回路2と、ROM3〜
5(アドレス空間0000 )−1〜7FFFH)と、
データバス7と、アドレスバス8と、外部インターフェ
ース9等で構成されでいる。アドレスバス8のアドレス
線A0〜AI5のうちアドレス線AI5は制御回路2に
接続され、ROM3〜5にはアドレスA0〜A14が接
続されでいる。なお、ROM3〜5は絶対番地0000
Hから相異なったプログラムが格納されでいる。ま茫、
アドレス線A0〜AI5は他のメモリシステム(不図示
で、アドレス空間8000 H−FFFF H)にも接
続されでいる。制御回路2はROM3〜5を選択する回
路で、EEPROMIOとワンチップマイクロコンピュ
ータ11からなり、通信インターフェース12を介して
外部機器14または前面パネル操作部13からの設定情
報とアドレス線A Isの論理和をとり、ROM3〜5
を選択するチップセレクト信号C3I 、 C32、C
S3のいずれかを発生し、次にCPU1にリセット信号
RESET %出力する。なお、設定情報はEEPRO
MIOに記憶され、電源断時にもその内容を保持するよ
うになっている。
This embodiment is a communication line switching device that monitors and switches communication lines, and includes a CPU 1, a control circuit 2, and ROMs 3 to 3.
5 (address space 0000)-1 to 7FFFH),
It is composed of a data bus 7, an address bus 8, an external interface 9, etc. Among address lines A0 to AI5 of address bus 8, address line AI5 is connected to control circuit 2, and addresses A0 to A14 are connected to ROMs 3 to 5. Furthermore, ROM3 to 5 are at absolute address 0000.
Different programs have been stored since H. Maasa,
Address lines A0-AI5 are also connected to other memory systems (address spaces 8000H-FFFFH, not shown). The control circuit 2 is a circuit for selecting ROMs 3 to 5, and is composed of an EEPROMIO and a one-chip microcomputer 11, and performs the logical sum of setting information from an external device 14 or front panel operation unit 13 via a communication interface 12 and an address line AIs. and ROM3~5
Chip select signal to select C3I, C32, C
S3 is generated, and then a reset signal RESET% is output to the CPU1. In addition, the setting information is EEPRO
It is stored in the MIO, and its contents are retained even when the power is turned off.

したがって、制御プログラムを変更する場合には外部機
器14あるいは前面パネル操作部13から設定情報を制
御回路2に入力すれば、制御回路2により所望のROM
が自動的に選択される。
Therefore, when changing the control program, if the setting information is input to the control circuit 2 from the external device 14 or the front panel operation section 13, the control circuit 2 selects the desired ROM.
is automatically selected.

(発明の効果) 以上説明したように本発明は、ROMを複数個設(す、
外部からの設定情報に対応したROMG選択しで、CP
Uをリセットすることにより、同し絶対番地が開始する
プログラムを無人の状態で変更することができ、ROM
交換に必要な人員を削減することができる効果がある。
(Effects of the Invention) As explained above, the present invention has a plurality of ROMs.
Select the ROMG that corresponds to the setting information from the outside, and then
By resetting U, a program starting at the same absolute address can be changed unattended, and the ROM
This has the effect of reducing the number of personnel required for replacement.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のCPIJ付装置の一実施例の構成を示
す図、第2図は第1図中の制御回路2、外部インターフ
ェース9の構成を示す図である。 1・・・CPU、      2・・・制御回路、3.
4.5−ROM、   7・・・データバス、8・・・
アドレスバス、 9・・・外部インターフェース、 10・・・E E P ROM、 11・・・ワンチップマイクロコンピュータ、12・・
・通信インターフェース、 13・・・前面パネル操作部、 14・・・外部機器、
A0〜A Is ””アドレス線、 CSI 〜CS3−・・チップセレクト信号、RESE
T−・・リセット信号。
FIG. 1 is a diagram showing the configuration of an embodiment of the CPIJ attached device of the present invention, and FIG. 2 is a diagram showing the configuration of the control circuit 2 and external interface 9 in FIG. 1. 1...CPU, 2...Control circuit, 3.
4.5-ROM, 7...data bus, 8...
address bus, 9... external interface, 10... EEPROM, 11... one-chip microcomputer, 12...
・Communication interface, 13...Front panel operation unit, 14...External device,
A0 ~ A Is "" Address line, CSI ~ CS3-...Chip select signal, RESE
T--Reset signal.

Claims (1)

【特許請求の範囲】 CPUを有する装置において、 複数のROMと、外部インターフェースから設定情報を
入力し、CPUをリセットするとともに複数のROMか
ら該設定情報に対応するいずれか1つのROMを選択す
る制御回路とを有することを特徴とするCPU付装置。
[Claims] In a device having a CPU, a plurality of ROMs and a control for inputting setting information from an external interface, resetting the CPU, and selecting one ROM corresponding to the setting information from the plurality of ROMs. A CPU-equipped device characterized by having a circuit.
JP9778287A 1987-04-20 1987-04-20 Device with cpu Pending JPS63262739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9778287A JPS63262739A (en) 1987-04-20 1987-04-20 Device with cpu

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9778287A JPS63262739A (en) 1987-04-20 1987-04-20 Device with cpu

Publications (1)

Publication Number Publication Date
JPS63262739A true JPS63262739A (en) 1988-10-31

Family

ID=14201396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9778287A Pending JPS63262739A (en) 1987-04-20 1987-04-20 Device with cpu

Country Status (1)

Country Link
JP (1) JPS63262739A (en)

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