JP3123937B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure for reducing a leakage current of a PN junction of an insulated gate field effect transistor constituting the semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the advance of high integration of semiconductor devices,
The demand for miniaturization of the pattern size, which is the driving force, is becoming increasingly severe. In addition, as the pattern size is rapidly miniaturized, an insulated gate field effect transistor (hereinafter, referred to as a MOS) is required to maintain or further improve the function of the semiconductor element and the element isolation region between the semiconductor elements. The impurity diffusion layers forming the source / drain regions of the transistor (referred to as a transistor) have been made shallower, or the horizontal diffusion of the impurity diffusion layers on the surface of the semiconductor substrate has been reduced.

As a method for forming an impurity diffusion layer of a semiconductor integrated circuit composed of MOS transistors, a thick field oxide film and a gate electrode are used as a mask to ion-implement impurities of the opposite conductivity type to the semiconductor substrate in a self-aligned manner (self-aligned). A method of activating impurity ions by implanting and subsequently performing heat treatment is widely and generally employed. Further, after forming the impurity diffusion layer, in forming a wiring interconnecting the individual elements formed on the semiconductor substrate, a BPSG film (silicon containing boron glass and phosphorus glass) is used for flattening the surface of the insulating layer below the wiring. A method of performing a heat treatment on a material such as an oxide film is used. By this heat treatment, the impurities forming the impurity diffusion layer are thermally diffused, and the position of the PN junction is deep from the surface of the semiconductor substrate and spreads in the horizontal direction. Therefore, the end of the PN junction on the surface of the semiconductor substrate has reached deep below the field oxide film, which is a mask for impurity ion implantation.

Hereinafter, a conventional technique will be described with reference to FIG. FIG. 8 is a sectional view of a conventional MOS transistor in the order of manufacturing steps. The structure will be described together with the description of the manufacturing process.

As shown in FIG. 8A, for example, a field oxide film 102 is formed on the surface of a silicon substrate 101 having a P-type conductivity and an impurity concentration of about 1 × 10 ¹⁶ atoms / cm ³ . Then, a gate oxide film 103 is formed on the surface of the silicon substrate 101.

[0008] Next, as shown in FIG. 8 (b), a gate electrode 104 is formed in a predetermined region on the gate oxide film 103. Then, the field oxide film 102 and the gate electrode 1
A low concentration impurity diffusion layer 105 is formed to be self-aligned at 04. Here, the impurity of the low concentration impurity diffusion layer 105 is usually a phosphorus impurity. next,
A silicon oxide film is formed by a chemical vapor deposition (CVD) method or the like, and further, anisotropic dry etching (etch back) is performed. As shown in FIG. It is formed on the side wall of the electrode 104. In this etch-back step, the surface of the field oxide film 102 is also slightly etched.

Next, high-concentration impurities such as arsenic impurities are ion-implanted, and further subjected to a heat treatment to produce LDD (Lig).
The source / drain diffusion layer 107 having an htly doped drain structure is formed. Here, the junction surface of the source / drain diffusion layer 107 with the silicon substrate 101 is formed so as to be located at the end of the field oxide film 102 and below the field oxide film 102. The concentration of the high-concentration impurity is set to about 10 ¹⁹ atoms / cm ³ . Alternatively, in some cases, the impurity concentration of the source / drain diffusion layer 107 may be formed in a low concentration state. In this case, the impurity concentration is set to about 10 ¹⁸ atoms / cm ³ . A technique relating to such a structure is described in Japanese Patent Application Laid-Open No. 61-156682.

Next, as shown in FIG. 8D, the field oxide film 102 and the source / drain diffusion layer 107 formed on the surface of the silicon substrate 101, as well as the gate electrode 104 and the sidewall insulating film 106 are covered. As described above, the protective insulating film 108 is formed by the CVD method.

Next, an interlayer insulating film 109 is formed. Here, the interlayer insulating film 109 is made of B deposited by the CVD method.
It is a PSG film whose surface is flattened by the heat treatment.

[0010] Then, contact holes are formed in predetermined regions of the protective insulating film 108 and the interlayer insulating film 109, and source / drain electrodes 110 connected to the source / drain diffusion layers 107 are formed.

In this manner, a MOS transistor having the gate oxide film 103, the gate electrode 104, and the source / drain diffusion layers 107 on the silicon substrate 101 is formed. Here, a diffusion layer end 107a which is an end of the source / drain diffusion layer 107 must be formed at an end of the field oxide film 102 and at a position below the end, as shown in FIG. 8D.

[0012]

As described above, semiconductor elements such as MOS transistors are miniaturized as semiconductor devices become more highly integrated. The PN junction is made shallower and the element isolation region is made finer. However, when a MOS transistor or the like is miniaturized as in the related art, the reverse diode characteristic of the PN junction deteriorates. That is, it has been found that the leakage current due to the reverse bias of the PN junction increases.

This will be described with reference to FIG. FIG. 9 schematically shows a cross section of a PN junction of a MOS transistor according to a conventional technique. Here, FIG.
FIG. 9A shows a case where the source / drain diffusion layer 107 described in the related art has a high concentration impurity, and FIG.
Is a case where the source / drain diffusion layer 107 has a low concentration impurity. In FIG. 9, the same components as those in FIG. 8 are denoted by the same reference numerals.

As shown in FIG. 9A, a field oxide film 102 is formed on a silicon substrate 101 having a P-type conductivity. Then, a source / drain diffusion layer 107 having an N-type conductivity is provided, and a protective insulating film 108 is formed so as to cover the whole. Further, an interlayer insulating film 109 is formed on the protective insulating film 108,
The drain electrode 110 is connected to the source / drain diffusion layer 107 through the contact hole.

Here, if the etching back time described in the prior art shifts or the processing time with a hydrofluoric acid solution becomes longer, the surface of the field oxide film 102 is etched, and the end 107a of the diffusion layer becomes the field oxide film 102. It will be exposed from. This is more remarkable as the diffusion layer becomes shallower. Therefore, the position of the field oxide film end 111 is lower than the position of the diffusion layer end 107a. The end 107a of the diffusion layer is
8 will be covered directly.

With such a structure, when a reverse bias is applied between the source / drain diffusion layer 107 and the silicon substrate 101, the first depletion layer 112 is formed on the silicon substrate 101 side. In this case, since the impurity concentration of the source / drain diffusion layer 107 is high, a depletion layer is hardly formed on the source / drain diffusion layer 107 side. Thus, in the case of FIG. 9A, the structure is such that the protective insulating film 108 is formed on the surface of the depletion layer formed at the PN junction. Here, in the related art, an interface state is formed at the boundary between the protective insulating film 108 and the first depletion layer 112. For this reason, a leak current is generated via the interface state.

Similarly, as shown in FIG. 9B, a field oxide film 102 is formed on a silicon substrate 101. Then, a source / drain diffusion layer 107 having a low concentration impurity is provided, and a protective insulating film 108 is formed so as to cover the whole. Further, an interlayer insulating film 109 is formed on the protective insulating film 108, and the source / drain electrodes 110 are connected to the source / drain diffusion layers 107 through the contact holes.

In this case, the diffusion layer end 107a
Are located below the field oxide film edge 111.

In this structure, when a reverse bias is applied between the source / drain diffusion layer 107 and the silicon substrate 101, a first depletion layer 112 is formed on the silicon substrate 101 side. In this case, since the impurity concentration of the source / drain diffusion layer 107 is low, the second depletion layer 11
3 is also formed on the source / drain diffusion layer 107 side. Then, the position of the depletion layer end 113a is located above the field oxide film end 111. Thus, in the case of FIG. 9B, the structure is such that the protective insulating film 108 is formed on the surface of the depletion layer formed at the PN junction. For this reason, in the same manner as described above, a leak current occurs via the interface state.

Such an increase in the leakage current of the PN junction is slight and can be detected by a semiconductor device having high sensitivity. Such a leak current at the PN junction and its cause are new findings discovered by the present inventors for the first time.

An object of the present invention is to reduce the leakage current caused by the reverse bias of the PN junction, which occurs when the diffusion layer is made shallow and the lateral spread is reduced in order to miniaturize the MOS transistor and element isolation. An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same.

[0022]

For this purpose, a semiconductor device according to the present invention has a reverse conductivity type impurity diffusion layer formed in a predetermined region of a semiconductor substrate of one conductivity type. An insulated gate field effect transistor serving as a source / drain region is formed, and a thin thermally oxidized silicon oxide film is deposited on the surface of the impurity diffusion layer.

Alternatively, the semiconductor device of the present invention has an element isolation insulating film formed in a predetermined region of a semiconductor substrate of one conductivity type and an impurity diffusion layer formed in contact with the element isolation insulating film, A thin thermally oxidized silicon oxide film is deposited on the surface of the impurity diffusion layer.

Here, in the semiconductor device of the present invention, the impurity concentration of the impurity diffusion layer is set to be about one digit higher than the impurity concentration of the semiconductor substrate, and when a reverse bias is applied between them, The value of the width of the depletion layer formed on the semiconductor substrate side and the impurity diffusion layer side is the same digit.

The thickness of the thermally oxidized silicon film is 1
nm or more.

Alternatively, the device isolation insulating film is formed so as to be buried in a concave portion of a semiconductor substrate, and the thermal silicon oxide film is formed so as to be sandwiched between the semiconductor substrate and the device isolation insulating film. .

Alternatively, the impurity diffusion layer is connected to a conductive layer in a floating state, and charges are stored in the conductive layer.

The conductive layer forms a lower electrode of the capacitor.

Further, a method of manufacturing a semiconductor device according to the present invention
A step of selectively forming an element isolation insulating film on a surface of a semiconductor substrate, a step of forming a gate insulating film and a gate electrode on a surface of a predetermined region of the semiconductor substrate, and the step of forming the gate electrode and the element isolation insulating film Forming an impurity diffusion layer in a self-aligned manner , removing the insulating film on the surface of the impurity diffusion layer once , and further exposing a junction of the impurity diffusion layer.
A step of thereby Ru is, then, comprises the steps of forming a thin silicon oxide film using the impurity diffusion layer surface was thermally oxidized, and a step of forming an interlayer insulating film on the thin silicon oxide film. What
After removing the insulating film on the surface of the impurity diffusion layer once,
It is preferable that the surface of the impurity diffusion layer be inactivated.

Here, the thermal oxidation of the surface of the impurity diffusion layer is performed in a low pressure CVD furnace, and subsequently, the same low pressure CVD
An interlayer insulating film is formed in a furnace.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. Here, FIG. 1 is a cross-sectional view of the semiconductor device of the present invention, and FIG. 2 is a cross-sectional view in the order of manufacturing steps. FIG. 3 is a flowchart of the main steps of the present invention.

As shown in FIG. 1, a field oxide film 2 is selectively formed on a surface of a silicon substrate 1 of one conductivity type. Then, a gate oxide film 3 is formed in a predetermined region on the surface of the silicon substrate 1. Further, a gate electrode 4 and a sidewall insulating film 5 on the side wall thereof are formed on the gate oxide film 3.

Then, a source / drain diffusion layer 6 of the opposite conductivity type is formed. Here, the impurity concentration of the source / drain diffusion layer 6 is set to be low. Further, in the present invention, a protective thermal oxide film 7 is provided on the surface of the source / drain diffusion layer 6. Then, a protective insulating film 8 is formed so as to cover the protective thermal oxide film 7, the field oxide film 2, the gate electrode 4, and the like, and an interlayer insulating film 9 is formed on the protective insulating film 8.

Contact holes are formed in predetermined regions of the protective thermal oxide film 7, the protective insulating film 8, and the interlayer insulating film 9 on the source / drain diffusion layers 6, and the source / drain diffusion layers 6 are formed through the contact holes. Are provided.

In such a MOS transistor semiconductor device, a MOS transistor without the sidewall insulating film 5 is formed in the same manner.

Next, such a semiconductor device, that is, MO
A method for manufacturing the S transistor will be described with reference to FIGS.

As shown in FIG. 2A, similarly to the prior art, a P-type impurity concentration of 1 × 10 ¹⁶ atoms / cm ^{3 is used.}
A field oxide film 2 having a thickness of about 300 nm is formed on the surface of silicon substrate 1 having a thickness of about 300 nm. Further, gate oxide film 3 is formed on the surface of silicon substrate 1. Here, the gate oxide film 3 is a silicon oxide film having a thickness of about 10 nm.

Next, as shown in FIG. 2B, a gate electrode 4 is formed in a predetermined region on the gate oxide film 3. Here, the gate electrode 4 is formed of a polycide film containing a refractory metal such as a tungsten polycide film. Next, CV
A silicon oxide film is formed by a method D or the like, and further, is etched back in the same manner as in the prior art, and a sidewall insulating film 5 is formed on the side wall of the gate electrode 4 as shown in FIG. Become like In this etch back process,
The surface of field oxide film 2 is also etched. Then, source / drain diffusion layers 6 are formed so as to be self-aligned with field oxide film 2 and gate electrode 4. This source / drain diffusion layer 6 is formed by ion implantation of impurities and subsequent heat treatment. Here, an arsenic impurity is used as the impurity of the source / drain diffusion layer 6, and its concentration is set to about 10 ¹⁸ atoms / cm ³ .

Next, as shown in FIG. 2D, a protective thermal oxide film 7 is formed on the surface of the source / drain diffusion layer 6 by thermal oxidation. Furthermore, the protective insulating film is formed by CVD so as to cover the field oxide film 2 formed on the surface of the silicon substrate 1 and the protective thermal oxide film 7 on the surface of the source / drain diffusion layer 6 and the gate electrode 4 and the sidewall insulating film 5. A film 8 is formed.

Here, the process of forming the protective thermal oxide film 7 will be described with reference to the process flow chart of FIG.

After the formation of the source / drain diffusion layer 6 containing a low concentration of arsenic impurity, the surface of the silicon substrate, particularly the surface of the source / drain diffusion layer 6, is cleaned. In this surface cleaning, the natural oxide film formed on the surface of the source / drain diffusion layer 6 is removed and the surface is inactivated, while the contaminant impurities are removed by cleaning.
Due to this passivation, a natural oxide film is not formed on the surface of the source / drain diffusion layer 6. Next, the silicon substrate in such a state is placed in a low pressure (LP) CVD furnace, and the following processing is continuously performed. here,
The temperature of the LPCVD furnace is set to about 800 ° C.

That is, first, as the first processing, 80
Nitrous oxide (N ₂ O) gas is introduced into an LPCVD furnace at about 0 ° C. In this first process, a silicon oxide film having a thickness of about 1 nm is formed on the surface of the source / drain diffusion layer 6. This extremely thin silicon oxide film becomes the protective thermal oxide film 7.

After the formation of the protective thermal oxide film 7, the second
Then, a mixed gas of silane (SiH ₄ ) gas and nitrous oxide gas is introduced into the LPCVD furnace,
A silicon oxide film formed by CVD at a relatively high temperature is deposited on the surface of the protective thermal oxide film.

Thereafter, an interlayer insulating film 9 is formed as described in the background art. Then, contact holes are formed in predetermined regions of the protective thermal oxide film 7, the protective insulating film 8, and the interlayer insulating film 9, and source / drain electrodes 10 connected to the source / drain diffusion layers 6 are formed. .

Next, the effects of the present invention of the first embodiment will be described with reference to FIG. Here, FIG. 4A is a sectional view of a memory cell portion of a DRAM to which the present invention is applied. This memory cell is composed of one transfer transistor which is a MOS transistor and one capacitor. Hereinafter, the main part of the memory cell will be briefly described.

As shown in FIG. 4A, a field oxide film 12 is selectively formed on a surface of a predetermined region of a P-type silicon substrate 11. Then, a gate electrode 13 is formed on the surface of the silicon substrate 11 via a gate oxide film. A side wall insulating film 14 is formed on the side wall of the gate electrode 13.

The first diffusion layer 15 and the second diffusion layer 15 are formed on the surface of the silicon substrate between the field oxide film 12 and the gate electrode 13.
Diffusion layer 16 is formed. Here, the impurity concentration of the first diffusion layer 15 is set to be low, and the impurity concentration of the second diffusion layer 16 is set to be high. Similarly, FIG.
As shown in (a), a first diffusion layer 15a and a second diffusion layer 16a are also formed. The first diffusion layers 15 and 15a formed with the gate electrode interposed therebetween serve as source / drain regions of the transfer transistor.

A protective thermal oxide film 17 is provided on the surfaces of the first diffusion layers 15 and 15a.

Further, a lower electrode 19 of the capacitor and an upper electrode 20 are formed in the interlayer insulating film 18 with the capacitive insulating film interposed therebetween. Here, the lower electrode 19 is the first diffusion layer 1
5 is connected. The first diffusion layer 15a is connected to the bit line 21. Here, the second diffusion layer 1
6, 16a are the lower electrode 19 and the bit line 2 respectively.
1 is formed by diffusing high-concentration impurities contained in 1.

The gate electrodes 13a and 13b constitute the gate electrodes of the transfer transistors of the adjacent memory cells.

FIG. 4B shows an equivalent circuit of one memory cell having such a structure. That is, the word line WL is connected to the gate electrode of the transfer transistor TR. Then, one source / drain region of the transfer transistor TR is connected to the bit line BL. The other source / drain region is a capacitor C
It is connected to the P electrode. Here, a connection portion between the other source / drain region and the electrode of the capacitor CP is referred to as a node N1.

Next, based on FIG. 5, a TEG (Test Element) of a DRAM having such a memory cell will be described.
The relationship between the non-defective product ratio of the ntal group) and the protective thermal oxide film thickness will be described. Here, the TEG of the DRAM is 1
This is a semiconductor chip having memory cells for 6 megabits. The vertical axis in FIG. 5 indicates the yield rate of the semiconductor chip, and the horizontal axis indicates the thickness of the protective thermal oxide film.

As can be seen from FIG. 5, the non-defective chip rate sharply increases as the protective thermal oxide film thickness approaches 1 nm, and at 1 nm, the non-defective chip rate increases to nearly 100%.
As described above, in the present invention, when a protective thermal oxide film having a thickness of 1 nm or more is formed on the surface of the source / drain diffusion layer, a very large effect is produced.

Next, the effect of the present invention will be described with reference to FIG.
It will be described based on. FIG. 6 is a diagram showing the MOS in the technology of the present invention.
3 schematically illustrates a cross section of a PN junction of a transistor.

As shown in FIG. 6, a field oxide film 2 is formed on a silicon substrate 1. Then, a source / drain diffusion layer 6 having a low concentration impurity is provided, and a protective thermal oxide film 7 is formed only on the surface of the source / drain diffusion layer 6. Then, a protective insulating film 8 is provided so as to cover the whole. Further, an interlayer insulating film 9 is formed on the protective insulating film 8, and the source / drain electrodes 10 are formed.
Are connected to the source / drain diffusion layers 6 through the contact holes.

In this case, the diffusion layer end 6a is located below the field oxide film end 22.

With such a structure, when a reverse bias is applied between the source / drain diffusion layer 6 and the silicon substrate 1,
A first depletion layer 23 is formed on the silicon substrate 1 side. Further, the second depletion layer 24 is also formed on the source / drain diffusion layer 6 side. Then, the second depletion layer end 2
The position 4a is located above the field oxide film end 22. However, in this case, the protective thermal oxide film 7
Have a structure that covers the surface of the second depletion layer 24.
For this reason, the interface state in this region is greatly reduced unlike the case of the conventional technique. Then, leakage current via the interface state is prevented.

Next, a second embodiment of the present invention will be described with reference to FIG. Here, FIG. 7 is a sectional view of a MOS transistor which is a semiconductor element of the present invention.

As shown in FIG. 7, a trench is formed in a predetermined region on the surface of a silicon substrate 31 of one conductivity type, and an element isolation insulating film 32 is formed in the trench. Then, as in the first embodiment, a gate oxide film 33 is formed in a predetermined region on the surface of the silicon substrate 31.
Further, on the gate oxide film 33, a gate electrode 34 and a sidewall insulating film 35 on the side wall thereof are formed.

Then, a source / drain diffusion layer 36 of a reverse conductivity type containing a low concentration impurity is formed. Further, a protective thermal oxide film 37 is provided on the surface of the source / drain diffusion layer 36 and the surface in the trench. Then, a protective insulating film 38 is formed so as to cover the protective thermal oxide film 37, the field oxide film 32, the gate electrode 34 and the like, and an interlayer insulating film 39 is formed on the protective insulating film 38.

Then, contact holes are formed in predetermined regions of the protective thermal oxide film 37, the protective insulating film 38, and the interlayer insulating film 39 on the source / drain diffusion layers 36,
Through this contact hole, the source / drain diffusion layer 36
Is provided.

The effect of the second embodiment is the same as that described in the first embodiment, and the leakage current at the PN junction is reduced. Also, in this case,
Since the element isolation region is formed in a trench structure, M
OS transistors will be further miniaturized.

Although the two embodiments have been described above, in particular, when the present invention is applied to a memory cell composed of one transfer transistor and one capacitor, the data retention characteristic thereof is remarkably improved. In both cases, it is easy to reduce the size (area) of the memory cell.

Further, the present invention is applied not only to the impurity diffusion layer region constituting the circuit node having the charge holding function in the floating state as described above, but also disclosed in, for example, JP-A-2-176810. The present invention is also effective when applied to a semiconductor device including the circuit described above. That is, if an impurity diffusion layer region is connected to an intermediate node of a high-resistance element alone or a hybrid series circuit with a transistor element and the leakage current of the PN junction is large, the output potential of the series circuit is deviated from a design value. May occur, leading to malfunction. This is because, when the output potential is determined by the ratio of the series impedance, the ratio is deviated by the leak current.

Therefore, the present invention is effective for a semiconductor device having a circuit for determining the potential of an internal node by a high impedance circuit.

[0066]

According to the present invention, the PN junction formed by the impurity diffusion layer of the conductivity type formed on one main surface of the semiconductor substrate of the conductivity type and the leakage current in the vicinity of the end of the field oxide film of the depletion layer are reduced. Without increasing the impurity diffusion layer, it is possible to suppress the shallow junction and spread in the horizontal direction of the impurity diffusion layer, and it is possible to miniaturize the MOS transistor and the element isolation, thereby contributing to the realization of an ultra-highly integrated semiconductor device.

Further, by disposing the PN junction of the fine MOS transistor and its depletion layer below the thermal oxide layer at the end of the field oxide film, the interface state density between the thermal oxide layer and the silicon substrate becomes very low. , PN junction leakage current can be minimized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a MOS transistor for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view of the MOS transistor in a manufacturing process order.

FIG. 3 is a flow chart of main steps of manufacturing the MOS transistor.

FIG. 4 is a cross-sectional view and an equivalent circuit diagram of a memory cell portion of a DRAM.

FIG. 5 is a graph showing a non-defective DRAM rate for explaining the effect of the present invention.

FIG. 6 is an enlarged schematic sectional view of a PN junction of a MOS transistor.

FIG. 7 is a sectional view of a MOS transistor illustrating a second embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a conventional technique in the order of manufacturing steps of a MOS transistor.

FIG. 9 is an enlarged schematic cross-sectional view of a PN junction of a conventional MOS transistor.

[Explanation of symbols]

1, 11, 31, 101 Silicon substrate 2, 12, 102 Field oxide film 3, 33, 103 Gate oxide film 4, 13, 13a, 13b, 34, 104 Gate electrode 5, 14, 35, 106 Side wall insulating film 6 , 36, 107 Source / drain diffusion layers 6a, 107a Diffusion layer ends 7, 17, 37 Protective thermal oxide films 8, 38, 108 Protective insulating films 9, 18, 39, 109 Interlayer insulating films 10, 40, 110 Drain electrode 15, 15a First diffusion layer 16, 16a Second diffusion layer 19 Lower electrode 20 Upper electrode 21 Bit line 22, 111 Field oxide film edge 23, 112 First depletion layer 24, 113 Second depletion layer 24a , 113a Depletion layer end 32 Element isolation insulating film TR Transfer transistor WL Word line BL Bit line CP Capacitor Sita N1 node

Claims (8)

(57) [Claims] 1. A semiconductor device comprising: a semiconductor substrate of one conductivity type; an impurity diffusion layer of a reverse conductivity type formed in a predetermined region of a semiconductor substrate of one conductivity type; an element isolation insulating film; and a CVD insulating film. An inclined surface inclined downward from an end of the flat portion, wherein the element isolation insulating film covers another portion of the inclined surface of the semiconductor substrate so as not to cover a part of the inclined surface of the semiconductor substrate. In the impurity diffusion layer, a PN junction between the semiconductor substrate and the impurity diffusion layer is provided at the other part of the slope portion of the semiconductor substrate, and a PN junction between the semiconductor substrate and the impurity diffusion layer is formed from the PN junction between the semiconductor substrate and the impurity diffusion layer. A depletion layer extending toward the impurity diffusion layer is formed to include a part of the slope part of the semiconductor substrate and the flat surface part so as to appear at the part of the slope part of the semiconductor substrate. , The CVD insulating film is A semiconductor device formed on the element isolation insulating film and the impurity diffusion layer, wherein a part of the slope portion of the semiconductor substrate is used to prevent the CVD insulating film from contacting the impurity diffusion layer. And a thermally oxidized silicon film inserted between the CVD insulating film and the impurity diffusion layer so as to cover the flat portion. 2. The semiconductor device according to claim 1, wherein said thermally oxidized silicon film is formed to have a thickness of 1 nm or more. 3. A semiconductor substrate comprising: an element isolation insulating film formed in a predetermined region of a semiconductor substrate of one conductivity type; an impurity diffusion layer formed in contact with the element isolation insulating film; and a CVD insulating film. Comprises a substantially flat first surface portion and a second surface portion inclined downward from an end of the first surface portion, wherein the element isolation insulating film is provided on the first surface portion of the semiconductor substrate and the second surface portion. The other part of the second surface part of the semiconductor substrate is covered so as not to cover a part of the second surface part, and the impurity diffusion layer is a PN between the semiconductor substrate and the impurity diffusion layer.
A depletion layer is provided on the second surface of the semiconductor substrate and extends from a PN junction between the semiconductor substrate and the impurity diffusion layer toward the impurity diffusion layer. A semiconductor device selectively formed on the semiconductor substrate so as to appear on a part of a surface portion of the semiconductor device, wherein the CVD insulating film is formed on the element isolation insulating film and the impurity diffusion layer; The CVD method is performed so as to cover a part of the second surface of the semiconductor substrate in order to prevent the CVD insulating film from contacting the impurity diffusion layer.
A semiconductor device comprising a thermally oxidized silicon film having a thickness of 1 nm or more formed by thin thermal oxidation inserted between an insulating film and the impurity diffusion layer. 4. The device isolation insulating film is formed so as to be buried in a concave portion of a semiconductor substrate, and the thermally oxidized silicon film is formed so as to be sandwiched between the semiconductor substrate and the device isolation insulating film. The semiconductor device according to claim 1, wherein: 5. The semiconductor device according to claim 1, wherein the impurity diffusion layer is connected to a floating conductive layer, and charges are stored in the conductive layer. 13. The semiconductor device according to item 9. 6. The semiconductor device according to claim 5, wherein said conductive layer forms a lower electrode of a capacitor. 7. A step of selectively forming an element isolation insulating film on a surface of a semiconductor substrate, and a step of forming a gate insulating film and a gate electrode on a surface of a predetermined region of the semiconductor substrate;
A step of forming an impurity diffusion layer in a self-aligned manner on the gate electrode and the element isolation insulating film, and a step of once removing the insulating film on the surface of the impurity diffusion layer to expose a junction of the impurity diffusion layer; and A method for manufacturing a semiconductor device, comprising: a step of thermally oxidizing a surface of the impurity diffusion layer to form a thin silicon oxide film; and a step of forming an interlayer insulating film on the thin silicon oxide film. 8. The thermal oxidation of the surface of the impurity diffusion layer is performed under reduced pressure C.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the method is performed in a VD furnace, and subsequently, the interlayer insulating film is formed in the same low-pressure CVD furnace.