JP3112243B2 - Photodiode array module - Google Patents
Photodiode array moduleInfo
- Publication number
- JP3112243B2 JP3112243B2 JP08018645A JP1864596A JP3112243B2 JP 3112243 B2 JP3112243 B2 JP 3112243B2 JP 08018645 A JP08018645 A JP 08018645A JP 1864596 A JP1864596 A JP 1864596A JP 3112243 B2 JP3112243 B2 JP 3112243B2
- Authority
- JP
- Japan
- Prior art keywords
- photodiode array
- signal
- light receiving
- readout circuit
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、光半導体回路の実
装構造に関し、詳しくは化合物半導体のフォトダイオー
ドを複数個アレイ状に配列したフォトダイオードアレイ
とそのフォトダイオードの信号を読み出しする集積回路
（シリコンのＩＣ）を一体化したモジュールにおける各
エレメントの実装構造の改善に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor circuit mounting structure, and more particularly, to a photodiode array in which a plurality of compound semiconductor photodiodes are arranged in an array and an integrated circuit (silicon) for reading out signals from the photodiodes. (IC) integrated with each other in an integrated module.
【０００２】[0002]
【従来の技術】従来よりフォトダイオードアレイのモジ
ュールとしては、図２に示すような構造のものがある。
図において、１はフォトダイオード２を複数個配列して
なるフォトダイオードアレイ、４はフォトダイオード２
の各出力信号を読み出す信号読み出し回路である。2. Description of the Related Art A conventional photodiode array module has a structure as shown in FIG.
In the figure, 1 is a photodiode array in which a plurality of photodiodes 2 are arranged, and 4 is a photodiode 2
Is a signal reading circuit for reading each output signal.
【０００３】フォトダイオードアレイ１と信号読み出し
回路４は例えばプリント基板上にそれぞれ取り付けら
れ、フォトダイオードアレイ１に設けられたフォトダイ
オード２の各引出し線３の一端と信号読み出し回路４に
設けられた各電極パッド５とがアルミワイヤ６によるボ
ンディングにより接続されている。The photodiode array 1 and the signal readout circuit 4 are mounted on, for example, a printed circuit board, and one end of each lead wire 3 of the photodiode 2 provided in the photodiode array 1 and each of the signal readout circuits 4 are provided. The electrode pads 5 are connected by bonding with aluminum wires 6.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うな構造では、電極パッド５の剥がれや、セカンドボン
ディング時のマイクロクラックの発生などがあり、歩留
りと信頼性に問題があった。However, in such a structure, there are problems such as peeling of the electrode pad 5 and occurrence of microcracks at the time of second bonding, resulting in problems in yield and reliability.
【０００５】また、半田バンプを用いたフリップチップ
ボンディングを利用する構造、例えば図３に示すような
構造のものがある。図３において、２つのチップ１０，
１１はその電極面１０ａ，１１ａが上面になるようにプ
リント基板１２にそれぞれ搭載され、この２つのチップ
にまたがると共に電極面が対向するようにして、接続用
チップ１３を搭載し、半田バンプ１４を介してチップ１
３をチップ１０，１１に接続している。なお、チップ１
０，１１の各電極とプリント基板１２のパッド１２ａ，
１２ｂ間はワイヤボンディングにより接続されている。Further, there is a structure utilizing flip chip bonding using solder bumps, for example, a structure as shown in FIG. In FIG. 3, two chips 10,
Numeral 11 is mounted on the printed circuit board 12 so that the electrode surfaces 10a and 11a are on the upper surface. The connection chip 13 is mounted so as to extend over the two chips and to have the electrode surfaces facing each other. Through chip 1
3 is connected to chips 10 and 11. Note that chip 1
0, 11 and the pads 12a of the printed circuit board 12,
12b are connected by wire bonding.
【０００６】しかしながら、図３に示すような構造にお
いても、２つのチップ１０，１１の厚さの違いにより接
続用のチップ１３と各チップとがうまく接続できないと
か、接続時に応力が残るとかの欠点があり、やはり信頼
性に問題が残る。However, even in the structure as shown in FIG. 3, the two chips 10 and 11 have different drawbacks in that the thickness of the two chips 10 and 11 does not allow the connection between the connection chip 13 and each of the chips to be well connected, or that stress remains during connection. There is still a problem in reliability.
【０００７】本発明の目的は、このような点に鑑み、フ
ォトダイオードアレイに半田バンプを介して信号読み出
し回路をフリップチップボンディングする簡単な実装構
造とすることにより、高い歩留りと高信頼性を確保する
と同時に図２に示すようなワイヤボンディング構造に比
べより小型化することのできるフォトダイオードアレイ
モジュールを提供することにある。In view of the foregoing, it is an object of the present invention to secure a high yield and high reliability by adopting a simple mounting structure in which a signal readout circuit is flip-chip bonded to a photodiode array via solder bumps. Another object of the present invention is to provide a photodiode array module which can be made smaller than the wire bonding structure as shown in FIG.
【０００８】[0008]
【課題を解決するための手段】このような目的を達成す
るために本発明では、上面に複数のフォトダイオードの
受光部が配列されると共に前記受光部の引出し線ならび
に信号線および電源線用の配線パターンが形成されたフ
ォトダイオードアレイをプリント配線されたプリント基
板に固定する。このフォトダイオードアレイの上に、一
方の面に電極面が形成され前記フォトダイオードの受光
部の信号を読み出すための信号読み出し回路をその電極
面が前記フォトダイオードアレイの上面に対向するよう
に配置し、半田バンプを介して電極面を前記フォトダイ
オードアレイのパターンに接続する。前記フォトダイオ
ードアレイと前記プリント基板とはワイヤボンディング
により接続する。In order to achieve the above object, according to the present invention, a plurality of light receiving portions of photodiodes are arranged on an upper surface, and a lead line of the light receiving portion, a signal line, and a power line are provided. The photodiode array on which the wiring pattern is formed is fixed to a printed circuit board on which printed wiring is performed. An electrode surface is formed on one surface of the photodiode array, and a signal readout circuit for reading out a signal from a light receiving portion of the photodiode is arranged such that the electrode surface faces the upper surface of the photodiode array. The electrode surface is connected to the pattern of the photodiode array via a solder bump. The photodiode array and the printed circuit board are connected by wire bonding.
【０００９】フォトダイオードアレイをプリント基板に
固定する構造により、その間の熱抵抗を低く抑えること
ができる。また、フォトダイオードアレイと信号読み出
し回路とを半田バンプを用いて接続することにより、電
極パッドの剥がれやマイクロクラックの発生を防ぐこと
ができる。さらに、接続のための電極パッドが上下に重
なる構造としたため、その分モジュール面積は縮小され
る。With the structure in which the photodiode array is fixed to the printed circuit board, the thermal resistance therebetween can be kept low. Further, by connecting the photodiode array and the signal readout circuit using solder bumps, peeling of the electrode pads and generation of microcracks can be prevented. Further, since the electrode pads for connection are vertically stacked, the module area is reduced accordingly.
【００１０】[0010]
【発明の実施の形態】以下図面を用いて本発明を詳しく
説明する。図１は本発明に係るフォトダイオードアレイ
モジュールの一実施例を示す構成図であり、同図（ａ）
は平面図、同図（ｂ）は側面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of a photodiode array module according to the present invention, and FIG.
Is a plan view, and FIG. 2B is a side view.
【００１１】図において、２０は化合物半導体のフォト
ダイオードアレイ、３０はシリコンＩＣ等の信号読み出
し回路、４０はプリント配線されたプリント基板であ
り、プリント基板４０の上にフォトダイオードアレイ２
０を搭載し、更にその上に信号読み出し回路３０を搭載
したものである。In FIG. 1, reference numeral 20 denotes a photodiode array of a compound semiconductor, 30 denotes a signal readout circuit such as a silicon IC, and 40 denotes a printed circuit board on which printed wiring is provided.
0, and a signal readout circuit 30 is further mounted thereon.
【００１２】フォトダイオードアレイ２０は、その上面
に複数のフォトダイオードの受光部２１ａ〜２１ｆ（総
称して２１とする）が配列されると共に、その配列の両
端には一方の電源線用とアナログ信号用とでなる一組の
配線パターン２３と、他方の電源線用とデジタル信号用
とでなる他の一組の配線パターン２４がそれぞれ配置さ
れている。各配線パターンの一端にあるパッドとプリン
ト基板４０の所定のパッドとはボンディングワイヤ５０
により接続される。なお、フォトダイオードアレイ２０
の下面は半田によりプリント基板４０に接続され固定さ
れている。信号読み出し回路３０は、その下面に電極面
が形成され、半田バンプ６０を介してフォトダイオード
アレイ２０のパターンとそれぞれ接続するようになって
いる。The photodiode array 20 has a plurality of photodiode light receiving portions 21a to 21f (generally 21) arranged on the upper surface thereof.
At the end is a pair of one for power line and one for analog signal.
Wiring pattern 23, for the other power supply line and for digital signals
And another set of wiring patterns 24
Have been. A pad at one end of each wiring pattern and a predetermined pad on the printed circuit board 40 are connected to a bonding wire 50.
Connected by The photodiode array 20
Is connected to the printed circuit board 40 by solder and fixed.
Have been. The signal reading circuit 30 has an electrode surface formed on a lower surface thereof, and is connected to a pattern of the photodiode array 20 via a solder bump 60.
【００１３】このような構造における実装手順を以下に
説明する。フォトダイオードアレイ２０に、配線パター
ン２３（図では４本）と他方の配線パターン２４（図で
は４本）を予め形成しておく。また信号読み出し回路３
０には、フォトダイオードアレイ２０の各配線パターン
およびフォトダイオードの受光部２１からの引出し線２
２ａ〜２２ｆ（総称して２２とする）とそれぞれ接続す
る半田バンプ６０を予め形成しておく。なお、二組の配
線パターン２３と２４は信号読み出し回路３０の長手方
向（フォトダイオードの受光部２１の配列方向に同じで
ある）の各端に分け、各半田バンプの個数をほぼ同数に
し、しかも左右対称となるように配置するのが望まし
い。このように配線パターン２３と２４を両端に分ける
とアナログ信号とデジタル信号の相互干渉を減ずること
ができる。また半田バンプ数を均等化し左右対称の配置
にすれば、フリップチップボンディングの際、引っ張り
応力に差異は生ぜず、信号読み出し回路３０のフォトダ
イオードアレイ上での回転も未然に防止することができ
る。 The mounting procedure in such a structure will be described below. A wiring pattern is provided on the photodiode array 20.
23 (four in the figure) and the other wiring pattern 24 (in the figure)
It is formed in advance four). Also, the signal readout circuit 3
0 indicates the wiring patterns of the photodiode array 20 and the lead lines 2 from the light receiving portion 21 of the photodiode.
Solder bumps 60 respectively connected to 2a to 22f (generally referred to as 22) are formed in advance. Note that the two sets
The line patterns 23 and 24 are in the longitudinal direction of the signal readout circuit 30.
Direction (the same as the array direction of the light receiving portions 21 of the photodiodes)
It is preferable that the solder bumps are divided into respective ends, and the number of the solder bumps is substantially the same, and furthermore, the solder bumps are arranged symmetrically. Thus, the wiring patterns 23 and 24 are divided into both ends.
Reduce interference between analog and digital signals
Can be. Also equalizes the number of solder bumps and arranges them symmetrically
If you use flip chip bonding, pull
There is no difference in stress, and the signal
Rotation on the ion array can be prevented beforehand.
You.
【００１４】このように形成されたフォトダイオードア
レイ２０の上面を上向きにしてプリント基板４０にダイ
ボンディングする。次に、信号読み出し回路３０を裏向
きにしフォトダイオードの受光部２１には被さらないよ
うにフォトダイオードアレイ２０の上面に重ね、半田バ
ンプ６０を介してフリップチップボンディングさせる。
このとき、信号読み出し回路３０のフォトダイオードア
レイ２０への重なり部分は、リフロー時にずれないよう
にするため、信号読み出し回路３０の下面の約２／３以
上とするのが望ましい。The photodiode array 20 thus formed is die-bonded to the printed circuit board 40 with the upper surface thereof facing upward. Next, the signal readout circuit 30 is placed face down on the upper surface of the photodiode array 20 so as not to cover the light receiving portion 21 of the photodiode, and flip chip bonding is performed via the solder bump 60.
At this time, it is desirable that the overlapping portion of the signal readout circuit 30 with the photodiode array 20 be about ／ or more of the lower surface of the signal readout circuit 30 so as not to shift during reflow.
【００１５】その後フォトダイオードアレイ２０の各パ
ターンとプリント基板４０のパターンとをワイヤボンデ
ィングする。なお、上記実施例では説明を簡潔にするた
め、フォトダイオードアレイ２０のフォトダイオードの
個数や配線パターンの本数などは実際のものより少なく
して概念的に説明してある。Thereafter, each pattern of the photodiode array 20 and the pattern of the printed circuit board 40 are wire-bonded. In the above embodiment, for simplicity, the number of photodiodes and the number of wiring patterns of the photodiode array 20 are conceptually described as being smaller than actual ones.
【００１６】このような構成において、フォトダイオー
ドアレイ２０の受光部２１ａに入射した光は光電流に変
換され、配線パターン２４のあるパターンを介して与え
られる制御クロックのあるタイミングに、半田バンプ６
０を介して信号読み出し回路３０に読み取られる。読み
取られた信号は別の半田バンプ６０を介して配線パター
ン２３の１つからワイヤ５０の１つおよびプリント基板
４０を経由して外部へ出力される。In such a configuration, the light incident on the light receiving portion 21a of the photodiode array 20 is converted into a photocurrent, and at a certain timing of a control clock given through a certain wiring pattern 24, the solder bump 6
The signal is read by the signal readout circuit 30 via 0. The read signal is output from one of the wiring patterns 23 to the outside via one of the wires 50 and the printed board 40 via another solder bump 60.
【００１７】次の制御クロック入力により信号読み出し
回路３０が駆動され、隣の受光部２１ｂの光電流が別の
半田バンプ、配線パターン、ワイヤを介して同様に読み
取られ、出力される。他の受光部２１ｃ〜２１ｆについ
ても上記と同様な動作によりその信号はプリント基板４
０より出力される。The signal read circuit 30 is driven by the next control clock input, and the photocurrent of the adjacent light receiving portion 21b is read and output in the same manner via another solder bump, wiring pattern, and wire. The signals of the other light receiving units 21c to 21f are also output by the same operation as described above,
Output from 0.
【００１８】なお、本発明の以上の説明は、説明および
例示を目的として特定の好適な実施例を示したに過ぎな
い。したがって本発明はその本質から逸脱せずに多くの
変更、変形をなし得ることは明らかである。It is to be noted that the above description of the present invention has been presented by way of illustration and example only of a particular preferred embodiment. Thus, it is apparent that the present invention can be modified and changed in many ways without departing from the essence thereof.
【００１９】[0019]
【発明の効果】以上説明したように本発明によれば、次
のような効果がある。（１） 半田バンプを用いたフリップチップボンディング
を採用することにより、ワイヤボンディング時に生ずる
電極パッドの剥がれやマイクロクラックの発生を防ぐこ
とができる。そのため高い歩留りと高信頼性を確保でき
る。（２） フォトダイオードアレイをプリント配線されたプ
リント基板に固定するため、その間の熱抵抗を低く抑え
ることができ、フォトダイオードアレイの温度制御を確
実に行うことができる。（３） フォトダイオードの受光部が信号読み出し回路と
重ならないように搭載しており、信号読み出し回路に受
光部用の窓などを形成する必要は全くない。（４） 接続のための電極パッドが上下に重なるため、そ
の分モジュール面積が減り、小型化できる。 （５）アナログ信号用とデジタル信号用の配線パターン
をフォトダイオードアレイの受光部の配列方向の両端側
に分けて形成したことにより、容易にアナログ信号とデ
ジタル信号の相互干渉を減少させることができる。According to the present invention as described above, the following effects can be obtained. (1) By employing flip chip bonding using solder bumps, it is possible to prevent peeling of electrode pads and occurrence of microcracks that occur during wire bonding. Therefore, high yield and high reliability can be secured. (2) Since the photodiode array is fixed to a printed circuit board on which printed wiring is performed, the thermal resistance during that period can be kept low, and the temperature control of the photodiode array can be reliably performed. (3) The light receiving portion of the photodiode is mounted so as not to overlap with the signal readout circuit, and there is no need to form a window for the light receiving portion in the signal readout circuit. (4) Since the electrode pads for connection overlap vertically, the module area can be reduced accordingly and the size can be reduced. (5) Since the wiring patterns for the analog signal and the digital signal are formed separately on both ends in the arrangement direction of the light receiving portion of the photodiode array, mutual interference between the analog signal and the digital signal can be easily reduced. .
【図１】本発明に係るフォトダイオードアレイモジュー
ルの一実施例を示す構成図FIG. 1 is a configuration diagram showing one embodiment of a photodiode array module according to the present invention.
【図２】従来のフォトダイオードアレイモジュールの一
例を示す構成図FIG. 2 is a configuration diagram showing an example of a conventional photodiode array module.
【図３】半田バンプを用いたフリップチップボンディン
グを利用する場合の一例を示す構成図である。FIG. 3 is a configuration diagram illustrating an example of a case where flip chip bonding using solder bumps is used.
２０ フォトダイオードアレイ ２１ 受光部 ２２ 引出し線 ２３，２４ 配線パターン ３０ 信号読み出し回路 ４０ プリント基板 ５０ ボンディングワイヤ ６０ 半田バンプ REFERENCE SIGNS LIST 20 photodiode array 21 light receiving section 22 lead line 23, 24 wiring pattern 30 signal readout circuit 40 printed circuit board 50 bonding wire 60 solder bump
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平１−243465（ＪＰ，Ａ) 特開 平２−26080（ＪＰ，Ａ) 特開 昭58−128762（ＪＰ，Ａ) 特開 平９−138325（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 31/00 - 31/0392 H01L 31/10 - 31/119 H01L 27/15 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-243465 (JP, A) JP-A-2-26080 (JP, A) JP-A-58-128762 (JP, A) JP-A-9- 138325 (JP, A) (58) Fields studied (Int. Cl. 7 , DB name) H01L 31/00-31/0392 H01L 31/10-31/119 H01L 27/15
Claims (3)
と共に、前記受光部の引出し線と、一方の電源線用とア
ナログ信号用の一組の配線パターンと、他方の電源線用
とデジタル信号用の一組の配線パターンがそれぞれ形成
され、下面が前記プリント基板に接続されるフォトダイ
オードアレイと、下面に電極面が形成され前記フォトダイオードの受光部
の信号を読み出すための信号読み出し回路を備え、 前記フォトダイオードアレイは、前記一方の電源線用と
アナログ信号用の一組の配線パターンと、他方の電源線
用とデジタル信号用の他の一組の配線パターンとが前記
受光部の配列の両端側に分かれて形成され、 前記信号読み出し回路は、前記フォトダイオードアレイ
上に載置されて半田バンプを介して電極面が前記フォト
ダイオードアレイの引出し線および各配線パターンにそ
れぞれ接続され、 前記プリント基板にはワイヤボンディングにより前記フ
ォトダイオードアレイが接続された ことを特徴とするフ
ォトダイオードアレイモジュール。1. A printed circuit board on which printed wiring is provided, a plurality of light receiving portions of photodiodes are arranged on an upper surface, a lead wire of the light receiving portion, and a set of one of a power supply line and an analog signal. A wiring pattern, a pair of wiring patterns for the other power supply line and a digital signal are respectively formed, and a photodiode array whose lower surface is connected to the printed circuit board ; Department
A signal readout circuit for reading out the signal of the one of the power supply lines.
One set of wiring patterns for analog signals and the other power supply line
And another set of wiring patterns for digital signals
The signal readout circuit is formed separately on both ends of an array of light receiving sections, and the signal readout circuit is
The electrode surface is placed on
Connect the lead wire of the diode array and each wiring pattern
Are connected to the printed circuit board by wire bonding.
A photodiode array module to which a photodiode array is connected .
３以上が前記受光部を避けてフォトダイオードアレイに
重なるように配置されたことを特徴とする請求項１記載
のフォトダイオードアレイモジュール。2. The signal reading circuit according to claim 2, wherein
The photodiode array module according to claim 1, wherein three or more are arranged so as to overlap with the photodiode array while avoiding the light receiving unit.
パターンの電極面が信号読み出し回路の長手方向の各端
に分けて形成されると共に、その各端の半田バンプの個
数がほぼ同数でかつ左右対称となるように配置されたこ
とを特徴とする請求項１記載のフォトダイオードアレイ
モジュール。3. The signal read circuit according to claim 2 , wherein the two sets of wirings are provided.
The electrode surface of the pattern is at each end in the longitudinal direction of the signal readout circuit.
And solder bumps at each end
The numbers should be approximately the same and symmetrical.
The photodiode array module according to claim 1, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08018645A JP3112243B2 (en) | 1996-02-05 | 1996-02-05 | Photodiode array module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08018645A JP3112243B2 (en) | 1996-02-05 | 1996-02-05 | Photodiode array module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09213989A JPH09213989A (en) | 1997-08-15 |
| JP3112243B2 true JP3112243B2 (en) | 2000-11-27 |
Family
ID=11977357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08018645A Expired - Fee Related JP3112243B2 (en) | 1996-02-05 | 1996-02-05 | Photodiode array module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3112243B2 (en) |
-
1996
- 1996-02-05 JP JP08018645A patent/JP3112243B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09213989A (en) | 1997-08-15 |
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