JPH0365666B2 - - Google Patents
Info
- Publication number
- JPH0365666B2 JPH0365666B2 JP57011958A JP1195882A JPH0365666B2 JP H0365666 B2 JPH0365666 B2 JP H0365666B2 JP 57011958 A JP57011958 A JP 57011958A JP 1195882 A JP1195882 A JP 1195882A JP H0365666 B2 JPH0365666 B2 JP H0365666B2
- Authority
- JP
- Japan
- Prior art keywords
- light
- receiving element
- integrated circuit
- semiconductor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 59
- 239000002184 metal Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000000919 ceramic Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000001816 cooling Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は半導体装置に係り、さらに具体的には
入射光に感応する受光素子を配設した半導体チツ
プと該受光素子を駆動するための回路素子、ある
いは受光素子からの光電変換された信号を処理す
るための回路素子をそなえた半導体集積回路チツ
プとをフエイスダウンボンデイングして一体化し
た半導体装置の構造に関するものである。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a semiconductor device, and more specifically to a semiconductor chip provided with a light-receiving element that is sensitive to incident light, and a circuit for driving the light-receiving element. The present invention relates to the structure of a semiconductor device in which elements or semiconductor integrated circuit chips equipped with circuit elements for processing photoelectrically converted signals from light receiving elements are integrated by face-down bonding.
(b) 従来技術と問題点
例えばInSbやPbSnTe等の化合物半導体チツプ
にダイオードアレイを形成して受光素子群を構成
し、それら各受光素子への入射光量に応じて光電
変換された出力信号の処理は、通常、例えばSiか
らなる半導体集積回路チツプに構成した信号処理
回路によつてなされる。またこのような受光素子
と信号処理回路との接続は、従来、ワイヤボンデ
イングもしくはフエイスダウンボンデイング等の
技術を用いてなされていた。すなわちワイヤボン
デイング法では受光素子を配設した半導体チツプ
と該受光素子からの信号を処理するための回路素
子をそなえた半導体集積回路チツプとを並置し、
それらをAuあるいはAl細線等のボンデイングワ
イヤでボンデイングするものであるが、ボンデイ
ング作業が煩雑であり、信頼性にも劣り、占有空
間も大きくなるという欠点があつた。一方フエイ
スダウンボンデイング法では前記受光素子を配設
した半導体チツプと信号処理回路を構成した半導
体集積回路チツプとを対向配置し、これらをフエ
イスダウンボンデイング用のIn等の金属バンプを
用いてボンデイングするようにしたものである
が、この方法では受光素子を配設した半導体チツ
プの裏面側から光を入射する必要があるので、そ
の半導体チツプを薄く研磨して入射光が受光素子
の感光部まで到達するように加工する必要があつ
た。また受光素子を電荷注入素子で構成し、例え
ばSiからなる半導体集積回路チツプに構成した駆
動回路で駆動するような場合には、その受光素子
を構成した半導体チツプチツプ裏面側からの光の
入射が不可能となり、ワイヤボンデイング法で行
わざるを得ないような場合も生じ、前述のような
ボンデイング作業の煩雑化や信頼性の低下等を招
く結果となつていた。(b) Conventional technology and problems For example, a diode array is formed on a compound semiconductor chip such as InSb or PbSnTe to form a group of light receiving elements, and processing of output signals that are photoelectrically converted according to the amount of light incident on each light receiving element. This is usually performed by a signal processing circuit configured on a semiconductor integrated circuit chip made of Si, for example. Further, such a connection between the light receiving element and the signal processing circuit has conventionally been made using a technique such as wire bonding or face-down bonding. In other words, in the wire bonding method, a semiconductor chip equipped with a light-receiving element and a semiconductor integrated circuit chip equipped with circuit elements for processing signals from the light-receiving element are juxtaposed.
These are bonded using a bonding wire such as a thin Au or Al wire, but the bonding work is complicated, the reliability is poor, and the space occupied is large. On the other hand, in the face-down bonding method, a semiconductor chip on which the light-receiving element is disposed and a semiconductor integrated circuit chip that constitutes a signal processing circuit are arranged facing each other, and these are bonded using metal bumps such as In for face-down bonding. However, in this method, it is necessary to enter the light from the back side of the semiconductor chip on which the light-receiving element is arranged, so the semiconductor chip is polished thin to allow the incident light to reach the photosensitive part of the light-receiving element. It was necessary to process it like this. Furthermore, when the light receiving element is constructed of a charge injection device and is driven by a drive circuit constructed on a semiconductor integrated circuit chip made of Si, for example, it is impossible for light to enter from the back side of the semiconductor chip that constitutes the light receiving element. However, there are cases where wire bonding has to be carried out, resulting in the above-mentioned complication of the bonding work and reduction in reliability.
(c) 発明の目的
本発明は前述の点に鑑みなされたもので、受光
素子を配設した半導体チツプと該受光素子を駆動
するための回路素子あるいは受光素子からの信号
を処理するための回路素子をそなえた半導体集積
回路チツプとをボンデイングワイヤを用いること
なく容易に一体構成し、もつて信頼性の高い、占
有空間も小さい、安価な半導体装置の提供を目的
とするものである。(c) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and includes a semiconductor chip on which a light-receiving element is arranged, a circuit element for driving the light-receiving element, or a circuit for processing a signal from the light-receiving element. The object of the present invention is to provide an inexpensive semiconductor device that is highly reliable, occupies a small space, and can be easily integrated with a semiconductor integrated circuit chip provided with elements without using bonding wires.
(d) 発明の構成
本発明は受光素子を配設した半導体チツプと該
受光素子を駆動するための回路素子あるいは受光
素子からの信号を処理するための回路素子をそな
えた半導体集積回路チツプとをフエイスダウンボ
ンデイングしてなる構成において、前記半導体集
積回路チツプにおける受光素子対応領域を避けた
領域に前記回路素子を形成するとともに当該半導
体集積回路チツプの少なくとも受光素子対応領域
に光入射用透光孔を設けたことを特徴とするもの
である。(d) Structure of the Invention The present invention comprises a semiconductor chip provided with a light receiving element and a semiconductor integrated circuit chip provided with a circuit element for driving the light receiving element or a circuit element for processing a signal from the light receiving element. In the structure formed by face-down bonding, the circuit element is formed in a region of the semiconductor integrated circuit chip that avoids the region corresponding to the light receiving element, and a transparent hole for light incidence is formed in at least the region corresponding to the light receiving element of the semiconductor integrated circuit chip. It is characterized by the fact that it has been provided.
(e) 発明の実施例
以下本発明の実施例につき図面を参照して説明
する。(e) Embodiments of the invention Examples of the invention will be described below with reference to the drawings.
第１図は本発明による半導体装置の１列構造を
説明するための概念的に示した要部断面図であ
り、第２図は第１図で示した半導体装置における
半導体集積回路チツプの構造を説明するための要
部平面図であつて、第１図と同等部分には同一符
号を付した。第１図において１は化合物半導体か
らなる半導体チツプであつて、その半導体チツプ
１の表面には図示を省略した受光素子群が構成し
てある。そして半導体チツプ１は、その裏面を例
えばセラミツク基板２表面の凹部に接着してあ
り、セラミツク基板２は実装用基台３上に固着し
てある。またセラミツク基板２表面には金属配線
４が配設されている。なお半導体チツプ１は、そ
の表面がセラミツク基板２表面とほぼ同一平面と
なるようにセラミツク基板１の凹部に接着してあ
る。そして受光素子を配設した半導体チツプ１の
表面に例えばInからなるフエイスダウンボンデイ
ング用の金属バンプ５を配設し、また各金属配線
４上にもボンデイング用の金属バンプ６が形成し
てある。そしてこれら金属バンプ５および６を用
いて半導体集積回路７が半導体チツプ１および金
属配線４の各々とボンデイングされている。その
半導体集積回路チツプ７は例えばSiからなり、そ
の表面つまり半導体チツプ１と対向する側には第
２図に示すごとく、受光素子対応領域を避けた領
域８（斜線で示した領域）に受光素子を駆動する
ための回路素子や受光素子からの信号を処理する
ための回路素子が形成してある。さらにその半導
体集積回路チツプ７の受光素子対応領域には光入
射用透光孔９が設けてある。そして領域８に形成
した集積回路と受光素子との間の信号は金属バン
プ５によつてボンデイングされた各ボンデイング
パツト５ａを通して入出力される。またその集積
回路への制御信号および電力供給や集積回路で処
理された信号の取出し等は金属バンプ６でボンデ
イングされた各ボンデイングパツド６ａを通して
なされる。そして第１図に示すような構成におい
て、光学レンズ１０を通した入射光１１を半導体
集積回路チツプ７に設けた透光孔９を通して半導
体チツプ１の表面に配設した受光素子へ入射する
ようになつている。 FIG. 1 is a conceptual cross-sectional view of a main part for explaining a single-row structure of a semiconductor device according to the present invention, and FIG. 2 shows a structure of a semiconductor integrated circuit chip in the semiconductor device shown in FIG. This is a plan view of main parts for explanation, and the same parts as in FIG. 1 are given the same reference numerals. In FIG. 1, reference numeral 1 denotes a semiconductor chip made of a compound semiconductor, and a group of light receiving elements (not shown) are formed on the surface of the semiconductor chip 1. As shown in FIG. The back surface of the semiconductor chip 1 is adhered to, for example, a recess on the surface of a ceramic substrate 2, and the ceramic substrate 2 is fixed onto a mounting base 3. Furthermore, metal wiring 4 is provided on the surface of the ceramic substrate 2. Note that the semiconductor chip 1 is bonded to the recessed portion of the ceramic substrate 1 so that its surface is substantially flush with the surface of the ceramic substrate 2. Metal bumps 5 made of, for example, In for face-down bonding are provided on the surface of the semiconductor chip 1 on which the light-receiving element is provided, and metal bumps 6 for bonding are also formed on each metal wiring 4. The semiconductor integrated circuit 7 is bonded to the semiconductor chip 1 and the metal wiring 4 using these metal bumps 5 and 6. The semiconductor integrated circuit chip 7 is made of Si, for example, and as shown in FIG. A circuit element for driving the light receiving element and a circuit element for processing the signal from the light receiving element are formed. Furthermore, a light-transmitting hole 9 for light incidence is provided in the area of the semiconductor integrated circuit chip 7 corresponding to the light-receiving element. Signals between the integrated circuit formed in the region 8 and the light receiving element are input and output through each bonding pad 5a bonded by the metal bump 5. Further, control signals and power supply to the integrated circuit, extraction of signals processed by the integrated circuit, etc. are performed through each bonding pad 6a bonded with metal bumps 6. In the configuration shown in FIG. 1, the incident light 11 passing through the optical lens 10 is made to enter the light receiving element disposed on the surface of the semiconductor chip 1 through the light transmission hole 9 provided in the semiconductor integrated circuit chip 7. It's summery.
次に第３図は本発明による半導体装置のその他
の実施例を説明するための概念的に示した要部断
面図であつて、第１図と同等部分には同一符号を
付した。図において１２は冷却基台であり、受光
素子を配設した半導体チツプ１はセラミツク基板
２の凹部に接着されて、冷却基台１２によつて所
定温度に冷却されるようになつている。また冷却
基台１２に連結されたコールドシールド１３が設
けられ、そのコールドシールド１３は半導体集積
回路チツプ７の裏面側と密着した形で配設され
る。そしてコールドシールド１３に設けた視野決
定用孔１４を通して入射光が半導体チツプ１表面
の受光素子に入射されるようになつている。この
ような構成においては、半導体集積回路チツプ７
がコールドシールド１３によつて冷却されるの
で、半導体集積回路チツプ７の発熱にもとづく不
要な背景信号を減少できる効果もある。 Next, FIG. 3 is a sectional view conceptually showing essential parts for explaining another embodiment of the semiconductor device according to the present invention, in which the same parts as in FIG. 1 are given the same reference numerals. In the figure, reference numeral 12 denotes a cooling base, and the semiconductor chip 1 on which the light receiving element is disposed is bonded to a recessed portion of the ceramic substrate 2, and is cooled to a predetermined temperature by the cooling base 12. Further, a cold shield 13 connected to the cooling base 12 is provided, and the cold shield 13 is disposed in close contact with the back side of the semiconductor integrated circuit chip 7. The incident light is made to enter the light-receiving element on the surface of the semiconductor chip 1 through the field-of-view determining hole 14 provided in the cold shield 13. In such a configuration, the semiconductor integrated circuit chip 7
Since the semiconductor integrated circuit chip 7 is cooled by the cold shield 13, unnecessary background signals due to heat generation of the semiconductor integrated circuit chip 7 can be reduced.
なお前述の実施例では半導体集積回路チツプ７
の形状が８角形のような多角形の場合について説
明したが、実装用基台や冷却基台の形状に応じて
４角形あるいは円形にすることもできる。また半
導体集積回路チツプには受光素子を駆動するため
の駆動回路素子と受光素子からの信号を処理する
ための信号処理回路素子とを構成するに限らず、
駆動回路素子または信号処理回路素子のいずれか
のみを構成することも可能である。 Note that in the above embodiment, the semiconductor integrated circuit chip 7
Although the case where the shape is a polygon such as an octagon has been described, it can also be made into a rectangular or circular shape depending on the shape of the mounting base and the cooling base. Furthermore, the semiconductor integrated circuit chip is not limited to configuring a driving circuit element for driving a light receiving element and a signal processing circuit element for processing a signal from the light receiving element.
It is also possible to configure only either the drive circuit element or the signal processing circuit element.
(f) 発明の効果
以上の説明から明らかなように本発明によれば
受光素子を配設した半導体チツプと駆動回路ある
いは信号処理回路を構成した半導体集積回路チツ
プとをボンデイングワイヤを用いることなく容易
に一体構成することができ、信頼性の高い、占有
空間の小さいコンパクトな半導体装置を安価に実
現できる利点を有する。(f) Effects of the Invention As is clear from the above description, according to the present invention, it is possible to easily connect a semiconductor chip on which a light receiving element is disposed and a semiconductor integrated circuit chip on which a drive circuit or a signal processing circuit is configured without using bonding wires. This has the advantage that a highly reliable, compact semiconductor device that occupies a small space can be realized at low cost.
第１図は本発明による半導体装置の１例構造を
説明するための概念的に示した要部断面図、第２
は第１図で示した半導体装置における半導体集積
回路チツプの構造を説明するための要部平面図、
第３図は本発明による半導体装置のその他の実施
例を説明するための概念的に示した要部断面図で
ある。
図において、１は受光素子を配設した半導体チ
ツプ、２はセラミツク基板、３は実装用基台、４
は金属配線、５および６は金属バンプ、５ａおよ
び６ａはボンデイングパツド、７は半導体集積回
路チツプ、８は回路素子を形成した領域、９は光
入射用透光孔、１０は光学レンズ、１１は入射光
１２は冷却基台、１３はコールドシールド、１４
は視野決定用孔をそれぞれ示す。
FIG. 1 is a conceptual cross-sectional view of main parts for explaining the structure of one example of a semiconductor device according to the present invention, and FIG.
is a plan view of a main part for explaining the structure of a semiconductor integrated circuit chip in the semiconductor device shown in FIG.
FIG. 3 is a conceptual sectional view of a main part for explaining another embodiment of the semiconductor device according to the present invention. In the figure, 1 is a semiconductor chip on which a light receiving element is arranged, 2 is a ceramic substrate, 3 is a mounting base, and 4
1 is a metal wiring, 5 and 6 are metal bumps, 5a and 6a are bonding pads, 7 is a semiconductor integrated circuit chip, 8 is a region where a circuit element is formed, 9 is a transparent hole for light incidence, 10 is an optical lens, 11 Incident light 12 is a cooling base, 13 is a cold shield, 14
indicate the visual field determination holes, respectively.
Claims (1)
子を駆動するための回路素子あるいは受光素子か
らの信号を処理するための回路素子をそなえた半
導体集積回路チツプとをフエイスダウンボンデイ
ングしてなる構成において、前記半導体集積回路
チツプにおける受光素子対応領域を避けた領域に
前記回路素子を形成するとともに当該半導体集積
回路チツプの少なくとも受光素子対応領域に光入
射用透光孔を設けたことを特徴とする半導体装
置。1. In a structure formed by face-down bonding of a semiconductor chip equipped with a light-receiving element and a semiconductor integrated circuit chip equipped with a circuit element for driving the light-receiving element or a circuit element for processing a signal from the light-receiving element. , a semiconductor characterized in that the circuit element is formed in a region of the semiconductor integrated circuit chip that avoids a region corresponding to a light receiving element, and a transparent hole for light incidence is provided in at least the region corresponding to the light receiving element of the semiconductor integrated circuit chip. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57011958A JPS58128762A (en) | 1982-01-27 | 1982-01-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57011958A JPS58128762A (en) | 1982-01-27 | 1982-01-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58128762A JPS58128762A (en) | 1983-08-01 |
| JPH0365666B2 true JPH0365666B2 (en) | 1991-10-14 |
Family
ID=11792121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57011958A Granted JPS58128762A (en) | 1982-01-27 | 1982-01-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58128762A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4710936B2 (en) * | 2008-08-29 | 2011-06-29 | 富士ゼロックス株式会社 | Exposure equipment |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1267468A (en) * | 1983-11-21 | 1990-04-03 | Hideaki Nishizawa | Optical device package |
| JPS648668A (en) * | 1987-06-30 | 1989-01-12 | Sharp Kk | Contact type image sensor |
| JPH02277273A (en) * | 1989-04-18 | 1990-11-13 | Fujitsu Ltd | Photodetector |
| JPH03259571A (en) * | 1990-03-08 | 1991-11-19 | Fujitsu Ltd | Photodetector |
| JP3017780B2 (en) * | 1990-09-10 | 2000-03-13 | 株式会社東芝 | Electronic endoscope imaging device |
| US5418566A (en) * | 1990-09-10 | 1995-05-23 | Kabushiki Kaisha Toshiba | Compact imaging apparatus for electronic endoscope with improved optical characteristics |
| US6351027B1 (en) * | 2000-02-29 | 2002-02-26 | Agilent Technologies, Inc. | Chip-mounted enclosure |
| FR2819940B1 (en) * | 2001-01-22 | 2003-10-17 | St Microelectronics Sa | METHOD FOR MANUFACTURING AN OPTICAL SEMICONDUCTOR PACKAGE AND OPTICAL SEMICONDUCTOR PACKAGE |
| JP2002329873A (en) * | 2001-05-01 | 2002-11-15 | Mitsubishi Electric Corp | Semiconductor module and semiconductor device |
| JP4191954B2 (en) * | 2002-05-17 | 2008-12-03 | 富士フイルム株式会社 | Imaging element mounting structure and imaging apparatus |
| FR3081256B1 (en) | 2018-05-18 | 2020-07-31 | St Microelectronics Grenoble 2 | OPTICAL TRANSMISSION / RECEPTION CIRCUIT |
| FR3081257B1 (en) * | 2018-05-18 | 2020-07-31 | St Microelectronics Grenoble 2 | OPTICAL TRANSMISSION / RECEPTION CIRCUIT |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5334210B2 (en) * | 1971-08-12 | 1978-09-19 | ||
| JPS5334213B2 (en) * | 1972-05-17 | 1978-09-19 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5624752Y2 (en) * | 1976-08-31 | 1981-06-11 | ||
| JPS5650008Y2 (en) * | 1976-08-31 | 1981-11-24 |
-
1982
- 1982-01-27 JP JP57011958A patent/JPS58128762A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5334210B2 (en) * | 1971-08-12 | 1978-09-19 | ||
| JPS5334213B2 (en) * | 1972-05-17 | 1978-09-19 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4710936B2 (en) * | 2008-08-29 | 2011-06-29 | 富士ゼロックス株式会社 | Exposure equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58128762A (en) | 1983-08-01 |
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