JP3109860B2 - Multi-layer wiring - Google Patents
Multi-layer wiringInfo
- Publication number
- JP3109860B2 JP3109860B2 JP03136102A JP13610291A JP3109860B2 JP 3109860 B2 JP3109860 B2 JP 3109860B2 JP 03136102 A JP03136102 A JP 03136102A JP 13610291 A JP13610291 A JP 13610291A JP 3109860 B2 JP3109860 B2 JP 3109860B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer wiring
- upper layer
- edge
- zigzag shape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、多層配線を必要とす
る電子デバイスの断線をなくすための効果的な手法を提
供し、電子デバイスの製造歩留及び信頼性の向上を目的
としている。BACKGROUND OF THE INVENTION The present invention aims to provide an effective method for eliminating disconnection of an electronic device requiring multilayer wiring, and to improve the production yield and reliability of the electronic device.
【０００２】[0002]
【従来の技術】ＩＣやＴＦＴ等の電子デバイスは、トラ
ンジスタのゲ−ト及びソ−スに信号を送るための配線が
必要であり、しかもそれらの配線が立体的に交差する多
層配線構造を用いなければならない場合が多数ある。2. Description of the Related Art Electronic devices such as ICs and TFTs require wiring for transmitting signals to gates and sources of transistors, and use a multilayer wiring structure in which these wirings cross three-dimensionally. There are many cases where it must be done.
【０００３】従来この種の装置において、多層配線は図
６及び図７に示すようなものがあり、例えば刊行物
（「三菱電機技報」Ｖｏｌ．６５・Ｎｏ．２・１９９１
・ｐ１４１〜１４５）に掲載されている。図６は従来の
電子デバイスの多層配線の要部を示す部分平面図、図７
は図６のＢ−Ｂ線断面図である。図において、１はＳｉ
ウェハ−等の半導体基板あるいはガラス等の透明絶縁基
板、２は電子デバイスを構成する絶縁膜や半導体膜、３
はＣｒやＡｌ等の金属で構成された下層配線、４はＳｉ
ＮやＳｉＯ2 等の絶縁膜、５はＣｒやＡｌ等の金属で構
成された上層配線、６は上層配線５の配線の脆弱な部分
である。Conventionally, in this type of apparatus, there are multilayer wirings as shown in FIGS. 6 and 7, and for example, a publication (“Mitsubishi Electric Technical Report”, Vol. 65, No. 2, 1991).
・ P.141-145). FIG. 6 is a partial plan view showing a main part of a multilayer wiring of a conventional electronic device.
FIG. 7 is a sectional view taken along line BB of FIG. 6. In the figure, 1 is Si
A semiconductor substrate such as a wafer or a transparent insulating substrate such as glass; 2, an insulating film or a semiconductor film constituting an electronic device;
Is a lower layer wiring made of metal such as Cr or Al, and 4 is Si
An insulating film such as N or SiO 2 , 5 is an upper layer wiring made of a metal such as Cr or Al, and 6 is a fragile portion of the wiring of the upper layer wiring 5.
【０００４】図６及び図７のような場合、下層配線３の
エッジ部の上に形成された上層配線は、平端部に形成さ
れたものと比べて膜が脆弱になっている。（図７の６）
特に上層配線５が真空蒸着のようなステップカバレージ
の悪い条件で成膜した時や下層配線３のパターンエッジ
がほとんど垂直に切り立っている場合には、脆弱になる
傾向が顕著になる。In the cases shown in FIGS. 6 and 7, the upper wiring formed on the edge of the lower wiring 3 has a weaker film than that formed on the flat end. (6 in FIG. 7 )
In particular, when the upper layer wiring 5 is formed under conditions with poor step coverage such as vacuum deposition or when the pattern edge of the lower layer wiring 3 is almost vertically steep, the tendency to become brittle becomes prominent.
【０００５】[0005]
【発明が解決しようとする課題】このような状態で、上
層配線５のパタ−ン形成（フォトエッチング）を行なう
と、上層配線の脆弱な部分６は、それ以外の部分よりも
エッチングレイトが大きいために、マウスホ−ルがで
き、さらには断線する。またエッチング時には断線しな
くても、その後の工程で受ける熱履歴により断線すると
か、デバイスとして完成したときに生じるストレスマイ
グレ−ションやまた電流を流したときに生じるエレクト
ロマイグレ−ション等により断線するといった不良が続
発していた。When the pattern of the upper wiring 5 is formed (photoetched) in such a state, the fragile portion 6 of the upper wiring has a larger etching rate than the other parts. Therefore, a mouse hole is formed, and furthermore, the wire is disconnected. Further, even if the wire is not broken during etching, the wire may be broken due to heat history received in a subsequent process, or may be broken due to stress migration generated when the device is completed or electromigration generated when a current is applied. The failure was one after another.
【０００６】この発明はこのような問題を解決するため
になされたもので、下層配線と上層配線が交差する部分
の下層配線のパタ−ンを工夫することにより、上層配線
の断線を防ぐことを目的としている。The present invention has been made in order to solve such a problem, and it is possible to prevent the disconnection of the upper layer wiring by devising the pattern of the lower layer wiring where the lower layer wiring and the upper layer wiring intersect. The purpose is.
【０００７】[0007]
【課題を解決するための手段】本発明に係る多層配線に
おいては、下層配線と実質的に直交する上層配線を有す
るものにおいて、下層配線のエッジ部は、上層配線のエ
ッジ部とほぼ直角に交差すると共に上層配線のエッジ部
間においてジグザグ形状に形成され、かつ上記ジグザグ
形状に沿った長さが上記上層配線の幅の２倍以上に形成
されているものである。According to the present invention, there is provided a multilayer wiring having an upper wiring substantially orthogonal to a lower wiring, wherein an edge of the lower wiring crosses an edge of the upper wiring substantially at right angles. It is formed in a zigzag shape between the edge portion of the upper wiring as well as, and the zigzag
The length along the shape is more than twice the width of the upper wiring
Those which are.
【０００８】[0008]
【作用】上記のように構成された多層配線は、ジグザク
部分のジグザグ形状に沿った長さが上層配線の幅の２倍
以上長いので、下層配線のエッジ部上の上層配線が脆弱
であって、上層配線形成時のエッチングにおいて、マウ
スホールができたとしても、そのマウスホールが上層配
線の幅方向に占める割合は小さい。したがって断線する
確率も１／２以下となりきわめて小さくなる。またその
後の工程で受ける熱履歴やデバイスとなったときに生じ
るストレスマイグレーションやエレクトロマイグレーシ
ョンに対しても、段差部の長さが長いために断線の発生
する確率はかなり低下する。因みに、実質的に直交する
上層配線と下層配線において、上層配線の幅をａ、本発
明による下層配線のジグザグ部分のジグザグ形状に沿っ
た長さをｂ×ａとすると、断線の発生する確率は、従来
の１／ｂ以下となる。In the multilayer wiring constructed as described above, the length of the zigzag portion along the zigzag shape is twice the width of the upper wiring.
Since the length is longer than the above , the upper wiring on the edge portion of the lower wiring is fragile, and even if a mouse hole is formed in the etching at the time of forming the upper wiring, the proportion of the mouse hole in the width direction of the upper wiring is small. Therefore, the probability of disconnection is １ ／ or less, which is extremely small. In addition, the probability of occurrence of disconnection is considerably reduced due to the long length of the stepped portion with respect to the thermal history received in the subsequent process and the stress migration and electromigration generated when the device is formed. By the way, in the upper layer wiring and the lower layer wiring which are substantially orthogonal, if the width of the upper layer wiring is a and the length along the zigzag shape of the zigzag portion of the lower wiring according to the present invention is b × a, the probability of occurrence of disconnection is , 1 / b or less of the conventional one.
【０００９】[0009]
【実施例】実施例１． 図１及び図２はこの発明の一実施例であり、図１は部分
平面図、そして図２は図１のＡ−Ａ線断面図である。図
において、１はＳｉウェハー等の半導体基板あるいはガ
ラス等の透明絶縁基板、２は電子デバイスを構成する絶
縁膜や半導体膜、３はＣｒやＡｌ等の金属で構成された
下層配線、４はＳｉＮやＳｉＯ2 等の層間絶縁膜、５は
ＣｒやＡｌ等の金属で構成され下層配線３と実質的に直
交する上層配線、６は上層配線５の脆弱な部分である。[Embodiment 1] 1 and 2 show an embodiment of the present invention. FIG. 1 is a partial plan view, and FIG. 2 is a sectional view taken along line AA of FIG. In FIG, 1 is a transparent insulating substrate such as a semiconductor substrate or a glass such as Si wafer, 2 constitutes the electronic device insulating film and the semiconductor film, 3 the lower layer wiring made of a metal such as Cr or Al, the 4 SiN and SiO 2 or the like of the interlayer insulating film, 5 is configuration a metal such as Cr and Al lower layer wiring 3 is substantially straight
The upper wiring 6 that intersects is a fragile portion of the upper wiring 5.
【００１０】以下、製造方法について説明する。まず半
導体基板あるいは透明絶縁基板１上に電子デバイスを構
成する絶縁膜あるいは半導体膜２を形成する。次に下層
配線となる金属膜３を成膜し、フォトエッチング法等の
方法でパターン形成する。このとき上層配線５と交差す
る部分の下層配線のエッジ部を、図１に示すように、上
層配線のエッジ部とほぼ直角に交差させると共に上層配
線のエッジ部間においてジグザグ形状にし、しかもこの
ジグザグ部分のジグザグ形状に沿った長さを、上層配線
５の幅に比べて十分長く、例えば上層配線５の幅の２倍
以上にする。その後、層間絶縁膜４を形成し、その上に
上層配線５を同様の方法で形成する。以上でこの発明の
主要部が形成される。Hereinafter, the manufacturing method will be described. First, an insulating film or a semiconductor film 2 constituting an electronic device is formed on a semiconductor substrate or a transparent insulating substrate 1. Next, a metal film 3 serving as a lower wiring is formed, and a pattern is formed by a method such as a photoetching method. The edge portion of the lower interconnect portions intersecting the upper wiring 5 this time, as shown in FIG. 1, the upper
Cross the wiring at almost right angles and
The zigzag shape is formed between the edge portions of the line , and the length of the zigzag portion along the zigzag shape is sufficiently longer than the width of the upper layer wiring 5, for example, twice or more the width of the upper layer wiring 5. After that, an interlayer insulating film 4 is formed, and an upper wiring 5 is formed thereon by a similar method. Thus, the main part of the present invention is formed.
【００１１】実施例２． なお、この発明においては、下層配線３と上層配線５が
交差する部分における下層配線のエッジ部が上層配線５
のエッジ部とほぼ直角に交差すると共に上層配線５のエ
ッジ部間においてジグザグ形状になっていればよく、図
１に示した形状の他に、図３、図４及び図５に示した形
状でもよく、さらに図１、図３、図４、及び図５の組み
合わせでもよく、そのジグザグ部の長さが、上層配線の
幅に対して長ければ上記実施例と同様の効果が得られ
る。 Embodiment 2 FIG. In the present invention, the edge of the lower wiring at the intersection of the lower wiring 3 and the upper wiring 5 corresponds to the upper wiring 5.
Crosses the edge portion of the upper layer wiring 5 almost at a right angle.
The zigzag shape between the edge portions is sufficient, and in addition to the shape shown in FIG. 1, the shape shown in FIGS. 3, 4 and 5 may be used. Further, FIGS. 1, 3, 4 and 5 The combination shown in FIG. 5 may be used. If the length of the zigzag portion is longer than the width of the upper wiring, the same effect as in the above embodiment can be obtained .
【００１２】[0012]
【発明の効果】以上のように、この発明によれば、下層
配線と実質的に直交する上層配線を有するものにおい
て、下層配線のエッジ部は、上層配線のエッジ部とほぼ
直角に交差すると共に上層配線のエッジ部間においてジ
グザグ形状に形成され、かつ上記ジグザグ形状に沿った
長さが上記上層配線の幅の２倍以上に形成されているの
で、そのジグザグ部のジグザグ形状に沿った長さが、上
層配線の幅に対して長く、上層配線が断線する確率を１
／２以下にすることができる。As described above, according to the present invention, in a semiconductor device having an upper wiring that is substantially orthogonal to the lower wiring, the edge of the lower wiring crosses the edge of the upper wiring substantially at a right angle. It is formed in a zigzag shape between the edge portions of the upper layer wiring , and conforms to the zigzag shape.
Since the length is formed to be at least twice the width of the upper wiring, the length of the zigzag portion along the zigzag shape is longer than the width of the upper wiring, and the probability of disconnection of the upper wiring is one.
/ 2 or less .
【図１】この発明の一実施例による多層配線の要部を示
す部分平面図である。FIG. 1 is a partial plan view showing a main part of a multilayer wiring according to an embodiment of the present invention.
【図２】図１のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】この発明の他の実施例による多層配線の要部を
示す部分平面図である。FIG. 3 is a partial plan view showing a main part of a multilayer wiring according to another embodiment of the present invention.
【図４】この発明のさらに他の実施例による多層配線の
要部を示す部分平面図である。FIG. 4 is a partial plan view showing a main part of a multilayer wiring according to still another embodiment of the present invention.
【図５】この発明のさらに他の実施例による多層配線の
要部を示す部分平面図である。FIG. 5 is a partial plan view showing a main part of a multilayer wiring according to still another embodiment of the present invention.
【図６】従来の多層配線の要部を示す部分平面図であ
る。FIG. 6 is a partial plan view showing a main part of a conventional multilayer wiring.
【図７】図６のＢ−Ｂ線断面図である。FIG. 7 is a sectional view taken along the line BB of FIG. 6;
１ 基板 ２ 電子デバイスを構成する絶縁膜や半導体膜 ３ 下層配線 ４ 層間絶縁膜 ５ 上層配線 ６ 上層配線５の脆弱な部分 DESCRIPTION OF SYMBOLS 1 Substrate 2 Insulating film and semiconductor film which comprises an electronic device 3 Lower wiring 4 Interlayer insulating film 5 Upper wiring 6 Vulnerable part of upper wiring 5
Claims (1)
配線上に絶縁膜を介して設けられ下層配線と実質的に直
交する上層配線とを有する多層配線において、上記下層
配線のエッジ部は、上記上層配線のエッジ部とほぼ直角
に交差すると共に上層配線のエッジ部間においてジグザ
グ形状に形成され、かつ上記ジグザグ形状に沿った長さ
が上記上層配線の幅の２倍以上に形成されていることを
特徴とする多層配線。An edge portion of the lower wiring in a multilayer wiring having a lower wiring formed on a substrate and an upper wiring provided on the lower wiring via an insulating film and substantially orthogonal to the lower wiring. Is formed in a zigzag shape between the edge portions of the upper layer wiring at substantially right angles with the edge portions of the upper layer wiring , and has a length along the zigzag shape.
Is formed to be at least twice the width of the upper layer wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03136102A JP3109860B2 (en) | 1991-06-07 | 1991-06-07 | Multi-layer wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03136102A JP3109860B2 (en) | 1991-06-07 | 1991-06-07 | Multi-layer wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04360534A JPH04360534A (en) | 1992-12-14 |
| JP3109860B2 true JP3109860B2 (en) | 2000-11-20 |
Family
ID=15167326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03136102A Expired - Lifetime JP3109860B2 (en) | 1991-06-07 | 1991-06-07 | Multi-layer wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3109860B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100776503B1 (en) * | 2002-12-02 | 2007-11-15 | 엘지.필립스 엘시디 주식회사 | Structure of lcd pixel |
| JP2005164854A (en) | 2003-12-01 | 2005-06-23 | Nec Lcd Technologies Ltd | Liquid crystal display device |
| KR101244656B1 (en) | 2006-06-19 | 2013-03-18 | 엘지디스플레이 주식회사 | Liquid Crystal Display |
-
1991
- 1991-06-07 JP JP03136102A patent/JP3109860B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04360534A (en) | 1992-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5472889A (en) | Method of manufacturing large-sized thin film transistor liquid crystal display panel | |
| JP3109860B2 (en) | Multi-layer wiring | |
| US5498571A (en) | Method of manufacturing a semiconductor device having reliable multi-layered wiring | |
| US7847403B2 (en) | Semiconductor device having no cracks in one or more layers underlying a metal line layer | |
| US6133141A (en) | Methods of forming electrical connections between conductive layers | |
| JPS59195844A (en) | Manufacture of semiconductor device | |
| JPH08204002A (en) | Manufacturing method for semiconductor integrated circuit device | |
| US5282922A (en) | Hybrid circuit structures and methods of fabrication | |
| JP2797929B2 (en) | Semiconductor device | |
| JPH1167908A (en) | Semiconductor device and manufacture thereof | |
| JPH04214630A (en) | Manufacture of semiconductor device | |
| KR100197129B1 (en) | Forming method for metal wiring in semiconductor device | |
| KR890004875B1 (en) | Manufacture of electrode on semiconductor body | |
| JPH01270248A (en) | Semiconductor device | |
| JPS60124950A (en) | Semiconductor device having multilayer interconnection structure | |
| JPS62281468A (en) | Semiconductor device | |
| JPH04373151A (en) | Semiconductor device | |
| JPS6378553A (en) | Semiconductor device | |
| JPS61208851A (en) | Manufacture of semiconductor device | |
| JPS61114557A (en) | Manufacture of semiconductor device | |
| JPS62291147A (en) | Semiconductor device | |
| JPS6132555A (en) | Formation of multilayer interconnection structure | |
| JPH11297697A (en) | Semiconductor device | |
| JPH11111849A (en) | Semiconductor device | |
| JPH04254330A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313114 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070914 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080914 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080914 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090914 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090914 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100914 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110914 Year of fee payment: 11 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110914 Year of fee payment: 11 |