JP3103610B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device such as a DRAM (Dynamic RAM), and more particularly to a method of forming an interlayer insulating film on a semiconductor substrate having a plurality of memory cells separated from each other by a selective oxide film. The present invention relates to a method for forming a substrate contact window reaching each of a plurality of memory cells by selectively removing an interlayer insulating film by etching after being deposited on one surface.

[0002]

2. Description of the Related Art A reduction in the area of a memory cell is one of important issues for increasing the density of a semiconductor memory device such as a DRAM. In order to reduce the memory cell area, it is fundamental to reduce the pattern size, but it can be said that the current pattern size has almost reached the minimum size limit of the current photolithography technology. In particular, it is difficult to reduce the size of a hole pattern such as a substrate contact window formed in an interlayer insulating film on a semiconductor substrate in order to provide a storage electrode in contact with each of a plurality of memory cells as compared with a line pattern. An improvement in the technology for forming a substrate contact window is one of the issues in reducing the area of a memory cell.

A method for forming a substrate contact window in a conventional method for manufacturing a semiconductor memory device will be described below with reference to the drawings. FIG. 4 is a plan view of a DRAM memory cell showing one process of a conventional method for manufacturing a semiconductor memory device.
This shows a state where a substrate contact window is formed in a silicon oxide film as an interlayer insulating film by etching using a photoresist as a mask. FIG. 5 is a cross-sectional view in the order of steps in the XX ′ portion and the YY ′ portion of FIG. 4 in the left diagram and the right diagram, respectively, and the left diagram and the right diagram in FIG. 3 shows a state corresponding to the state shown in FIG.

First, as shown in the left and right views of FIG. 5A, a selective oxidation film 2 is formed by selectively oxidizing the surface of a silicon substrate 1 and a plurality of memories separated from each other by the selective oxide film. The cell 3 is formed on the surface of the silicon substrate 1, and a transistor is formed in each of the plurality of memory cells 3. Reference numeral 4 denotes a word line formed of a polysilicon film constituting a transfer gate, which is formed in common on each of the plurality of memory cells 3 two by two (see FIG. 4). Then, the selective oxide film 2 and all the memory cells 3
And the LPCVD method (pressure reduction CV
D method), a silicon oxide film 6 as an interlayer insulating film is deposited on one surface.

Next, as shown in the left and right views of FIG. 5B, a pattern of a photoresist 7 is formed on the silicon oxide film 6 as an etching mask for forming a substrate contact window. The pattern of the photoresist 7 is a pattern having discrete window-shaped openings 8, and each opening 8 is provided for each region where a substrate contact window of each of the plurality of memory cells 3 is to be formed.

Further, using the photoresist 7 as a mask,
By selectively removing the silicon oxide film 6 as an interlayer insulating film by anisotropic dry etching using a gas plasma of CHF _{3/0 2,} to obtain a substrate contact window 9 to reach each of the plurality of memory cells 3. FIGS. 4 and 5C show the state in which the unnecessary photoresist 7 is removed.

After the substrate contact window 9 is formed as described above, polysilicon is deposited by LPCVD and photolithography and dry etching are applied, as shown in the left and right views of FIG. Thus, the pattern of the storage electrode 10 that contacts each of the memory cells 3 can be formed at each position of the substrate contact window 9.

[0008]

In the above-described conventional method of forming the substrate contact window 9, a discrete window-like opening 8 is formed for each region of the plurality of memory cells 3 where the substrate contact window is to be formed. Since the pattern of the photoresist 7 is used, the substrate contact window 9 in the direction of the word line 4 is used.
, That is, the contact size between the memory cell 3 and the storage electrode 10 cannot be made smaller than 0.8 μm, and the memory cell pitch in the direction of the word line 4 cannot be made smaller than 2.0 μm.

To explain this situation in detail, in the current photolithography technology, the critical minimum dimension of a hole pattern, that is, the minimum dimension that can be stably obtained in mass production is:
It is about 0.8 μm. That is, the size of the opening 8 of the photoresist 7 in the direction of the word line 4, that is, the size of the substrate contact window 9 in the same direction cannot be made smaller than 0.8 μm. Even when the size of the substrate contact window 9 in the direction of the word line 4 is set to the limit minimum dimension of 0.8 μm in order to minimize the memory cell area, the width of the storage electrode 10 is zero on both sides from the substrate contact window 9. 1.2 μm because it is necessary to allow a normal mask alignment margin of 2 μm.
That is all. Moreover, since a gap of at least 0.8 μm is required between adjacent storage electrodes 10, the interval between two adjacent memory cells 3 in the direction of the word line 4, that is, the memory cell pitch is smaller than 2.0 μm. It cannot be made smaller. In other words, it is impossible to realize a memory cell pitch smaller than 2.0 μm with the above-mentioned conventional technology, and this is one of the factors that hinder the reduction of the memory cell area and the increase in the density of the semiconductor memory device. Was.

An object of the present invention is to partially reduce the size of a substrate contact window to reduce the memory cell pitch by partially reducing the size of a substrate contact window, thereby reducing the area of a memory cell and, consequently, the semiconductor memory device. The aim is to increase the density.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is directed to a photoresist having a discrete window-shaped opening in each region where a substrate contact window of each memory cell is to be formed. Instead of the pattern, after forming a photoresist pattern having a groove-like opening that continuously connects the region where the substrate contact window is to be formed,
This adopts a configuration in which a substrate contact window is formed by etching.

Specifically, the invention of claim 1 is
Forming a plurality of memory cells and a selective oxide film for separating each of the plurality of memory cells from each other on the surface of the semiconductor substrate, depositing an interlayer insulating film to cover both the plurality of memory cells and the selective oxide film, A photoresist pattern having a groove-shaped opening that continuously connects regions where a substrate contact window of each of a plurality of memory cells is to be formed is formed on an interlayer insulating film, and is selected by etching using the photoresist as a mask. This adopts a configuration in which a substrate contact window reaching each of a plurality of memory cells is formed by selectively removing an interlayer insulating film while leaving an oxide film.

According to a second aspect of the present invention, a two-layer film having a silicon nitride film as a lower layer and a silicon oxide film as an upper layer is used as an interlayer insulating film, and the interlayer insulating film is etched by dry etching using gas plasma. In this configuration, the end point of the dry etching is detected by detecting the emission spectrum of nitrogen from the lower silicon nitride film.
According to a third aspect of the present invention, the thickness of the silicon nitride film as a lower layer of the interlayer insulating film is set to 20 nm or more, and the fourth aspect of the present invention sets the area of the opening of the photoresist to 20% of the total area of the photoresist. Each of the above configurations is adopted.

[0014]

According to the first aspect of the present invention, in the direction in which the groove-shaped opening of the photoresist extends, all the interlayer insulating film is etched, and each of the plurality of memory cells is exposed over the entire width. At this time, the distance between the adjacent selective oxide films, that is, the element region width determined by the selective oxidation becomes the size of the substrate contact window, that is, the contact size. That is, the contact size is not limited by the pattern of the photoresist for etching. Therefore, if the element region width is reduced when the selective oxide film is formed, the contact size can be reduced, and the memory cell pitch can be reduced.

According to the second aspect of the present invention, a silicon nitride film is deposited so as to cover both the plurality of memory cells and the selective oxide film, and a silicon oxide film is further deposited on the silicon nitride film. Forming a photoresist pattern having the groove-shaped openings on an interlayer insulating film composed of a two-layer film of a silicon nitride film and a silicon oxide film, and performing dry etching using the photoresist as a mask to form a two-layer interlayer. A substrate contact window is formed by selectively removing the insulating film. In this dry etching, the end point of the etching is detected by detecting the emission spectrum of nitrogen from the underlying silicon nitride film, and the silicon nitride film is completely removed by overetching after the detection of the end point. At this time, by controlling the over-etching time, film loss due to etching of the selective oxide film serving as the base is eliminated.

According to the third aspect of the present invention, the thickness of the silicon nitride film as a lower layer of the interlayer insulating film is set to 20 nm or more. Since the silicon nitride film is removed by overetching after detecting the end point, the silicon nitride film needs to have a minimum thickness of 20 nm in order to prevent the underlying selective oxide film from being reduced in film thickness.

In the conventional method using a photoresist pattern having discrete window-shaped openings, the ratio of the opening area to the entire area of the photoresist, that is, the opening ratio is only about 2-3%. Even when a two-layered film having a silicon nitride film as a lower layer and a silicon oxide film as an upper layer is deposited as an interlayer insulating film, the emission spectrum intensity of nitrogen is very small, and stable detection of the end point of etching cannot be performed. However, according to the invention of claim 4, a groove-shaped opening that continuously connects the regions where the substrate contact windows of the plurality of memory cells are to be formed is provided in the photoresist,
Moreover, since the aperture ratio is set to 20% or more, the exposed area of the silicon nitride film during the etching increases, and the end point of the etching can be stably detected through the detection of the emission spectrum of nitrogen from the silicon nitride film.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a DRAM memory cell showing one process of a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, in which an interlayer insulating film composed of a silicon nitride film and a silicon oxide film is formed. This figure shows a state in which a photoresist pattern having a groove-shaped opening on the top is formed. FIG. 2 is a cross-sectional view in the order of steps taken along the line XX ′ and the line YY ′ in FIG. 1, and the left and right views in FIG. 3 shows a state corresponding to the state shown in FIG.

First, as shown in the left and right views of FIG. 2A, the surface of the silicon substrate 1 is selectively oxidized to selectively oxide the film 2 and a plurality of memories separated from each other by the selective oxide film. The cell 3 is formed on the surface of the silicon substrate 1, and a transistor is formed in each of the plurality of memory cells 3. Reference numeral 4 denotes a word line formed of a polysilicon film constituting a transfer gate, which is partially formed on each of the plurality of memory cells 3 in a partially common manner (see FIG. 1). Then, the selective oxide film 2 and all the memory cells 3
And an interlayer insulating film composed of a two-layer film having a 20 nm-thick silicon nitride film 5 as a lower layer and a 150 nm-thick silicon oxide film 6 as an upper layer so as to cover the word lines 4.
It is deposited on one side by the method.

Next, as shown in FIGS. 1 and 2B, a silicon nitride film 5 and a silicon oxide film 6 are formed.
A pattern of a photoresist 7 is formed as an etching mask for forming a substrate contact window on the interlayer insulating film composed of the two-layer film. The pattern of the photoresist 7 has a groove-shaped opening 8 that continuously connects the regions where the substrate contact windows 9 of the memory cells among the plurality of memory cells 3 arranged in the direction of the word line 4 are to be formed. It is a pattern.

Further, using the photoresist 7 as a mask,
By selectively removing the interlayer insulating film having a two-layered film of a silicon nitride film 5 and the silicon oxide film 6 while leaving the selective oxide film 2 by anisotropic dry etching using a gas plasma of CHF _{3/0 2,} A substrate contact window 9 reaching each of the plurality of memory cells 3 arranged in the direction of the word line 4 is obtained. The state in which the unnecessary photoresist 7 is removed is shown in the left and right views of FIG.

In this dry etching, the end point of the etching is detected by detecting the emission spectrum of nitrogen from the underlying silicon nitride film 5, and the silicon nitride film 5 is completely removed by overetching after the detection of the end point. At this time, if the thickness of the silicon nitride film 5 is set to 20 nm or more, it is possible to prevent the selective oxide film 2 serving as the base from being reduced in film thickness by controlling the over-etching time. If the ratio of the area of the opening 8 to the entire area of the photoresist 7, that is, the opening ratio is set to 20% or more, a large exposed area of the silicon nitride film 5 can be obtained during etching. The end point of the etching can be stably detected through the detection of the emission spectrum of nitrogen.

After the substrate contact window 9 is formed as described above, polysilicon is deposited by LPCVD and photolithography and dry etching are applied, as shown in the left and right views of FIG. Thus, the pattern of the storage electrode 10 that contacts each of the memory cells 3 can be formed at each position of the substrate contact window 9.

As described above, according to the method of this embodiment, when the substrate contact window 9 is viewed in the direction of the word line 4 as shown in the right diagram of FIG.
The interlayer insulating film composed of a two-layer film including the silicon oxide film 6 and the silicon oxide film 6 is etched without leaving the selective oxide film 2 alone, and each of the plurality of memory cells 3 is exposed over the entire width. At this time, the distance between the adjacent selective oxide films 2, that is, the element region width determined by the selective oxidation becomes the size of the substrate contact window 9 in the direction of the word line 4, that is, the contact size. That is, the contact size is not limited by the pattern of the photoresist 7 for etching. Therefore, if the element region width is reduced when the selective oxide film 2 is formed, the contact size can be reduced, and the memory cell pitch can be reduced.

FIG. 3 shows that a small gap is formed on the surface of the silicon substrate 1 by selective oxidation on the surface of the silicon substrate 1 in order to realize a small element region width before reaching the state shown in the right diagram of FIG. FIG. 4 is a cross-sectional view in a process order showing a method for forming a selective oxide film 2 in FIG.

First, as shown in FIG. 3A, a silicon oxide film 11 and a silicon nitride film 1
2 are sequentially formed, and a pattern of a photoresist 13 for determining a selective oxidation region is formed. The pattern width of the photoresist 13 is set to the above-mentioned 0.8 μm which is the minimum dimension of the current photolithography technology.

Next, the silicon nitride film 12 is patterned by etching using the photoresist 13 as a mask. FIG. 4B shows a state in which the unnecessary photoresist 13 has been removed. The pattern width of the silicon nitride film 12 is
This is 0.8 μm, which is the same as the pattern width of the photoresist 13.

Further, the selective oxidation film 2 is formed by selectively oxidizing the surface of the silicon substrate 1 using the patterned silicon nitride film 12 as an oxidation mask. FIG. 3C shows a state in which the silicon nitride film 12 and the silicon oxide film 11 are removed after the formation of the selective oxide film 2. At the time of this selective oxidation, an oxide film enters below the pattern of the silicon nitride film 12 (bird's beak). If the size of the bird's beak is 0.2 μm on one side, the distance between adjacent selective oxide films 2, that is, the element region width is 0.4 μm.
m.

As described above, according to the present embodiment, the element region width is the size of the substrate contact window 9 in the direction of the word line 4, that is, the contact size. That is, 0.4μ
m contact size can be realized.

The memory cell pitch in this case is calculated in the same manner as in the case of the above-mentioned prior art. The width of the storage electrode 10 is at least 0.8 μm on both sides from the substrate contact window 9 with an ordinary mask alignment margin of 0.2 μm. If a gap of 0.8 μm is provided between adjacent storage electrodes 10, the interval between two adjacent memory cells 3 in the direction of the word line 4, that is, the memory cell pitch is 1.6 μm. That is, according to the present embodiment, the memory cell pitch can be reduced by 0.4 μm as compared with the related art, and the memory cell area is reduced by 2 μm.
A reduction of 0% can be realized.

[0031]

As described above, according to the first aspect of the present invention, there is provided a photoresist pattern having a groove-like opening which continuously connects regions where a substrate contact window of each memory cell is to be formed. Is formed and then a substrate contact window is formed by etching, so that the distance between adjacent selective oxide films, that is, the element region width determined by selective oxidation becomes the contact size,
The contact size is not limited by the pattern of the photoresist for etching. Therefore, a small contact size which cannot be realized conventionally can be realized only by reducing the element region width when forming the selective oxide film, and the memory cell pitch can be reduced. In other words, it is possible to reduce the memory cell area and increase the density of the semiconductor memory device while partially following the conventional photolithography technology.

According to the second aspect of the present invention, the interlayer insulating film is a two-layer film of a silicon nitride film (lower layer) and a silicon oxide film (upper layer), and gas plasma is used for etching the interlayer insulating film. Since the dry etching method is adopted and the end point of the dry etching is detected by detecting the emission spectrum of nitrogen from the lower silicon nitride film, the control of the etching process is facilitated. At this time, the silicon nitride film is completely removed by over-etching after the end point is detected. However, by controlling the over-etching time, it is possible to eliminate the film loss due to the etching of the underlying selective oxide film.

According to the third aspect of the present invention, since the thickness of the silicon nitride film as the lower layer of the interlayer insulating film is set to 20 nm or more, the silicon nitride film is formed by over-etching after detecting the end point of dry etching. At the time of complete removal, the underlying selective oxide film is not immediately etched, so that a decrease in the film due to the selective oxide film etching can be prevented.

According to the fourth aspect of the present invention, not only is the photoresist provided with a groove-shaped opening which continuously connects the regions where the substrate contact windows of the plurality of memory cells are to be formed, but also the opening of the photoresist is formed. , The exposed area of the silicon nitride film during dry etching is increased, and the etching through the detection of the emission spectrum of nitrogen from the silicon nitride film is performed. End point detection is stabilized.

[Brief description of the drawings]

FIG. 1 is a plan view of a DRAM memory cell showing one process of a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, and illustrates a structure of an interlayer insulating film including a two-layer film of a silicon nitride film and a silicon oxide film. This figure shows a state in which a photoresist pattern having a groove-shaped opening on the top is formed.

FIG. 2 is a XX ′ part and a Y part of FIG. 1 respectively.
FIG. 4A is a sectional view in the order of steps in a portion Y- ′, wherein FIG. (B) shows a state corresponding to the state shown in FIG. 1 in which a photoresist pattern having a groove-like opening is formed on the interlayer insulating film, and (C) shows a state corresponding to the state shown in FIG. A state in which a substrate contact window is formed by selectively removing an interlayer insulating film while leaving a selective oxide film by etching using the photoresist as a mask. FIG. 4D shows a state in which each of the memory cells is contacted using the substrate contact window. The state where the pattern of the storage electrode is formed
Each is shown.

3A to 3C are cross-sectional views in a process order showing a method for forming a selective oxide film at minute intervals on the surface of a silicon substrate before reaching the state of FIG. 2A, wherein FIG. (B) shows a state in which a silicon oxide film and a silicon nitride film are sequentially formed and then a photoresist pattern for determining an oxidized region is formed, and (B) shows a state in which the silicon nitride film is patterned by etching using the photoresist as a mask. (C) shows a state in which the silicon nitride film and the silicon oxide film are removed after forming a selective oxide film on the surface of the silicon substrate using the silicon nitride film as an oxidation mask.

FIG. 4 is a plan view of a DRAM memory cell showing a process of a conventional method of manufacturing a semiconductor memory device, in which a substrate contact window is formed in a silicon oxide film as an interlayer insulating film by etching using a photoresist as a mask. It shows.

FIG. 5 is a left view and a right view of FIG.
FIG. 4A is a sectional view in the order of the process in a portion Y-A ', wherein FIG. 4A is a diagram illustrating a selective oxide film formed on the surface of a silicon substrate, and a silicon oxide film as an interlayer insulating film deposited all over a memory cell and a word line. (B) shows a state in which a photoresist pattern having discrete window-shaped openings is formed on the silicon oxide film, and (C) shows a state in which the silicon oxide film is etched by using the photoresist as a mask. The state corresponding to the state of FIG. 4 in which the contact window is formed,
(D) shows a state in which the pattern of the storage electrode contacting each of the memory cells is formed using the substrate contact window.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate (semiconductor substrate) 2 selective oxide film 3 memory cell 4 word line 5 silicon nitride film (interlayer insulating film) 6 silicon oxide film (interlayer insulating film) 7 photoresist 8 opening 9 Substrate contact window 10 Storage electrode 11 Silicon oxide film 12 Silicon nitride film 13 Photoresist

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-51-35639 (JP, A) JP-A-2-2619 (JP, A) JP-A-3-257964 (JP, A) JP-A-4- 107965 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/28 H01L 21/3065 H01L 21/768 H01L 21/8242

Claims (4)

(57) [Claims] A plurality of memory cells and a selective oxide film for separating each of the plurality of memory cells from each other are formed on a surface of a semiconductor substrate, and an interlayer is formed so as to cover both the plurality of memory cells and the selective oxide film. Depositing an insulating film, forming a photoresist pattern on the interlayer insulating film having a groove-shaped opening that continuously connects regions where the substrate contact windows of the plurality of memory cells are to be formed, Forming a substrate contact window that reaches each of the plurality of memory cells by selectively removing the interlayer insulating film while leaving the selective oxide film by etching using a photoresist as a mask. . 2. The method according to claim 1, wherein the interlayer insulating film is a two-layered film having a silicon nitride film as a lower layer and a silicon oxide film as an upper layer, and the interlayer insulating film is etched by dry etching using gas plasma. 2. The method according to claim 1, wherein an end point of the dry etching is detected by detecting an emission spectrum of nitrogen from the film. 3. The method according to claim 2, wherein the thickness of the silicon nitride film as a lower layer of the interlayer insulating film is 20 nm or more. 4. The method according to claim 2, wherein the area of the opening of the photoresist is 20% or more of the entire area of the photoresist.