JP3096431B2 - コンピュータシステム、グラフィックスプロセッサ、インストラクションプリフェッチユニットおよびオペコードインストラクションをプリフェッチする方法 - Google Patents

コンピュータシステム、グラフィックスプロセッサ、インストラクションプリフェッチユニットおよびオペコードインストラクションをプリフェッチする方法

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Publication number
JP3096431B2
JP3096431B2 JP08340240A JP34024096A JP3096431B2 JP 3096431 B2 JP3096431 B2 JP 3096431B2 JP 08340240 A JP08340240 A JP 08340240A JP 34024096 A JP34024096 A JP 34024096A JP 3096431 B2 JP3096431 B2 JP 3096431B2
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Japan
Prior art keywords
instruction
instructions
opcode
graphics processor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP08340240A
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English (en)
Japanese (ja)
Other versions
JPH09251288A (ja
Inventor
ケイ． ラーソン マイケル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic Inc
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Publication of JPH09251288A publication Critical patent/JPH09251288A/ja
Application granted granted Critical
Publication of JP3096431B2 publication Critical patent/JP3096431B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP08340240A 1995-12-19 1996-12-19 コンピュータシステム、グラフィックスプロセッサ、インストラクションプリフェッチユニットおよびオペコードインストラクションをプリフェッチする方法 Expired - Lifetime JP3096431B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/574,835 1995-12-19
US08/574,835 US5917505A (en) 1995-12-19 1995-12-19 Method and apparatus for prefetching a next instruction using display list processing in a graphics processor

Publications (2)

Publication Number Publication Date
JPH09251288A JPH09251288A (ja) 1997-09-22
JP3096431B2 true JP3096431B2 (ja) 2000-10-10

Family

ID=24297851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP08340240A Expired - Lifetime JP3096431B2 (ja) 1995-12-19 1996-12-19 コンピュータシステム、グラフィックスプロセッサ、インストラクションプリフェッチユニットおよびオペコードインストラクションをプリフェッチする方法

Country Status (4)

Country Link
US (1) US5917505A (enExample)
EP (1) EP0780761B1 (enExample)
JP (1) JP3096431B2 (enExample)
TW (1) TW310410B (enExample)

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US6247088B1 (en) * 1998-05-08 2001-06-12 Lexmark International, Inc. Bridgeless embedded PCI computer system using syncronous dynamic ram architecture
US6323867B1 (en) * 1999-04-26 2001-11-27 Mediaq Inc. Parsing graphics data structure into command and data queues
US6598146B1 (en) 1999-06-15 2003-07-22 Koninklijke Philips Electronics N.V. Data-processing arrangement comprising a plurality of processing and memory circuits
US6515670B1 (en) * 1999-12-10 2003-02-04 Silicon Integrated Systems Corp. Graphics system and method for minimizing the idle time of a host processor in the graphics system
US6771269B1 (en) * 2001-01-12 2004-08-03 Ati International Srl Method and apparatus for improving processing throughput in a video graphics system
US6657632B2 (en) * 2001-01-24 2003-12-02 Hewlett-Packard Development Company, L.P. Unified memory distributed across multiple nodes in a computer graphics system
US6810483B2 (en) * 2001-01-25 2004-10-26 Synopsys, Inc. Synchronizing data and function opcodes between an application layer having a first clock speed and a circuit having a slower clock speed
US6952216B2 (en) * 2001-09-18 2005-10-04 Seiko Epson Corporation High performance graphics controller
US7629979B2 (en) * 2003-08-20 2009-12-08 Hewlett-Packard Development Company, L.P. System and method for communicating information from a single-threaded application over multiple I/O busses
KR100460009B1 (ko) * 2004-06-23 2004-12-04 엔에이치엔(주) 이미지 리소스를 로딩하는 방법 및 이미지 리소스 로딩시스템
TWI236657B (en) * 2004-09-01 2005-07-21 Au Optronics Corp Timing controller with external interface and apparatuses based thereon
US7546483B1 (en) * 2005-10-18 2009-06-09 Nvidia Corporation Offloading RAID functions to a graphics coprocessor
JP5137866B2 (ja) * 2009-01-28 2013-02-06 三菱電機株式会社 設備操作表示装置
US8243313B2 (en) 2009-05-26 2012-08-14 Infoprint Solutions Company Llc Cache optimization mechanism
US10698859B2 (en) 2009-09-18 2020-06-30 The Board Of Regents Of The University Of Texas System Data multicasting with router replication and target instruction identification in a distributed multi-core processing architecture
US20120120050A1 (en) * 2010-11-12 2012-05-17 Nokia Corporation Dual-mode two-dimensional/three-dimensional display
JP2012233965A (ja) * 2011-04-28 2012-11-29 Mitsubishi Electric Corp 画像表示装置
KR101574406B1 (ko) * 2011-08-15 2015-12-03 미쓰비시덴키 가부시키가이샤 묘화 제어 장치
US20150378920A1 (en) * 2014-06-30 2015-12-31 John G. Gierach Graphics data pre-fetcher for last level caches
US10452399B2 (en) 2015-09-19 2019-10-22 Microsoft Technology Licensing, Llc Broadcast channel architectures for block-based processors
US10719321B2 (en) 2015-09-19 2020-07-21 Microsoft Technology Licensing, Llc Prefetching instruction blocks
US11016770B2 (en) 2015-09-19 2021-05-25 Microsoft Technology Licensing, Llc Distinct system registers for logical processors
US10180840B2 (en) 2015-09-19 2019-01-15 Microsoft Technology Licensing, Llc Dynamic generation of null instructions
US11126433B2 (en) 2015-09-19 2021-09-21 Microsoft Technology Licensing, Llc Block-based processor core composition register
US11977891B2 (en) 2015-09-19 2024-05-07 Microsoft Technology Licensing, Llc Implicit program order
US10768936B2 (en) 2015-09-19 2020-09-08 Microsoft Technology Licensing, Llc Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
US10198263B2 (en) 2015-09-19 2019-02-05 Microsoft Technology Licensing, Llc Write nullification
US10871967B2 (en) 2015-09-19 2020-12-22 Microsoft Technology Licensing, Llc Register read/write ordering
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings
US10678544B2 (en) 2015-09-19 2020-06-09 Microsoft Technology Licensing, Llc Initiating instruction block execution using a register access instruction
US10776115B2 (en) 2015-09-19 2020-09-15 Microsoft Technology Licensing, Llc Debug support for block-based processor

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JPS63226764A (ja) * 1987-03-17 1988-09-21 Fanuc Ltd 高速浮動小数点演算システム
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US5369744A (en) * 1989-10-16 1994-11-29 Hitachi, Ltd. Address-translatable graphic processor, data processor and drawing method with employment of the same
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US5528764A (en) * 1992-12-24 1996-06-18 Ncr Corporation Bus system with cache snooping signals having a turnaround time between agents driving the bus for keeping the bus from floating for an extended period
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Also Published As

Publication number Publication date
EP0780761A2 (en) 1997-06-25
EP0780761B1 (en) 2001-08-08
JPH09251288A (ja) 1997-09-22
EP0780761A3 (en) 1997-11-12
TW310410B (enExample) 1997-07-11
US5917505A (en) 1999-06-29

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