JP3075620B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a capacitor on a semiconductor substrate such as a DRAM memory cell.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional stack type (laminated type) DR.
A method for manufacturing an AM memory cell will be described. First, as shown in FIG. 2A, a thick field oxide film 2 is selectively formed on a surface portion of a silicon substrate 1 by a LOCOS method to perform element isolation. Next, a thin oxide film 3 serving as a gate insulating film is formed on the exposed surface of the substrate 1, and polysilicon for forming a gate electrode is formed on the entire surface. Then, after doping the polysilicon with phosphorus using POCl ₃ as a diffusion source to impart conductivity, the polysilicon is patterned by performing anisotropic etching with gate photolithography to form the gate electrode 4. At this time, the oxide film 3 is simultaneously formed on the gate electrode 4.
And the same pattern as above. Next, arsenic ⁽⁷⁵ As ⁺⁾ to form the source and drain 5 by implanting ions into the substrate 1 using the gate electrode 4 as a mask. Thus, the transfer gate transistor is completed.

[0003] Next, as shown in FIG.
A SiO ₂ film 6 is grown, and a contact hole 7 is formed in the SiO ₂ film 6 by photolithography and anisotropic etching. Thereafter, polysilicon for forming the storage electrode of the capacitor is formed on the entire surface including the contact hole 7 portion, the polysilicon is doped with phosphorus by using POCl ₃ as a diffusion source to have conductivity, and the polysilicon is further subjected to photolithography. The storage electrode 8 of the capacitor is formed by patterning by etching. Thereafter, a thin thermal oxide film 9 serving as a capacitor insulating film is formed on the surface of the storage electrode 8, and then polysilicon for forming a plate electrode of the capacitor is formed on the entire surface, and phosphorus is converted to polysilicon using POCl ₃ as a diffusion source. Doped to make it conductive. Thereafter, the polysilicon is patterned by photolithographic etching to form a plate electrode 10 of the capacitor.
Thus, the capacitor is completed.

Thereafter, as shown in FIG.
The PSG film 11 is grown, and a heat treatment at about 900 ° C. is performed to planarize the surface. Thereafter, a contact hole 12 is formed in the BPSG film 11 and the CVD SiO ₂ film 6 by photolithography and etching, and a bit line 13 is formed by patterning by sputtering of aluminum and photolithography.

[0005]

However, in the conventional manufacturing method as described above, if the storage electrode 8 of the capacitor is reduced due to high integration and a reduction in the size of the substrate, a sufficient capacitance cannot be obtained. A hold time defect occurs, which causes problems such as deterioration of device characteristics and reduction in yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a method of manufacturing a semiconductor device capable of obtaining a large surface area of a capacitor electrode even if the capacitor electrode is reduced, thereby obtaining a sufficient capacitor capacitance. With the goal.

[0007]

According to the present invention, a first film having large irregularities is formed, and a second film having small irregularities is further formed thereon. A lower electrode is formed.

[0008]

According to the above-mentioned forming method, the surface shape of the capacitor lower electrode has a shape in which small irregularities due to the second film ride on large irregularities due to the first film. The surface area of the lower electrode can be significantly increased by the above two types of unevenness. Therefore,
Thereafter, by forming a capacitor insulating film on the lower electrode and further forming an upper electrode to complete the capacitor, a sufficient capacitance of the capacitor can be obtained even if the area of the capacitor is reduced.

[0009]

An embodiment of the present invention will be described below with reference to FIG. In one embodiment, the present invention is applied to the formation of a capacitor of a DRAM memory cell. Of course, the present invention can be used for other capacitor formation.

In FIG. 1A, reference numeral 21 denotes a silicon substrate.
Is formed, and a transfer gate transistor is formed on the substrate 21. This transfer gate transistor is composed of a gate oxide film 23, a gate electrode 24, and a source / drain diffusion layer 25, and the detailed manufacturing method is the same as that of the related art. Thereafter, a CVD SiO ₂ film 26 is grown on the entire surface of the substrate 21 as an interlayer insulating film, and a contact hole 27 is formed in the film.

The subsequent steps are a capacitor forming step. First, as shown in FIG. 1A, a silicon film 28 having large irregularities is formed as a first film of a lower electrode on the entire surface of a substrate. The silicon film 28 has a temperature of 575, for example.
LP using SiH ₄ (silane) gas at ℃, pressure 0.2 Torr
It is formed by forming amorphous silicon to a thickness of 100 nm by a CVD (Low Pressure Chemical Vapor Deposition) method and subsequently performing annealing in a vacuum for 15 minutes. Under the conditions in this case, the unevenness is about 0.2 μm. Next, once the structure is taken out of the LPCVD furnace and the silicon film 28 is exposed to the atmosphere, a silicon film 29 having small irregularities is formed on the silicon film 28 as a second film of the lower electrode. The silicon film 29 is formed, for example, at a temperature of 570 ° C. and a pressure of 0.2
At rr, amorphous silicon is formed by LPCVD using SiH ₄ gas to a thickness of about 30 nm.
Formed by minute annealing. Under the conditions in this case, the unevenness is about 30 nm.

Then, after introducing impurities into the silicon films 29 and 28 to make them conductive, the silicon films 2
By patterning 9 and 28 as shown in FIG. 1B, a capacitor lower electrode 30 having a two-layer film structure is formed. The surface shape of the lower electrode 30 is
Small irregularities due to the silicon film 29 are superimposed on the large irregularities due to the above, and the surface area is increased by the two kinds of irregularities.

The method and conditions for forming the silicon films 28 and 29 are not limited to the above methods and conditions, but may be other methods and conditions. However, the silicon film 28 having large unevenness is formed with an unevenness of 0.05 μm to 0.2 μm. If the unevenness is larger than this, the entire surface becomes flat and the effect of increasing the surface area is reduced. If the unevenness is smaller than this, the concave portion is filled with the subsequently formed silicon film 29 having small unevenness, and the effect of increasing the surface area is reduced. . The silicon film 29 having small irregularities is
It is formed with irregularities of 0.01 μm to 0.05 μm. If the unevenness is larger than this, the concave portion of the silicon film 28 having the large unevenness in the lower layer is filled, and if the unevenness is smaller than this, the effect of increasing the surface area is reduced. In the above manufacturing method, after the silicon film 28 is formed, the silicon film 28 is once taken out of the LPCVD furnace and exposed to the atmosphere. This is because a natural oxide film is formed on the surface of the silicon film 28 so that the silicon film 28 When growing the silicon film 29, the crystal growth of the underlying silicon film 28 is discontinuous and a new growth nucleus can be formed. As a result, the silicon film 29 having small irregularities which is not affected by the underlying silicon film 28 is formed. Although it is possible, a natural oxide film may be formed by flowing oxygen in the same LPCVD furnace instead of exposing to the atmosphere. The natural oxide film is destroyed by ion implantation for introducing impurities into the silicon films 29 and 28 or by a subsequent heat treatment, so that the conductivity of the lower electrode 30 is not adversely affected.

After the lower electrode 30 is formed as described above, a thin thermal oxide film 31 is formed as a capacitor insulating film on the surface of the lower electrode 30 as shown in FIG. The electrode 32 is formed of polysilicon to complete the capacitor. Further, an intermediate insulating film 33 is formed entirely, a contact hole 34 is opened, and a bit line 35 is formed to complete a DRAM memory cell.

[0015]

As described above in detail, according to the present invention, the second film having the small unevenness is formed on the first film having the large unevenness, and the small unevenness is placed on the large unevenness. Since the lower electrode of the capacitor is formed in the shape of the surface, even if the plane area of the capacitor is reduced, the surface area of the lower electrode can be increased and a sufficient capacitance of the capacitor can be obtained. Therefore, for example, a hold time defect does not occur in the DRAM memory cell, and the device characteristics and the yield can be improved.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing one embodiment of the present invention.

FIG. 2 is a process sectional view showing a method for manufacturing a conventional stacked DRAM memory cell.

[Explanation of symbols]

 28 silicon film 29 silicon film 30 lower electrode

Continuation of the front page (56) References JP-A-5-13677 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27 / 04

Claims (3)

(57) [Claims] A step of forming a first silicon film having irregularities on a substrate, a step of forming an oxide film on a surface of the first silicon film, and a step of forming an oxide film on a surface of the oxide film. A method for manufacturing a semiconductor device, comprising: a step of forming a second silicon film having irregularities smaller than the irregularities of a first silicon film; and a step of destroying the oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein both the first silicon film and the second silicon film are formed by reacting SiH ₄ in a low-pressure CVD furnace. A method for manufacturing a semiconductor device, comprising: 3. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film is formed by exposing the substrate and the first silicon film to the atmosphere or by using SiH ₄ and O ₂ in a low-pressure CVD furnace. A method for manufacturing a semiconductor device, characterized by being formed by reacting