JP3074683B2 - Binarization circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binarization circuit for binarizing an output signal from a solid-state imaging device such as a CCD image sensor to obtain image data.

[Prior art and its problems] Generally, image data optically read by a CCD image sensor is output at an electric signal level corresponding to the luminance of the subject. By binarizing the electric signal level, black and white image data can be obtained. This CCD
One way to binarize the output signal is to first
Only the high-frequency component is extracted by differentiating the output signal, and the differentiated output is compared with two levels _VH and _VL ,
The time from the point when the voltage exceeds _VH to the point when the voltage becomes lower than _VL is
(High) level signal, and conversely, an L (low) level signal from the point when the voltage _falls below _VL to the point when it exceeds _VH
Value is achieved. In this case, a black-and-white image is created by setting the area where the Δ level signal is obtained as white and the area where the L level signal is obtained as black.

That is, in the above-described conventional binarization circuit, since the white data and the black data are binarized at a point where a change in contrast is large as a boundary, even if the luminance of the subject and its background is slightly different, the dark portion of the subject may be darkened. Exactly 2
It can be binarized, and even if the CCD output signal slightly changes due to the influence of noise, it can be binarized accurately without being affected by the noise.

However, when binarized image data is obtained by the above-described conventional binarizing circuit, minute binarization of the CCD output signal can be eliminated and a reliable binarization process not affected by noise can be performed, but fine image information may be lost. is there.

[Object of the Invention] The present invention has been made in view of the above problems,
It is an object of the present invention to provide a binarizing circuit that can obtain a CCD output signal in a fine information portion in a subject as fine image information without being affected by a minute change.

[Gist of the Invention] That is, a binarizing circuit according to the present invention comprises an input means for inputting an image signal, and a first differentiating means for differentiating the image signal obtained by the input means based on a first time constant τ1. A second differentiating means for differentiating the image signal obtained by the input means based on a second time constant τ2 (<τ1);
Binarizing means for obtaining binarized data of the image signal in accordance with each differential output from the first differentiating means and the second differentiating means. First, a small change is eliminated with a large differential time constant τ1. After capturing the contrast between the background portion and the subject portion of the subject, the binarization process is performed by capturing the minute change only in the subject portion with a smaller differential time constant τ2.

Further, as described in claim 2, the binarizing means includes a first binarizing means for binarizing a signal outputted from the first differentiating means, and a signal outputted from the second differentiating means. A second binarizing means for binarizing the output signal, and a logical sum of the respective binarized outputs of the first and second binarizing means as a binarized output. With this configuration, binarization processing can be performed with a simple configuration.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration. First, an electric signal corresponding to an optical image output from a CCD (solid-state imaging device) is:
It is input to the first differentiating circuit 11a and the second differentiating circuit 11b. The first and second differentiating circuits 11a and 11b convert electric signals output from the CCD into different time constants τ ₁ and τ, respectively.
₂ (τ ₁ > τ ₂ ), and the CCD differential output signal from the first differentiating circuit 11a is obtained by the comparator (12a1)
Terminal and the (+) terminal of the comparator 12a2, and the CCD differential output signal from the second differentiating circuit 11b is supplied to the comparator 12b1
And the (+) terminal of the comparator 12b2. Here, the binarized reference voltage V H1 is applied to the (+) terminal of the comparator 12a1, and the binarized reference voltage is applied to the (−) terminal of the comparator 12a2.
VL1 is supplied, the binary reference voltage VH2 is supplied to the (+) terminal of the comparator 12b1, and the binary reference voltage VL2 is supplied to the (-) terminal of the comparator 12b2. In this case, the binarized reference voltage
The voltage levels of V H1, V L1, V H2, and V L2 are set in the following relationship.

V H1> V H2>0> V L2> V L1 i.e., comparator 12a1,12a2 is the threshold level of a wide vertical width differential output signal of the constant tau ₁ time obtained from the first differential circuit 11a V H1V L1 The first holding circuit 13a is set when the first differential output level of the CCD exceeds the reference voltage V H1, and a binary image signal corresponding to a portion having a large contrast change is obtained. When the first differential output level falls below the reference voltage VL1, the first holding circuit 13
a is reset.

Further, the comparator 12b1,12b2 is made to correspond to the second binarizing the differential output signal of the constant tau ₂ in the threshold level V H2V L2 narrow vertical width when obtained from the differentiation circuit 11b relatively fine contrast change When the CCD second differential output level exceeds the reference voltage VH2, the second holding circuit 13b is set, and the CCD second differential output level falls below the reference voltage VL2. And the second holding circuit 13b
Is reset.

The output signals from the first holding circuit 13a and the second holding circuit 13b are output as binary image signals via OR gates OR, respectively.

In this case, the first holding circuit 13a is always in the set state in the white area of the white original, so that the first holding circuit 13a
Only in the black data region where is reset, a fine binary image signal corresponding to the set / reset operation of the second holding circuit 13b can be obtained.

FIG. 2 is a waveform diagram showing the operation of each section of the above-mentioned binarization circuit.

That is, when the CCD output signal is given, the CCD differential output differentiated by the large time constant τ ₁ in the first differentiating circuit 11a is compared with the reference voltages V H1 and V L1 in the comparators 12a1 and 12a2.
The value is binarized, and the binarized output is output from the first holding circuit 13a. Here, a white background image region bordering on a portion where the contrast change is large is obtained as a Δ level signal, and a black image region therein is obtained as an L level signal.

On the other hand, when the CCD output signal is given in parallel with the black and white binarization by the first differentiation process, the second differentiation circuit 11b
, The CCD differential output differentiated by the small time constant τ ₂ is binarized by the reference voltages V H2 and V L2 in the comparators 12b1 and 12b2, and the binarized output is output from the second holding circuit 13b. Here, a white background image region including a relatively small portion of contrast change is a Δ level signal, and a black image region is L level.
This is what was obtained with the level signal.

Then, a black-and-white binary signal obtained by the first differential processing,
The black-and-white binary signal obtained by the second differentiation processing is combined through an OR gate OR, and an image signal finely binarized only in the black image area can be obtained.

Therefore, according to the binarization circuit having the above configuration, a white-to-H level and black-to-L level binarized signal from which a minute signal change is eliminated in advance by the first differential processing, and a fine signal change by the second differential processing. Since a final binarized image signal is obtained by performing a logical sum synthesis with a black-and-white binarized signal including a black and white binarized signal, accurate image information can be read without losing a fine portion of black image information.

In the above-described embodiment, the case in which the subject image information on the white background is read as fine binary data is described. Only when the output levels of the circuits 13a and 13b are both high (white) levels,
What is necessary is just to obtain a (white) level binary output. That is, the first and second holding circuits in FIG.
The outputs of 13a and 13b may be combined through AND gate AND.

[Effects of the Invention] As described above, according to the present invention, an input unit for inputting an image signal, and the image signal obtained by the input unit is transmitted to the first unit.
A first differentiating means for differentiating based on the time constant τ1 of the first time, and a second time constant τ2 of the image signal obtained by the input means.
A second differentiating means for differentiating based on (<τ1), and a binarizing means for obtaining binary data of the image signal according to each differential output from the first differentiating means and the second differentiating means. First, a large differential time constant τ1 is used to capture the contrast between the background portion of the subject and the subject portion from which minute changes are eliminated, and then a small differential time constant τ2 is used to capture a small change in only the subject portion. Since the binarization process is performed, it is possible to provide a binarization circuit that can obtain fine image information without being affected by a slight change in a CCD output signal in a subject portion.

Further, as described in claim 2, the binarizing means includes a first binarizing means for binarizing a signal outputted from the first differentiating means, and a signal outputted from the second differentiating means. A second binarizing means for binarizing the output signal, and a logical sum of the respective binarized outputs of the first and second binarizing means as a binarized output. With this configuration, the binarization processing can be performed with a simple configuration, so that a binarization circuit that can perform binarization with a simple configuration can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a binarizing circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing operation waveforms of each section of the binarizing circuit. 11a... First differentiator circuit, 11b... Second differentiator circuit, 12a1, 12a
2, 12b1, 12b2 ... comparator, 13a ... first holding circuit, 13b ...
... Second holding circuit, OR ... OR gate.

Claims (2)

(57) [Claims] An input means for inputting an image signal, and an image signal obtained by the input means is converted into a first time constant τ
And a second time constant τ.
2 (<τ1), and a binarizing unit that obtains binarized data of the image signal according to each differential output from the first and second differentiating units. A binarization circuit, comprising: A second binarizing means for binarizing the signal output from the first differentiating means; and a binarizing means for converting the signal output from the second differentiating means into two. A second binarizing means for converting a value, and a means for outputting, as a binarized output, a logical sum of respective binarized outputs of the first and second binarizing means. 2. The binarization circuit according to claim 1, further comprising: