JP3070539B2 - External storage device, data processing device, and data processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an external storage device in which a storage area is divided into a plurality of blocks. The present invention also relates to a data processing device that stores data in an external storage device in which a storage area is divided into a plurality of blocks. The present invention also relates to a data processing method for storing data in an external storage device in which a storage area is divided into a plurality of blocks.

[0002]

2. Description of the Related Art As an external storage device used for a data processing device such as a personal computer or a digital still camera, there is an external storage device having a flash memory.

An external storage device provided with a flash memory divides a storage area into a plurality of blocks, and manages a data area in units of blocks. Here, each block is a unit of data erasure. That is, when erasing data, an initialization process is performed on the entire block including the data. Thereby, the data stored in the block is erased collectively.

In such an external storage device, when data is stored in blocks, unique logical addresses are set for those blocks. Each block is managed using this logical address.

[0005] Data stored in the external storage device is usually stored in the external storage device in file units. However, when one file covers a plurality of blocks, connection information of those blocks is required. Become. Therefore, when one file extends over a plurality of blocks, the logical address of the next block (hereinafter, referred to as a concatenated address) is stored in each of the blocks storing the file.

[0006]

Conventionally, in such an external storage device, processing for checking whether or not there is an error in a storage area, and processing for trying to repair the error when there is an error, have been proposed. It is executed every time the external storage device is started. In the following description, such processing is referred to as error detection and correction processing. Usually, such an error detection and correction process is a process that requires a relatively large load and takes a long time. Therefore, there has been a problem that the conventional external storage device cannot be started immediately due to the error detection and correction processing.

In an external storage device in which data area management is performed in block units, when data is newly written to a block or when data stored in a block is updated, the data is suddenly stored. When the power supply is cut off or the external storage device is forcibly removed from the data processing device, a state in which a plurality of blocks having the same logical address exist at the same time (hereinafter, referred to as a “block”).
This is called a logical address error. ) Or a state in which the block indicated by the link address does not exist (hereinafter, referred to as a link address error). Naturally, in such a state, the file is linked to an unexpected block, and the external storage device cannot be used normally.

However, the conventional external storage device does not have a function of detecting a logical address error or a linked address error and appropriately recovering the error. for that reason,
Conventionally, when the power supply was suddenly cut off or the external storage device was forcibly removed from the data processing device, the external storage device could not be used normally thereafter. .

The present invention has been proposed in view of the above-described conventional circumstances. Even if a logical address error or a concatenated address error occurs in an external storage device, the error can be detected and appropriately corrected. It is intended to be.

[0010]

An external storage device according to the present invention is an external storage device that is detachably connected to a data processing device and stores data from the data processing device.
It has a serial interface for exchanging serial data with the data processing device, and a non-volatile memory for storing data. Then, the nonvolatile memory is divided into a plurality of blocks that can be erased at once, and the blocks include:
A logical address and an identification number indicating the new or old of the data stored in the block are stored. If there are a plurality of blocks having the same logical address, based on the identification number,
It is determined whether the data stored in these blocks is new or old, the newer data is invalid, and the old data is valid.

[0011]

Further, the data processing device according to the present invention is divided into a serial interface for exchanging serial data, and a plurality of blocks which can be erased at once,
A data processing device to which an external storage device having a nonvolatile memory for storing data in a block is attached and detached. When storing data in the external storage device, a logical address and a logical address are stored in a block of the nonvolatile memory. Stores identification numbers indicating the old and new of the stored data, and when reading data from the external storage device, if there are multiple blocks with the same logical address, stores them in those blocks based on the identification numbers The old and new data is determined as invalid data, and the old data is determined as valid data.

[0013]

Further, according to the data processing method of the present invention, when storing data in an external storage device having a nonvolatile memory divided into a plurality of blocks that can be erased at once, a logical address is stored in a block of the nonvolatile memory. And an identification number indicating the old and new of the data stored in the block, and when reading data from the external storage device, when there are a plurality of blocks having the same logical address, based on the identification number, The old and new data stored in the block is determined, and the newer data is regarded as invalid data.
The older data is regarded as valid data.

[0015]

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[0017] 1. Overall Configuration of System FIG. 1 shows the overall configuration of an example of a system to which the present invention is applied. This system includes a data processing device 1 serving as a host-side system, and a memory card 2 serving as an external storage device connected to the data processing device 1 via a serial interface.

[0018]

The data processing device 1 includes an arithmetic processing device (CP
U) 3, an internal memory 4, an auxiliary storage device 5, and a serial interface circuit 6, which are interconnected by a bus 7. This data processing device 1
For example, the CPU 3 reads a program stored in the auxiliary storage device 5 and executes the program by using the internal memory 4 as a work area.
At this time, data is exchanged with the memory card 2 via the serial interface circuit 6 as necessary.

The data processing device 1 used in the system to which the present invention is applied is not particularly limited as long as it can exchange data with an external storage device. Is applicable to various data processing devices such as a personal computer, a digital still camera, and a digital video camera.

The data processing device 1 and the memory card 2
They are connected by a serial interface. Specifically, at least three data lines SCLK and Sta
te, DIO. That is, the data processing device 1 and the memory card 2 are connected to at least the first data line SCLK for transmitting a clock signal during data transmission.
And a second data line State for transmitting a status signal required for data transmission, and a third data line DIO for serially transmitting data to be written to the memory card 2 or data to be read from the memory card 2, Through these, data is exchanged between the data processing device 1 and the memory card 2.

Data exchange between the data processing device 1 and the memory card 2 is usually performed in units of a file composed of a header and actual data. In the header of the file, for example, information for accessing the file, information required by a program executed by the data processing device 1, and the like are stored.

[0023] 2. 2. Configuration of Memory Card As shown in FIG. 2, the memory card 2 includes a controller 11 composed of a so-called control IC and a flash memory 12 managed by the controller 11.

The controller 11 has a serial / parallel / parallel / serial interface sequencer 13 (hereinafter referred to as an S / P & P / S interface) for performing serial / parallel conversion, parallel / serial conversion, and the like.
Called sequencer 13. ) And the flash memory 12
And a page buffer 15 for temporarily storing data exchanged between the S / P & P / S interface sequencer 13 and the flash memory interface sequencer 14. An error correction circuit 16 for performing error correction processing, a command generator 17 for generating a control command for controlling access to the flash memory 12, etc., and version information and various attribute information of the memory card 2 are stored. A configuration ROM 18 and an oscillator 19 for supplying a clock signal necessary for the operation of each circuit.

The S / P & P / S interface sequencer 13 includes at least the three data lines SC described above.
Data processing device 1 via LK, State, DIO
, And exchanges data with the data processing device 1 via these data lines SCLK, State, and DIO. That is, the S / P & P / S interface sequencer 13 converts the parallel data sent from the page buffer 15 into serial data, and
To the serial interface circuit 6. Also,
S / P & P / S interface sequencer 13
Converts the serial data sent from the serial interface circuit 6 of the data processing device 1 into parallel data and sends it to the page buffer 15.

This S / P & P / S interface
Transmission of serial data between the sequencer 13 and the data processing device 1 is performed by the third data line DIO while synchronizing with the clock signal sent from the data processing device 1 by the first data line SCLK. Will be At this time, the data type of the serial data exchanged by the third data line DIO is determined by the status signal transmitted by the second data line State. Here, the types of serial data include, for example, data to be written to the flash memory 12, data read from the flash memory 12, control data for controlling the operation of the memory card 2, and the like. Note that the status signal is also used to indicate the state of the memory card 2. The state of the memory card 2 indicated by the status signal includes, for example, a state in which the memory card 2 is not accepting data input from the data processing device 1 during some processing, or a state in which the processing on the memory card 2 is completed. Waiting for data input from the data processing apparatus 1.

If the data sent from the data processing device 1 is control data for controlling the operation of the memory card 2, the S / P & P / S interface sequencer 13 transmits the control data The command is sent to the command generator 17.

The command generator 17 is based on control data sent from the data processing device 1 via the S / P & P / S interface sequencer 13.
A control command for controlling access to the flash memory 12 is generated.
Send it to the interface sequencer 14. The flash memory interface sequencer 14 writes data to the flash memory 12 and reads data from the flash memory 12 based on the control command, as described later.

An erroneous erasure prevention switch 20 is connected to the command generator 17. When the erroneous erasure prevention switch 20 is turned on, control data instructing to erase data written in the flash memory 12 is transmitted to the data processing device 1.
Command generator 17
Does not generate a control command for erasing data written in the flash memory 12. In other words, this memory card 2 is
It is possible to switch between a state in which data stored in the flash memory 12 cannot be erased and a state in which data stored in the flash memory 12 can be erased.

The page buffer 15 disposed between the S / P & P / S interface sequencer 13 and the flash memory interface sequencer 14
This is a so-called buffer memory, which temporarily stores data exchanged between the S / P & P / S interface sequencer 13 and the flash memory interface sequencer 14.

That is, data sent from the S / P & P / S interface sequencer 13 to the flash memory interface sequencer 14 first
The data is sent from the S / P & P / S interface sequencer 13 to the page buffer 15 and is temporarily stored by the page buffer 15. At this time, the data stored in the page buffer 15 is transferred to the error correction circuit 16.
To add an error correction code. The data with the error correction code is sent from the page buffer 15 to the flash memory interface sequencer 14 for each predetermined page unit (for example, one page = 512 bytes).

Alternatively, data sent from the flash memory interface sequencer 14 to the S / P & P / S interface sequencer 13 is first sent from the flash memory interface sequencer 14 to the page buffer 15, and the page buffer 15 temporarily stored. At this time, the data stored in the page buffer 15 is transferred to the error correction circuit 16.
Performs an error correction process. The data subjected to the error correction processing is sent from the page buffer 15 to the S / P & P / S interface sequencer 13 for each predetermined page unit.

The flash memory interface sequencer 14 writes data to the flash memory 12 and reads data from the flash memory 12 based on a control command from the command generator 17. That is, the flash memory interface sequencer 14 reads data from the flash memory 12 based on a control command from the command generator 17, and transfers the data to the S / P & P / S via the page buffer 15 as described above.・ Send to the interface sequencer 13. Or,
Flash memory interface sequencer 14
Transmits the data from the S / P & P / S interface sequencer 13 based on the control command from the command generator 17 to the page buffer 1 as described above.
5 and the data is stored in the flash memory 1
Write to 2.

The configuration ROM 18 stores version information and various attribute information of the memory card 2. The information stored in the configuration ROM 18 is read and used by the command generator 17 via the S / P & P / S interface sequencer 13 as needed. That is, the command generator 17 reads information stored in the configuration ROM 18 as necessary, and performs various settings relating to the memory card 2 based on the information.

The data to be written to the flash memory 12 is sent to the memory card 2 as serial data from the data processor 1 via the three data lines SCLK, State, and DIO described above. First, S / P & P / S interface
The sequencer 13 converts the serial data into parallel data, and converts the parallel data into a page buffer 15.
Send to The page buffer 15 is S / P & P / S.
The data sent from the interface sequencer 13 is temporarily stored. At this time, page buffer 1
The data stored in 5 is subjected to an error correction code by an error correction circuit 16. Then, the data with the error correction code is sent to the flash memory interface sequencer 14 for each predetermined page unit. Then, the flash memory interface sequencer 14 writes the data sent from the page buffer 15 to the flash memory 12 based on a control command from the command generator 17.
By the above processing, the data sent from the data processing device 1 is written to the flash memory 12.

When reading data from the memory card 2 as described above, first, the command generator 17
, Data is read from the flash memory 12 by the flash memory interface sequencer 14. Then, the flash memory interface sequencer 14 sends the data read from the flash memory 12 to the page buffer 15. The page buffer 15 temporarily stores data sent from the flash memory interface sequencer 14. At this time, the data stored in the page buffer 15 is subjected to error correction processing by the error correction circuit 16. The data subjected to the error correction processing is sent to the S / P & P / S interface sequencer 13 for each predetermined page unit. Then, the S / P & P / S interface sequencer 13 converts the data sent from the page buffer 15 into serial data, and then converts the data through the three data lines SCLK, State, and DIO described above. It is sent to the processing device 1. By the above processing, the data read from the flash memory 12 is
The data is sent to the data processing device 1.

When data is written or read, not only is data exchanged with the flash memory 12 and data read from the flash memory 12 performed, but also control data for controlling the exchange is performed. Is sent from the data processing device 1 to the S / P & P / S interface sequencer 13 of the memory card 2. This control data is sent from the S / P & P / S interface sequencer 13 to the command generator 17. And the command generator 17
Is the S / P & P / S interface sequencer 1
3 to generate a control command for controlling access to the flash memory 12. Then, the control command is sent to the flash memory interface sequencer 14, and the flash memory interface sequencer 14 accesses the flash memory 12 based on the control command to perform data writing and data reading. .

The memory card 2 includes not only the above-mentioned three data lines SCLK, State, and DIO, but also includes a wiring for supplying a voltage and a wiring for a reserve which is not normally used. Is also good. For example, FIG.
In FIG. 3 described later, the three data lines SC described above are used.
In addition to LK, State, and DIO, the memory card 2 is provided with four power supply wirings VSS1, VSS2, VCC, and INT and three reserve wirings RSV1, RSV2, and RSV3.

[0039] 3. Appearance of the memory card Next, a specific profile of the memory card 2 as described above will be described with reference to FIG.

The memory card 2 is a thin card-shaped case 21 made of synthetic resin or the like and having a rectangular planar shape.
The controller 11 and the flash memory 12
Etc. are built-in. And this memory card 2
The memory card 2 is used by being mounted on the data processing apparatus 1 having a mounting mechanism for mounting the memory card 2.

At the front end of the case 21 of the memory card 2, there is formed a notch 22 which is cut obliquely.
Zero concave portions 23 are formed. When the memory card 2 is mounted on the mounting device of the data processing device 1, the data processing device 1
The external connection terminals connected to the connection terminals are arranged. That is, this memory card 2 has ten terminals 24a, 24b, 24c,
24d, 24e, 24f, 24g, 24h, 24i, 2
4j. The breakdown of these external connection terminals is
Three data line terminals 24b, 24d, 24h, four power supply terminals 24a, 24f, 24i, 24j, and 3
These are the reserve terminals 24c, 24e and 24g of the book.

An erroneous erasure prevention member 25 is attached to the upper surface of the case 21 of the memory card 2.
The erroneous erasure prevention member 25 is engaged with the erroneous erasure prevention switch 20 housed inside the case 21, and by sliding the erroneous erasure prevention member 25, the on / off of the erroneous erasure prevention switch 20 is performed. Can be switched.

The memory card 2 has a case 20 for preventing the memory card 2 from dropping out of the data processing device 1 when the memory card 2 is mounted on the mounting device of the data processing device 1.
An arc-shaped first lock notch 26 is formed on one of the side surfaces of the case 20, and a rectangular second lock notch 27 is formed on the other side of the case 20. When the memory card 2 is mounted on the mounting device of the data processing device 1, the locking notches 26 and 27 are engaged with the mounting device of the data processing device 1 so that the memory card 2 does not fall off. Is done.

The memory card 2 shown in FIG. 3 is merely an example of an external storage device to which the present invention is applied. That is, the present invention is applicable to any external storage device without depending on the external shape of the external storage device.

[0045] 4. Next, the structure of the storage area of the flash memory 12 mounted on the memory card 2 as described above will be described.

The storage area of the flash memory 12 is
As shown in FIG. 4A, the data is divided into a plurality of blocks which are data erasing units. Note that these blocks include a boot block in which boot data, which is data read first by the data processing device 1 when the memory card 2 is started, is stored, and a data block in which arbitrary data is written. is there. Each block has a unique physical address. These blocks are the unit of data erasure,
It is also the minimum unit for file management. That is, a file is stored in one or more blocks, and one block cannot be used in a plurality of files.

Each block is "1" or "0".
, And in the initial state, all bits are set to “1”, and a change in bit units can be made only from “1” to “0”. I have. That is, when writing data consisting of “1” and “0”, the corresponding bit is held as it is for “1”, and the corresponding bit is changed from “1” to “0” for “0”.

When data once written is erased, initialization processing is performed collectively for each block, and all bits of the block are set to "1". As a result, the data written in the block is collectively erased, and the block becomes ready for data writing again.

In order to change from "0" to "1", it is necessary to perform initialization processing collectively for each block and set all bits of the block to "1". "
Can be changed from “0” to “0” without performing the initialization process collectively in block units. In the following description, changing from "1" to "0" without performing the initialization process collectively for each block is referred to as overwriting.

It is to be noted that the present invention is not limited to a flash memory in which each bit can take only two states as described above (a so-called binary flash memory).
The present invention is also applicable to a flash memory that can take one or more states (a so-called multi-level flash memory).

As shown in FIG. 4B, each block of the flash memory 12 is composed of a plurality of pages serving as a unit for writing and reading data. That is, when writing data to the flash memory 12, as described above, the page buffer 1
5 is written to the flash memory 12 by the flash memory interface sequencer 14 in page units. When data is read from the flash memory 12, the data is read for each page by the flash memory interface sequencer 14 and sent to the page buffer 15.

Each page has a data area and a redundant area. The data area is an area where arbitrary data is written. The redundant area is an area in which information necessary for managing data written in the data area is stored.

Specifically, as shown in FIG. 4C, so-called distributed management information is stored in the redundant area of the first page of a block as information necessary for managing the block. In addition, the redundant area of each page after the second page of the block is also provided as spare distributed management information.
The same distributed management information stored in the redundant area of the first page is stored. However, in the redundant area of the last page, not so-called distributed management information, but so-called additional management information is stored as additional information that cannot be managed only by the distributed management information.

As described above, in the flash memory 12, the distribution management information is stored in the redundant area in each block. The distribution management information is information for managing a block in which the distribution management information is stored. From the distributed management information, for example, information as to whether or not the block is the first block of the file, or information indicating the connection of the blocks when the file is composed of a plurality of blocks is obtained. be able to. The distribution management information will be described later in detail.

The memory card 2 collects distributed management information of each block to create so-called collective management information as information for managing the entire flash memory, and flashes the collective management information as a file. It is stored in the memory 12.

Then, usually, according to the set management information,
Get the information needed to access each block. That is, the data processing device 1 and the memory card 2
When exchanging data with the data processing device 1
Reads the group management information from the memory card 2, creates a management table in the internal memory 4, and accesses the memory card 2 based on the management table. This allows
It is not necessary to access the distributed management information stored in each block every time data is accessed, so that higher-speed data access is possible.

[0057] 5. Distributed management information will now be described in detail distributed management information.

The distribution management information is information for managing a block in which the distribution management information is stored, and is written in a 16-byte redundant area. Specifically, FIG.
, A 1-byte enable / disable flag, a 1-byte block flag, a 4-bit final flag, a 4-bit reference flag, a 1-byte management flag, a 2-byte logical address, It consists of a byte concatenated address, a 3-byte reserved area, a 2-byte error management code for distributed management information, and a 3-byte data error correction code.

The enable / disable flag is a flag indicating whether the block is in a usable state or an unusable state, and specifically indicates two states of "usable" and "unusable".
"Available" indicates that the block is usable,
"Unusable" indicates that the block is unusable. For example, when an unrecoverable error occurs in a block, the enable / disable flag is set to “unavailable”, and the block is disabled.

The block flag is a flag indicating the state of the block, and specifically, “unused”, “head used”
The four states of “used” and “not erased” are shown. "unused"
Indicates that the block is unused or has been erased, is in an initial state (a state in which all bits are “1”), and in which data can be written immediately. “Top use” indicates a state in which the block is used at the beginning of the file. In the boot block in which the boot data is stored, the block flag is set to “used at the beginning”. “Use” indicates a state in which the block is used at a position other than the beginning of the file. When the block flag is "use",
This block is connected from another block. “Unerased” indicates a state in which data written in the block has become invalid. For example, when erasing data, first set the block flag to "not erased".
When there is enough processing time, a block whose block flag is set to “unerased” is erased. Thus, the erasing process can be performed more efficiently.

The last flag is a flag indicating whether or not the file has ended, and specifically indicates two states of “block continuation” and “block end”. “Block continuation” indicates that there is a connection to the next block. That is, "block continuation" indicates that the file stored in the block still continues, and the file continues in another block. "Block end"
Indicates the last block. That is, “block end” indicates that the file stored in the block ends with this block.

The reference flag is a flag for designating the reference of the additional management information, and specifically shows two states of “without reference information” and “with reference information”. "No reference information" indicates that there is no valid additional management information in the redundant area of the last page of the block. “With reference information” indicates that valid additional management information exists in the redundant area on the last page of the block.

The management flag is a flag indicating a block attribute or the like. For example, the management flag indicates whether the block is a read-only block or a writable block. Further, for example, the management flag indicates whether the block is a boot block or a data block.

The logical address literally indicates the logical address of the block. The value of the logical address is updated as necessary, for example, when rewriting data.
The value of the logical address is set so that a plurality of blocks do not have the same logical address value at the same time as long as the processing is performed normally.

Incidentally, in the case of a flash memory, as described above, it is necessary to first erase a block in order to rewrite data in the same block. However, the guaranteed number of erasable operations has an upper limit, and it is required that the number of block erase operations be as small as possible. Therefore, when updating data in a block, new data is written in another block instead of using the same block to rewrite new data. At this time, the block flag of the block in which the data is stored first is set to “not erased” so as to indicate that the data stored in the block has become invalid. In the memory card 2, even if the data is updated in this manner, the physical address set in advance for each block is such that the address indicating the block in which the data is stored is the same. Separately, a dynamically changeable logical address is assigned to each block so that the logical address represents a block in which data is stored.

The link address indicates a logical address of a block linked to the block. In other words, if the file stored in the block has a continuation, and the file continues to another block, the link address indicates
The value of the logical address of the next block in which the continuation of the file is stored is set.

The error correction code for distributed management information is an error correction code for data written in the management flag, the logical address, the link address, and the reserved area in the distributed management information. The enable / disable flag, block flag, last flag, and reference flag are not subject to error correction by the error management code for distributed management information. Therefore, the enable / disable flag, block flag, last flag, and reference flag can be rewritten without updating the error correction code for distributed management information.

The data error correction code is an error correction code for data written in the data area of the page in which the data error correction code is stored.

The error correction code for distributed management information and the error correction code for data are used by the error correction circuit 16 arranged inside the memory card 2. Therefore, error correction using these error correction codes is
Without depending on the data processing device 1, the memory card 2
Can be used.

[0070] 6. Additional management information will be described in detail for additional management information.

The additional management information is information stored in the 16-byte redundant area of the last page of the block, and includes additional information that cannot be managed only by the distributed management information.

Specifically, as shown in FIG. 6, the additional management information includes a 1-byte enable / disable flag, a 1-byte block flag, a 4-bit final flag, a 4-bit reference flag, It consists of a 1-byte identification number, a 2-byte effective data size, a 5-byte reserved area, a 2-byte error correction code for additional management information, and a 3-byte data error correction code.

Here, the enable / disable flag, block flag, last flag, reference flag, reserved area, and data error correction code are the same as in the case of the distribution management information. Further, the error correction code for additional management information is equivalent to the error correction code for distributed management information in the distributed management information. Among the additional management information, the identification number, the effective data size, and the data written in the reserved area are targeted. This is the error correction code.

The identification number and the effective data size are included in the additional management information as additional information that cannot be managed only by the distributed management information.

The identification number is information for error processing.
Each time the data of the block is rewritten, the value of this identification number is incremented. This identification number is used to identify the old and new of the data written in those blocks when some error occurs and a plurality of blocks having the same logical address exist. A 1-byte area is used for the identification number, and its value ranges from "0" to "255".
Its initial value is "0". Note that the identification number is "25
When it exceeds "5", it is returned to "0". When there are a plurality of data blocks having the same logical address, the data block having the smaller value of the identification number is valid. However, if there are spare boot blocks, the identification numbers of the boot blocks have the same value in a normal state. In the case where the identification numbers of the boot blocks are different due to some abnormality, the boot block with the larger value of the identification number is validated.

The valid data size indicates the size of valid data in the block. That is, when there is a free space in the data area of the block, a value indicating the size of the data written in the data area is set in the effective data size. At this time, the reference flag of the distributed management information is set to “with reference information”. If there is no free space in the data area of the block, “0xffff” is set in the effective data size as a value indicating that there is no free space in the data area.

The above-described distributed management information and additional management information are updated so that they are always the latest information every time data in a block is updated.

[0078] 7. Set management information Next, set management information will be described in detail.

As described above, the collective management information is information created by collecting distributed management information of each block, and is stored in the flash memory 12 as a file. That is, as shown in FIG. 7, a file of set management information, which is information for managing all blocks collectively, is created from the distributed management information of each block, and this set management information is stored in the data area of a predetermined block. Is stored.
The set management information may be stored in one block or may be stored over a plurality of blocks. Then, the data processing device 1 normally obtains information necessary for accessing each block by using the set management information.

That is, when the effective collective management information is stored as a file in the memory card 2, the data processing device 1 reads out the collective control information file and develops it on the internal memory 4 to manage the memory card 2. Create a management table for Note that the physical address of the block in which the head of the file of the set management information is stored is included in the boot data, and the data processing device 1
Accesses the set management information file based on the physical address.

As shown in FIG. 8, this set management information
A header of the set management information, a bitmap table indicating the state of each block, a conversion table for performing conversion from a specified logical address to a physical address when accessing the block, And a connection table indicating blocks.

The bitmap table stores information such as a valid / invalid flag, a block flag, a final flag, a reference flag, and a management flag extracted from the distribution management information of each block.

As shown in FIG. 9, the conversion table is a table in which physical addresses corresponding to logical addresses are described. The area where the physical address is stored is 2 bytes per entry. When the conversion table is created from the distribution management information, the logical address written in the distribution management information of the target block is checked, and the physical address of the block is registered at a corresponding position in the table. If a logical address is not used, “0xffff” is set to the corresponding physical address.

As shown in FIG. 10, the concatenation table is a table in which a concatenation address corresponding to a logical address is described. The area where the concatenation address is stored is 2 bytes per entry. When creating this connection table from the distribution management information, the connection address written in the distribution management information of the target block is checked, and the connection address of the block is registered at a corresponding position in the table.

[0085] 8. Procedure when the memory card starts Next, a procedure of startup of the memory card 2, FIG. 1
This will be described with reference to the flowchart of FIG.

When starting up the memory card 2, FIG.
As shown in FIG. 1, first, in step S1, the data processing device 1 reads boot data from a boot block of the memory card 2. Next, the process proceeds to step S2.

In step S2, the data processing device 1
Confirms whether the reading of the boot data from the boot block has been performed normally. If it is read normally, the process proceeds to step S3. If it is not read correctly, the process proceeds to step S8.

In step 3, the data processing device 1
Determines whether the memory card 2 is compatible with the data processing device 1 based on the read boot data. If the memory card is compatible, step S
The process proceeds to step S4, and if the memory card is not supported, the process proceeds to step S8.

In step S4, the data processing device 1
Reads the collective management information from the memory card 2. Note that the physical address of the block in which the set management information is stored is specified in the boot data. Next, the process proceeds to step S5.

In step S5, the data processing device 1
Confirms whether the valid set management information has been read normally. If it can be read normally, the process proceeds to step S6. If it cannot be read normally, the process proceeds to step S7.

In step S6, the data processing device 1
Expands the read set management information into the internal memory 4,
A management table for managing the memory card 2 is created. With the above processing, the initial processing at the time of starting the memory card 2 is completed, and the memory card 2 can be used.

If it is determined in step S5 that valid set management information cannot be read normally, the process proceeds to step S7 as described above. In step S7,
The data processing device 1 reads out the distribution management information of each block and reconstructs the set management information. Then, the group management information is expanded in the internal memory 4 and a management table for managing the memory card 2 is created. With the above processing,
The initial processing at the time of starting the memory card 2 is completed, and the memory card 2 can be used.

On the other hand, if it is determined in step S2 that an error has occurred during the reading of boot data, and if it is determined in step S3 that the memory card 2 does not correspond to the data processing device 1, as described above. Step S
Proceed to 8.

The process proceeds to step S8 for the memory card 2
It is when you can not use. Therefore, in step S8, the data processing device 1 performs a predetermined error process such as displaying a message indicating that the memory card 2 cannot be used, and terminates the startup process of the memory card 2.

9. Acquisition of set management information during data update processing
Each time the handling data processing device 1 performs a process of writing data to the memory card 2 or a process of erasing data from the memory card 2 (hereinafter, these processes are collectively referred to as “data update process”). The management table held in the internal memory 4 is updated as needed so as to match the actual state of the memory card 2 (that is, to match the contents of the distributed management information). On the other hand, the collective management information stored as a file in the memory card 2 is not updated every time the data is updated, but the changed content is updated collectively at an appropriate timing.

Generally, there is an upper limit to the number of times that the flash memory 12 can be rewritten. Therefore, the life of the memory card 2 can be extended.

However, when performing the data updating process, the file of the collective management information stored in the memory card 2 is invalidated. This is because the consistency between the distributed management information and the collective management information is not lost. During the data update processing, the distributed management information of the block to be processed is updated at the same time, but the contents of the collective management information are not updated at the same time, so that the distributed management information and the collective management information do not match. So, in such a state,
The set management information file stored in the memory card 2 is invalidated.

Specifically, at the time of the data update processing, FIG.
As shown in FIG. 2, first, in step S11, the data processing device 1 determines whether the set management information stored in the memory card 2 is valid or invalid. If the set management information has already been invalidated, the process directly proceeds to the data update process. On the other hand, if the set management information is valid, the process proceeds to step S12.

In step S12, the data processing device 1 invalidates the set management information. Specifically, the block flag of the block in which the file of the set management information is stored is set to “not erased”, or the block is erased to erase the data. Then, after the set management information is invalidated as described above, the process proceeds to the data update process.

The set management information file stored in the memory card 2 is invalidated during the data update process in order to maintain the consistency between the distributed management information and the set management information. The content of the management table held in the internal memory 4 is constantly updated so as to be the latest state. Then, the data processing device 1
Usually, each block is managed based on this management table.

The collective management information invalidated during the data update processing is newly written to the memory card 2 at an appropriate timing, and becomes valid again. Here, the appropriate timing is, for example, when the power of the memory card 2 is turned off after the use of the memory card 2 is completed, when the access to the memory card 2 is not performed for a predetermined time or more, or when the data is This is the case when the above is performed.

Specifically, for example, before the use of the memory card 2 is terminated and the power is turned off, a termination process as shown in FIG. 13 is performed to make the group management information valid.

In this end processing, first, in step S21
In, the data processing device 1 determines whether the set management information stored in the memory card 2 is valid or invalid. Then, if the set management information is valid, the process ends. On the other hand, if the set management information is invalid, the process proceeds to step S22.

In step S22, the data processing device 1 determines whether or not an erasing process has been performed on the block storing the file of the set management information. If the erasing process has not been performed, the process proceeds to step S23. If the erasing process has been performed, the process proceeds to step S24.

In step S23, the data processing device 1 performs an erasing process on the block storing the file of the set management information. Thereafter, the process proceeds to step S24.

In step S24, the data processing device 1 writes the collective management information in the memory card 2. At this time, the data processing device 1 creates a new file of collective management information based on the contents of the management table held in the internal memory 4 and writes the new collective management information file to the memory card 2. As a result, the effective collective management information indicating the latest state of the memory card 2 is stored in the memory card 2.

With the above, the end processing is completed, and the memory card 2
Is stored.

[0108] 10. Writing a new file The following describes a procedure for writing a new file in the memory card 2. The processing procedure for writing a file to the memory card 2 differs depending on whether the file size is known in advance or not.

10-1 Know the File Size in Advance
If the size of the file is known in advance, each time data of the file is written to a new block, it is determined whether the data fits in the block. And
If the data does not fit in the block, the logical address of the next succeeding block is secured, the data is written in the data area, and the distribution management information is written using the logical address of the next succeeding block as a concatenated address. At this time, the final flag is set to “block continuation”. On the other hand, if the data fits in a block,
The fractional part of the data, that is, the free area of the data area is set to “0xffff”. At this time, the last flag is set to “block last”, and the effective data size is written in the additional management information.

Next, a procedure for writing a file whose size is known in advance as described above to the memory card 2 will be described in detail with reference to the flowchart shown in FIG. In the flowchart shown in FIG. 14 and the flowcharts shown in FIGS. 15 and 17 described later, the check of the erroneous erasure prevention switch 20 of the memory card 2 and the processing when any error occurs are omitted. .

When writing a file of which size is known in advance to the memory card 2, first, in step S31, the data processing apparatus 1 prepares actual data to be written to the memory card 2 and a header of the actual data. In other words, in step S31, the data processing device 1
Prepares a file to be written to the data area of the memory card 2. The file header contains information on the size of the file. Next, step S32
Proceed to.

In step S32, the data processing device 1 sets the block flag of the block in which the file is stored first to “use at the beginning” and secures a free logical address. Next, the process proceeds to step S33.

At step S33, the data processing device 1 searches for a free physical address. Next, the process proceeds to step S34.

In step S34, the data processing device 1 determines whether or not the file fits in the block to be processed. If the file does not fit in the block and there is a continuation of the file, the process proceeds to step 35, while if the file fits in the block and there is no continuation of the file, the process proceeds to step 36.

In step S35, the data processing device 1 secures a logical address of the next succeeding block and sets this logical address as a concatenated address. next,
Proceed to step S37.

On the other hand, in step S36, the data processing device 1 sets the last flag to “block end” and sets the connection address to “0xffff”. Next, the process proceeds to step S37.

In step S37, the data processing device 1 creates distribution management information for the block to be processed based on the information set in the previous steps. Next, the process proceeds to step S38.

In step S38, the data processing device 1 sequentially writes data in block units to be processed in page units. If the file does not fit in the block to be processed, 1
Block data is written in page units. If the file can be accommodated in the block to be processed, data is written in the required page units in page units. Note that what is written in the block in step S38 is the data of the file to be newly written and the distribution management information created in step S37. Next, the process proceeds to step S39.

In step S39, the data processing device 1 determines whether or not writing to the memory card 2 has been completed for all data in the file. If writing has not been completed and data still remains, step S
Returning to step 33, the process is repeated. On the other hand, if the writing has been completed, the process proceeds to step S40.

In step S40, the data processing device 1 determines whether the written data ends in the middle of the block. If the data ends in the middle of the block, the process proceeds to step S41. On the other hand, if the data has been stored up to the end of the block, the process is terminated.

In step S41, the data processing device 1 writes the effective data size in the additional management information stored in the redundant area of the last page. That is, the data processing device 1 writes the value indicating the size of the data written in the data area of the block in which the last part of the file is stored as the effective data size in the additional management information of the block.

Thus, the process of writing the file whose size is known in advance to the memory card 2 is completed.

10-2 File size is not known
If the file size is not known in advance, the logical address of the next block is always secured, and when the data ends, the final flag of the final block is set by overwriting. The other distributed management information and additional management information are set in the same manner as when the file size is known in advance.

A procedure for writing a file whose size is not known in advance to the memory card 2 will be described in detail with reference to the flowchart shown in FIG.

When writing a file whose size is not known in advance to the memory card 2, first, in step S 51, the data processing device 1 creates a temporary header of the file to be written to the memory card 2. At this stage,
Because the file size is unknown, this temporary header contains
Does not include file size information. Next, the process proceeds to step S52.

In step S52, the data processing device 1 sets the block flag of the block in which the file is stored first to “use at the beginning” and secures a free logical address. Next, the process proceeds to step S53.

In step S53, the data processing device 1 prepares data to be written to the memory card 2. Next, the process proceeds to step S54.

In step S54, the data processing device 1 determines whether or not data to be written to the memory card 2 remains. If the data has not been completed and the data still remains, the process proceeds to step S55. On the other hand, if the data has been completed and no data remains, the process proceeds to step S61.

In step S55, the data processing device 1 searches for a free physical address. Next, the process proceeds to step S56.

In step S56, the data processing device 1 secures the logical address of the next succeeding block and sets this logical address as a concatenated address. next,
Proceed to step S57.

In step S57, the data processing device 1 creates distribution management information for the block to be processed based on the information set in the previous steps. Next, the process proceeds to step S58.

In step S58, the data processing device 1 sequentially writes data in block units to be processed in page units. If the file does not fit in the block to be processed, 1
Block data is written in page units. If the file can be accommodated in the block to be processed, data is written in the required page units in page units. What is written to the block in step S58 is the data of the file to be newly written and the distribution management information created in step S57. Next, the process proceeds to step S59.

In step S59, the data processing device 1 determines whether the written data ends in the middle of the data area of the block. If the data has been stored up to the end of the data area, the process returns to step S53 to repeat the processing. On the other hand, if the data ends in the middle of the data area, step S60
Proceed to.

In step S60, the data processing device 1 writes the effective data size in the additional management information stored in the redundant area of the last page of the block to be processed. That is, the data processing device 1 writes the value indicating the size of the data written in the data area of the block in which the last part of the file is stored as the effective data size in the additional management information of the block.
Next, the process proceeds to step S61.

In step S61, the data processing device 1 sets the last flag of the block to be processed to "block last" by overwriting. Next, the process proceeds to step S62.

At step S62, the data processing device 1 updates the header of the file. In other words, at this stage, the file size is clear,
A new header including the file size information is newly created, and the temporary header described above is rewritten to a new header including the file size information.

Thus, the process of writing the file whose size is not known in advance into the memory card 2 is completed.

[0138] 11. Update of File Next, a processing procedure when updating a file stored in the memory card 2 will be described.

When updating a file, the same logical address as that of the block whose data is to be rewritten is assigned to another block, and new data is written to the block. At this time, the block in which the old data is written is held without being released until the file update is completed. As a result, even if a failure occurs during the file update, it is possible to restore the state before the file update.

A specific example of such a file update procedure will be described with reference to FIG.

As shown in FIG. 16A, the head of the file is stored in the block of the logical address “1”, the next part of the file is stored in the block of the logical address “2”, and the next of the file is stored. Is stored in the block of the logical address “3”. It is also assumed that the identification number of the block having the logical address “1” is “6”, the identification number of the block having the logical address “2” is “4”, and the identification number of the block having the logical address “3” is “1”. .

Then, in such a state, it is assumed that the data of the block of the logical address "2" is rewritten.
In this case, first, as shown in FIG. 16B, a logical address "2" is assigned to a free block, and new data is written to this block. Here, as the identification number of the block in which new data is written, a value obtained by incrementing the identification number of the block in which old data is written by 1, that is, “5” is set.

At this stage, there are two blocks having the same logical address. Then, of these two blocks, the data stored in the block with the larger identification number is the newer data,
The data stored in the block with the smaller identification number is the older data.

Then, when the writing of the new data is completed normally, next, as shown in FIG. 16C, the block in which the old data has been written is erased. At this time, instead of performing the erasing process on the block in which the old data has been written, only the block flag of the corresponding block is set to “not erased”, and at an appropriate timing later, An erasing process may be performed on this block.

The above processing procedure is described in FIG.
This will be described in detail with reference to the flowchart shown in FIG.

When updating a file, first, in step S71, the data processing device 1 selects a block to be updated. Next, the process proceeds to step S72.

In step S72, the data processing device 1 reads the identification number of the block to be updated, and sets the value obtained by incrementing the value by 1 as the identification number of the block in which new data is to be written. Also,
The same value as the logical address of the block to be updated is set as the logical address of the block in which new data is to be written. Next, the process proceeds to step S73.

In step S73, the data processing device 1 prepares new data to be written to the block. Next, the process proceeds to step S74.

In step S74, the data processing device 1 searches for a free physical address. Next, the process proceeds to step S75.

In step S75, the data processing device 1 determines whether or not all data changes have been completed. If not completed, the process proceeds to step S76, and if completed, the process proceeds to step S79.

In step S76, the data processing device 1 secures a logical address of the next block, and sets this logical address as a link address. next,
Proceed to step S77.

In step S77, the data processing device 1 creates distribution management information for a block in which new data is to be written, based on the information and the like set in the previous steps. Next, the process proceeds to step S78.

In step S78, the data processing device 1 sequentially writes new data in page units in the block of the physical address searched in step S74. If the file does not fit in the block to be processed, data for one block is written in page units. If the file can be accommodated in the block to be processed, data is written in the required page units in page units. Note that what is written to the block in this step S78 is the data of the new file and the distribution management information created in step S77. After step S78, the process returns to step S73 to repeat the processing.

On the other hand, in step S79, the data processing device 1 determines whether or not a link address has been set to the block which was the last to be updated.
If the link address has not been set, step S80
The process proceeds to step S81 if the link address has been set.

In step S80, the data processing device 1 sets the last flag of the last block in which new data has been written to "block last". Next, the process proceeds to step S82.

On the other hand, in step S81, the data processing device 1 sets the value of the link address set in the block to be updated last in the link address of the block in which the new data was written last. . Next, the process proceeds to step S82.

In step S82, the data processing device 1 updates the header of the file. That is, since there is a possibility that the file size has been changed due to the update of the file, a header including information on the new file size is newly created and the header of the file is updated. Next, the process proceeds to step S83.

In step S83, the data processing device 1 erases the block in which the old data has been written. At this time, instead of performing the erasing process on the block in which the old data has been written, only the block flag of the corresponding block is set to “not erased”, and at an appropriate timing later, An erasing process may be performed on these blocks.

Thus, the file update processing is completed.

[0160] 12. Error Detection and Correction Processing In such a system as described above, when a new file is written to the memory card 2 or when a file stored in the memory card 2 is being updated, the power is suddenly shut off or the memory is turned off. When the card 2 is forcibly removed from the data processing device 1, a state where a plurality of blocks having the same logical address exist simultaneously (that is, a logical address error) occurs,
Alternatively, there is a possibility that a state in which the block indicated by the link address does not exist (that is, a link address error) may occur.

Therefore, in a system to which the present invention is applied,
When constructing the set management information, an error detection and correction process for detecting and correcting a logical address error or a link address error is performed. Hereinafter, the error detection and correction processing will be described in detail.

12-1 Error Detection Table In the system to which the present invention is applied, a logical address error or a linked address error is detected when constructing the set management information. Then, an error detection table is used as a table used for detecting a link address error. The error detection table is a table used only for detecting a link address error, and is temporarily secured in the internal memory 4 of the data processing device 1 when performing error detection and correction processing. The area reserved for the error detection table is released after the error detection and correction processing ends.

As shown in FIG. 18, this error detection table is a table provided with a 1-bit area indicating the connection state of each block for one logical address. In other words, the error detection table has one bit per entry, and each entry indicates the connection state of the logical address by “0” or “1”. When there are N blocks to be processed, the area occupied by the error detection table is N / 8 bytes.

In the error detection table, the meaning of the value indicating the connection state of each block differs between when the set management information is constructed and when the construction of the set management information is completed.

When the value indicating the connection state is “0” during the construction of the set management information, the entry indicates that the entry is in a normal state, or the logic corresponding to the entry is This indicates that the address is not specified by a concatenated address of another block before the current block to be processed. In this state, the value may become "1" as the processing proceeds, and it is uncertain whether it is a linked address error.

When the value indicating the connection state is "1" during construction of the set management information, the logical address corresponding to the entry is currently processed. This indicates a state in which a link address of another block is specified before the block, but does not correspond to a physical address. In this state, the value may become “0” as the processing proceeds in the future, and it is uncertain whether or not there is a connection address error.

On the other hand, when the value indicating the connection state is “1” at the stage when the construction of the set management information has been completed, the entry indicates that the logical address corresponding to the entry is specified as the connection address. This indicates that the corresponding physical address does not exist. Therefore, in this state, a link address error occurs.

When the value indicating the connection state is "0" at the stage when the construction of the set management information has been completed, the entry is in a state where the connection related to the logical address corresponding to the entry is normal. Is shown.

12-2 Detection of Linked Address Error Next, detection of a linked address error performed using the above-described error detection table will be described with a specific example.

For example, as shown in FIG. 19, for a block having a physical address "10", its logical address is "1", its concatenated address is "3", and for a block having a physical address "17", It is assumed that the logical address is “3” and the link address is “2”. It is also assumed that there is no block whose logical address is “2”.

At this time, if the process of reconstructing the collective management information is performed, a connection address error is detected as shown in FIG. 20 along with the restructuring of the collective management information.

First, in the initial state, as shown in FIG. 20A, the values of the error detection table are all set to the initial value "0" for each of the logical addresses "1", "2" and "3". In addition, the conversion table of the set management information is also
All are set to the initial value "0xffff". At this time, the consolidation table of the set management information is in a state where no value is entered.

Next, information on the block having the logical address "1" is read. Thus, as shown in FIG. 20B, the value of the conversion table corresponding to the logical address “1” is the value of the physical address of the block having the logical address “1”, that is, “10”. The value of the link table corresponding to the logical address “1” is the value of the link address of the block having the logical address “1”, that is, “3”.
It is said.

Next, the entry of the logical address “3” indicated by the value of the concatenation table corresponding to the logical address “1” is confirmed. At this time, since the physical block is not allocated to the entry of the logical address “3”, FIG.
As shown in 0 (c), the value of the error detection table corresponding to the logical address “3” is “1”. The value of the conversion table corresponding to the logical address “3” is the value of the logical address of the connection source, that is, “1”.

Next, the information of the block of the logical address “3” whose value of the error detection table is “1” is read. At this time, the block with the logical address “3” exists, and the information of the block can be read normally. Therefore, as shown in FIG. 20D, the value of the error detection table corresponding to the logical address “3” is set to “0”. At this time, the value of the conversion table corresponding to the logical address “3” is the value of the physical address of the block of the logical address “3”, that is, “1”.
7 ". The value of the link table corresponding to the logical address “3” is the value of the link address of the block having the logical address “3”, that is, “2”.

Next, the entry of the logical address “2” indicated by the value of the concatenation table corresponding to the logical address “3” is confirmed. At this time, since the physical block is not allocated to the entry of the logical address “2”, FIG.
As shown in 0 (e), the value of the error detection table corresponding to the logical address “2” is set to “1”. The value of the conversion table corresponding to the logical address “2” is the value of the logical address of the connection source, that is, “3”.

Next, an attempt is made to read the information of the block of the logical address "2" in which the value of the error detection table is "1". However, since the block having the logical address “2” does not exist, it is determined at this stage that a link address error has occurred.

12-3 Error Correction Processing In a system to which the present invention is applied, error correction processing for a logical address error is performed as follows.

When a logical address error has occurred, each block having the same logical address is examined. If there is only one complete block, the complete block is used and the remaining blocks are invalidated.

When there are a plurality of complete blocks (excluding the boot block) having the same logical address,
The identification number is compared, and the block having the smaller value is used.
The identification number of one block is “255”,
If the identification number of the other block is "0", the block with the identification number of "255" is used.

Normally, even if there are a plurality of blocks having the same logical address, the difference between their identification numbers is 1. If this is not the case,
Instead of automatically performing error correction processing on the system side, a manual recovery mode is set.

In the system to which the present invention is applied, when a link address error occurs, an appropriate error correction process is performed according to application software that uses the memory card 2, data stored in the memory card 2, and the like. To do. Specifically, for example, the following error correction processing may be performed.

That is, for example, a new block is assigned as the block indicated by the last link address. Then, the data of the last block is read up to a page that can be read correctly, and the data up to that page is copied to a new block. At this time, the final flag of the new block is set to “block final”. Such error correction processing is particularly suitable when the target data is data that is significant even in the middle of data, such as music data.

Alternatively, for example, the entire file including the block in which the link address error has occurred is deleted. Such error correction processing is particularly suitable when the target data is data that does not make sense in the middle of data, such as a program or image data.

12-4 Construction of Set Management Information and Error Detection
Output Correction Process In a system to which the present invention is applied, a physical address error or a link address error occurs when some trouble occurs during the data update process. And in the system to which the present invention is applied, as described above,
Prior to the data update processing, the collective management information stored in the memory card 2 is invalidated. Therefore, when a physical address error or a link address error occurs, the set management information is invalid. When the collective management information is invalid, when the memory card 2 is started next, the process of re-examining the distributed management information of all the blocks and reconstructing the collective management information is always performed.

Therefore, in this system, when reconstructing the set management information, attention is paid to rechecking all blocks, and at this time, error detection and correction processing is performed simultaneously. In other words, when the set management information is valid, there is no possibility that a physical address error or a concatenated address error has occurred, and no error detection and correction processing is performed at this time. That is, in this method, the error detection and correction processing is performed only when the set management information is reconstructed. This allows the memory card 2 to perform error detection and correction processing.
There is no need for extra access to. As a result, for example, the memory card 2 can be quickly activated.

This error detection and correction processing is performed according to the following procedure.

(1) The conversion tables on the internal memory 4 of the data processing device 1 are all initialized to “0xffff”. Also,
The area of the error detection table is secured in the internal memory 4,
The error detection table is all initialized to “0”.

(2) Move to the beginning of the block.

(3) The distribution management information is read from the block, and a bitmap table is constructed using the distribution management information. At this time, if the enable / disable flag is “unusable” or the block flag is “unused” or “unerased”, the process moves to the next block after the bitmap table is created. And repeat the process.

(4) Check the logical address of the block (hereinafter, logical address A) and the concatenated address (hereinafter, logical address B).

(5) If the logical address A is "0xffff", the process moves to the next block, returns to (3), and repeats the process.

(6) Check the column of logical address A in the error detection table. Logical address A of error detection table
Is replaced with "0" and the physical address of the block of the logical address "A" is written in the column of the logical address A in the conversion table.
If the logical address A column of the error detection table is “0”, the logical address A column of the conversion table is checked. When the value of the logical address A in the conversion table is “0xffff”, the physical address of the block of the logical address A is written therein.

When a value other than “0xffff” is already entered as the value of the logical address A in the conversion table,
Since a logical address error has occurred, error correction processing for the logical address error is performed.

(7) The value of the logical address B is entered in the column of the logical address A in the connection table.

(8) Check whether the last flag is "block last". If it is "block end", the linked address is invalid, so the process moves to the next block, returns to (3), and repeats the process.

(9) Whether or not a physical address corresponds to the logical address B is confirmed by using a conversion table. When the value of the logical address B in the conversion table is other than “0xffff”, the physical address corresponds to the logical address B. On the other hand, if the value of the logical address B in the conversion table is “0x
In the case of “ffff”, the physical address does not correspond to the logical address B up to the current block. At this time, “1” is entered in the logical address B column of the error detection table.
Is written, and the value of the logical address A is written in the column of the logical address B in the conversion table. Thereafter, the process moves to the next block, returns to (3), and repeats the processing.

Even if the value of the logical address B in the conversion table is "0xffff", it is clear whether or not the physical address really corresponds to the logical address B at the stage where processing is performed only halfway through the block. is not. That is, there are two cases: a case where the physical address does not really correspond to the logical address B, and a case where the corresponding block appears as the processing proceeds in the future.

(10) After processing all blocks, the error detection table is referred to. A logical address whose value in the error detection table is “1” does not correspond to a physical address. That is, a link address error has occurred. In this case, since the logical address of the link source block is stored in the conversion table,
Using this, the original block is specified, and appropriate error correction processing is performed. After the error correction processing, the value of the error detection table is set to “0”, and the value of the corresponding conversion table is set to “0xffff”.

In the system to which the present invention is applied, as described above, the error detection and correction processing is performed when constructing the set management information. Hereinafter, a specific method of constructing the set management information and performing the error detection and correction processing will be described in more detail with reference to flowcharts illustrated in FIGS.

Here, the variables I, A, B,
Use C, D, T (I) and N as a constant.
The variable I is a variable to which a physical address is input, the variable A is a variable to which a logical address is input, and the variable B
Are variables to which a link address is input, and variables C and D
Is a variable to which the value of the identification number is input, and the variable T
(I) is a variable indicating the value of the error detection table corresponding to the logical address “I”. The constant N is a constant indicating the total number of blocks.

When constructing the group management information, in step S101 of FIG. 21, the data processing device 1 initializes the conversion table and sets all values to “0xffff”. Next, the process proceeds to step S102.

In step S102, the data processing device 1 initializes the error detection table and sets all values to "0". Next, the process proceeds to step S103.

In step S103, the data processing device 1 substitutes “0” for the variable I. Next, step S1
Go to 04.

In step S 104, the data processing device 1 reads the distribution management information of the block having the physical address “I” from the memory card 2. Next, step S105
Proceed to.

In step S105, the data processing device 1 refers to the permission / inhibition flag of the distribution management information read in step S104 to determine whether the block of the physical address “I” is usable. If available,
Proceed to step S106, and if unusable, proceed to step S129.

In step S106, the data processing device 1 refers to the block flag of the distribution management information read in step S104, and determines whether the block of the physical address “I” is in use. Specifically, it is determined whether or not the block flag is set to “head use” or “use”. If the block flag is “head use” or “use” and the block is in use, the process proceeds to step S107. If the block is not in use, the process proceeds to step S129.

In step S107, the data processing device 1 adds information on the block of the physical address “I” to the bitmap table. Next, step S1
Proceed to 08.

[0209] In step S108, the data processing device 1 substitutes the logical address of the block of the physical address "I" into the variable A based on the distribution management information read in step S104, and sets the logical address of the block of the physical address "I". The link address is assigned to the variable B. Next, step S10
Go to 9.

[0210] In step S109, the data processing device 1 determines whether or not the value of A is "0xffff".
If it is not “0xffff”, the process proceeds to step S110, and “0xffff”
If “ffff”, the process proceeds to step S120 in FIG.

In step S110, the data processing device 1 checks the value of the logical address “A” in the error detection table. Next, the process proceeds to step S111.

In step S111, the data processing device 1 determines whether the value of the logical address “A” in the error detection table is “1”. If “1”, the process proceeds to step S112, and if “1”, the process proceeds to step S130.
Proceed to.

In step S112, the data processing device 1 rewrites the value of the logical address “A” in the error detection table to “0”. Next, the process proceeds to step S113.

In step S113, the data processing device 1 writes the variable “I” (ie, the physical block “I”) in the column of the logical address “A” in the conversion table.
Next, the process proceeds to step S114.

In step S114, the data processing device 1 writes the variable “B” (ie, the connection address “B”) in the column of the logical address “A” in the connection table.
Next, the process proceeds to step S115.

[0216] In step S115, the data processing device 1 determines whether or not the last flag is "block last". If it has not reached the "block end", the process proceeds to step S116, and if it has reached the "block end", the process proceeds to step S120 in FIG.

At step S116, the data processing device 1 checks the value of the conversion table corresponding to the logical address "B". Next, the process proceeds to step S117.

In step S117, the data processing device 1 determines whether the value of the conversion table corresponding to the logical address “B” is “0xffff”. If “0xffff”, the process proceeds to step S118, and if not “0xffff”,
The process proceeds to step S120 in FIG.

In step S118, the data processing device 1 rewrites the column of the logical address “B” in the error detection table to “1”. Next, the process proceeds to step S119.

[0220] In step S119, the data processing device 1 writes the logical address "A" in the logical address "B" column of the error detection table. Next, the process proceeds to step S120 in FIG.

At step S120 in FIG. 22, the data processing device 1 compares the value of the variable I with the value of a constant N indicating the total number of blocks. If I <N, step S
The process proceeds to 121, and if I <N, the process proceeds to step S128.

In step S121, the data processing device 1 substitutes “0” for the variable I. Next, step S1
Proceed to 22.

In step S122, the data processing device 1 determines whether the variable T (I) indicating the value of the logical address “I” in the error detection table is “1”.
If it is not "1", the process proceeds to step S123, and if it is "1", the process proceeds to step S125.

In step S123, the data processing device 1 compares the value of the variable I with the value of a constant N indicating the total number of blocks. If I = N, the process ends here. If not I = N, the process proceeds to step S124.

[0225] In step S124, the data processing device 1 increments the value of the variable I by one. afterwards,
Returning to step S122, the process is repeated.

If the variable T (I) is "1" in step S122, as described above, the process proceeds to step S12.
Go to 5. The process proceeds to step S125 when a link address error has occurred. Therefore, in step S125, the data processing device 1 performs a predetermined error correction process for the link address error. Here, as described above, an appropriate error correction process is performed according to application software that uses the memory card 2, data stored in the memory card 2, and the like. Then, when the error correction processing is completed, step S
Go to 126.

In step S126, the data processing device 1 sets the value of the logical address “I” in the error detection table to “0”. Next, the process proceeds to step S127.

In step S127, the data processing device 1 sets the logical address “I” column of the conversion table to “0x”.
ffff ”. Thereafter, the process proceeds to step S123, and performs the above-described processing.

When I <N in step S120, the process proceeds to step S128 as described above. The process proceeds to step S128 when the reading of the distribution management information has not been completed for all blocks. Therefore, in step S128, the data processing device 1 increments the value of the variable I by one, and thereafter,
The process returns to Step S104 of Step 1 and is repeated.

When the block of the physical address "I" is unusable in step S105 of FIG. 21 and when the block of the physical address "I" is not in use in step S106, Step S1
Go to 29.

In step S129, the data processing device 1 adds information on the block having the physical address “I” to the bitmap table. Thereafter, the process proceeds to step S120 in FIG. 22, and the above-described processing is performed.

If the value of the logical address "A" in the error detection table is not "1" in step S111 of FIG. 21, the process proceeds to step S130 as described above.
In this step S130, the data processing device 1
The value of the logical address “A” in the conversion table is checked. Next, the process proceeds to step S131.

In step S131, the data processing device 1 sets the value of the logical address “A” in the conversion table to “0x
ffff ”. If “0xffff”, the process proceeds to step S113 to perform the above-described processing, and “0xffff”
If not, the process proceeds to step S132 in FIG.

The process proceeds to step S132 in FIG. 23 when a logical address error has occurred and there are two blocks having the logical address "A". Therefore, in step S132, the data processing device 1 reads the identification numbers of the two blocks having the logical address “A”. When the identification number of one block can be read, the value is substituted for the variable C. When the identification number of the other block can be read, the value is substituted for the variable D. Next, the process proceeds to step S133.

[0235] In step S133, the data processing device 1 determines whether the identification number has been read out normally in step S132. When only the identification number assigned to the variable C can be read, the process proceeds to step S134, otherwise, the process proceeds to step S137.

In step S134, the data processing device 1 sets the block flag of the block corresponding to the variable D to “not erased”. Next, the process proceeds to step S135.

[0237] In step S135, the data processing device 1 determines whether the process in step S134, that is, the process of setting the block flag of the block corresponding to the variable D to "unerased" was successful. If successful, Figure 21
Returning to step S113, the above-described processing is performed, and if not successful, the flow proceeds to step S136.

In step S136, the data processing device 1 sets the permission / inhibition flag of the block corresponding to the variable D to “unusable”. Thereafter, step S11 in FIG.
3 and the above-described processing is performed.

In step S137, the data processing device 1 determines whether the reading of the identification number in step S132 has been performed normally. If only the identification number assigned to the variable D can be read, the process proceeds to step S138; otherwise, the process proceeds to step S141.

In step S138, the data processing device 1 sets the block flag of the block corresponding to the variable C to “not erased”. Next, the process proceeds to step S139.

In step S139, the data processing device 1 determines whether or not the process in step S138, that is, the process of setting the block flag of the block corresponding to the variable C to “not erased” has succeeded. If successful, Figure 21
Returning to step S113, the above-described processing is performed, and if not successful, the flow proceeds to step S140.

In step S140, the data processing device 1 sets the permission / inhibition flag of the block corresponding to the variable C to “unusable”. Thereafter, step S11 in FIG.
3 and the above-described processing is performed.

In step S141, the data processing device 1 determines whether the reading of the identification number in step S132 has been performed normally. If both the identification number assigned to the variable C and the identification number assigned to the variable D can be read normally, the process proceeds to step S142. on the other hand,
If neither of them can be read, the mode is shifted to the manual recovery mode, and the appropriate processing required for error correction is manually performed.

In step S142, the data processing device 1 compares the value of the variable C with the value obtained by adding “1” to the value of the variable D. If these values are equal, step S1
The process proceeds to step S143, and if the values are not equal, the process proceeds to step S143.

In step S143, the data processing device 1 compares the value of the variable D with the value obtained by adding “1” to the value of the variable C. If these values are equal, step S1
The process proceeds to step S38, and the above-described processing is performed. On the other hand, when these values are not equal, the mode is shifted to the manual recovery mode, and appropriate processing necessary for error correction is manually performed.

With the above-described processing, the error detection and correction processing is performed at the same time when the set management information is reconstructed. Thus, as described above, it is not necessary to access the memory card 2 extra for the error detection and correction processing. That is, in the system to which the present invention is applied, the error detection and correction processing is not executed when the data writing has been completed normally and the valid collective management information has been written back to the memory card 2.

As described above, in the system to which the present invention is applied, since unnecessary error detection and correction processing is not performed, the efficiency of access to the memory card 2 can be improved.
In particular, the error detection and correction processing is performed simultaneously with the operation of constructing the centralized management information from the distributed management information, so that access to the memory card 2 is minimized.

In the system to which the present invention is applied, each block of the memory card 2 is assigned an identification number, and the identification number is used to deal with a logical address error. It can be carried out.
In other words, even if an error occurs during data update processing and there are multiple blocks having the same logical address, the data before the data update processing can be restored by using the identification number. Can be.
Further, in the system to which the present invention is applied, by using the error detection table, a link address error can be detected, and a block having no link destination can be detected.

[0249]

As described above in detail, according to the present invention, an identification number is stored in each block of an external storage device,
Since the logical address error is dealt with using the identification number, the data updating process can be performed safely. In other words, even if some error occurs during the data update process and there are a plurality of blocks having the same logical address, based on the identification number,
By discriminating whether the data stored in the block is new or old, setting the new data as invalid data and setting the old data as valid data, the data in the state before the data update process can be recovered. .

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a system to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a memory card to which the present invention is applied.

FIG. 3 is a perspective view showing the appearance of a memory card to which the present invention is applied.

FIG. 4 is a diagram showing a structure of a storage area of a memory card to which the present invention is applied.

FIG. 5 is a diagram illustrating a configuration of distributed management information.

FIG. 6 is a diagram showing a configuration of additional management information.

FIG. 7 is a diagram showing a state in which set management information is constructed from distributed management information of each block.

FIG. 8 is a diagram showing a configuration of collective management information.

FIG. 9 is a diagram showing a conversion table.

FIG. 10 is a diagram showing a connection table.

FIG. 11 is a flowchart showing a procedure when starting a memory card.

FIG. 12 is a flowchart illustrating a procedure during a data update process.

FIG. 13 is a flowchart illustrating a procedure of a termination process.

FIG. 14 is a flowchart showing a procedure for writing a file of a known size to a memory card.

FIG. 15 is a flowchart showing a procedure for writing a file whose size is not known to a memory card.

FIG. 16 is a conceptual diagram showing a specific example of a file update procedure.

FIG. 17 is a flowchart illustrating a file update procedure.

FIG. 18 is a diagram illustrating an error detection table.

FIG. 19 is a diagram illustrating a specific example of a connection state between blocks.

20 is a diagram showing a flow of processing when the connection state between blocks is the state shown in FIG. 19 as an example of detection of a connection address error;

FIG. 21 is a flowchart illustrating a procedure of construction of collective management information and error detection and correction processing.

FIG. 22 is a flowchart illustrating a procedure of construction of the set management information and error detection and correction processing.

FIG. 23 is a flowchart showing a procedure of construction of the set management information and error detection and correction processing.

[Explanation of symbols]

1 data processing device, 2 memory card, 3 arithmetic processing device, 4 internal memory, 5 auxiliary storage device,
6 serial interface circuit, 7 bus, 1
1 controller, 12 flash memory, 13
Serial / Parallel / Parallel / Serial Interface Sequencer, 14 Flash Memory Interface Sequencer, 15 Page Buffer, 16 Error Correction Circuit, 17 Command Generator, 18 Configuration ROM, 19
Oscillator, 20 Erroneous erase prevention switch

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI G06F 12/00 531 G06F 12/00 531Z 542 542J JP-A-246645 (JP, A) JP-A-7-248978 (JP, A) JP-A-4-3218 (JP, A) JP-A-63-75951 (JP, A) JP-A-8-221333 (JP, A) Special table Hei 9-506460 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/16 G06F 3/06-3/08 G06F 12/00

Claims (3)

(57) [Claims] 1. A data processing apparatus, comprising:
External storage device for storing data from the data processing device
In location was to exchange the data processing device and the serial data
And a non-volatile memory for storing the data, wherein the non- volatile memory includes a plurality of blocks that can be erased in a batch.
The above block is divided into a logical address and the above
Identification number indicating the old or new of the above data stored in the block
Is stored, and if there are a plurality of blocks having the same logical address, the old and new data stored in those blocks is determined based on the identification number, and the new data is regarded as invalid data. And the older data is regarded as valid data. 2. A system for exchanging serial data.
Real interface and multiple blocks that can be deleted all at once
Blocks that store data in the above blocks.
Data to be attached to and detached from an external storage device having a volatile memory
In the processing device, when storing data in the external storage device,
Logical addresses and the above blocks
Stores the identification number indicating the old or new of the above data stored in
And, when data is read from the external storage device, when a plurality of blocks having the same logical address exists, based on the identification number, to determine the old and new data stored in these blocks, A data processing device wherein the newer data is invalid data and the older data is valid data. 3. Data is stored in an external storage device having a nonvolatile memory divided into a plurality of blocks that can be collectively erased.
At the time of storage , the logical
Dress and the old and new data stored in the block
Storing an identification number indicating, when data is read out from the external storage device, when a plurality of blocks having the same logical address exists, the data based on the identification number, is stored in the blocks Of the old and new,
A data processing method, wherein new data is invalid data and old data is valid data.