JP3057707B2 - Method for manufacturing semiconductor memory cell - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for forming a memory cell of a dynamic RAM (DRAM).

[Conventional technology]

A method of forming a memory cell of this type of conventional integrated circuit device will be described below with reference to FIGS.

In FIG. 4, LOCO is applied to the surface of the semiconductor substrate 1 (P type).
After the field oxide film 15 is formed by the S method, ions are selectively implanted into the semiconductor substrate 1 to form an N-type impurity diffusion layer 2. Next, after forming the capacitance oxide film 3 and the capacitance nitride film 4, oxidation is performed to form an oxide film 6. Further, after the polysilicon film 8 is grown and phosphorus diffusion is performed to reduce the resistance, etching is selectively performed to obtain a cross section as shown in FIG.

Next, as shown in FIG. 5, after an interlayer isolation oxide film 16 was formed on the polysilicon film 8 by thermal oxidation, ion implantation for controlling a threshold voltage was performed in a region where the channel portion 11 of the transistor was formed. After that, the capacitance nitride film 4 and the capacitance oxide film 3 on the channel portion 11 are removed, and a gate oxide film 12 is formed. After a phosphorus-doped polysilicon film is formed thereon as the gate electrode 14, the polysilicon film is selectively etched. The channel length is determined at the time of this etching.

Further, after applying a photoresist in the state of FIG. 5,
As shown in FIG. 6, after selectively forming a drain diffusion layer 17 and growing an interlayer polysilicon film 18, an opening is formed above the drain diffusion layer 17, and an aluminum drain electrode 13 is sputtered and patterned. Then, a conventional memory cell is formed.

[Problems to be solved by the invention]

By the way, the area of the capacitance film of the above-mentioned semiconductor integrated circuit device becomes smaller as the degree of integration of the integrated circuit increases. For this reason, the capacitance has decreased, and the deterioration of the alpha ray soft error resistance has become a problem.

Although studies have been made to reduce the thickness of the capacitive composite film as much as possible and to form a groove type capacitive film, even if the conventional technology reduces the thickness of the capacitive composite film as much as possible, In technology, 40Å for capacitance oxide film,
The limit is to reduce the thickness of the capacitive nitride film to about 80Å. The oxide film on the capacitive nitride film cannot be made too thin to eliminate pinholes in the nitride film.

In addition, isolation between elements is performed by the LOCOS method. However, with the increase in integration, reduction of the element formation region due to BIRD'S BEAK also poses a problem. Since the capacitor portion and the transistor are on the same substrate surface, the channel length of the transistor is also narrowed, and this control becomes difficult.

The channel length of a transistor is determined by accurate etching of the photoresist and the polysilicon film, but with current technology, variations as small as 0.05 μm cannot be ignored, thus reducing the yield of the transistor, and thus the memory cell. In addition, since the channel doping must be performed before the gate size is determined, it is difficult to control the threshold voltage.

Furthermore, according to the conventional method, the drain electrode and the gate electrode are
It had to be formed in a separate step.

An object of the present invention is to provide a method of manufacturing a memory cell which eliminates the above-mentioned disadvantages and is particularly suitable for high integration.

[Means for solving the problem]

According to the method of manufacturing a semiconductor memory cell of the present invention, an impurity diffusion layer is selectively formed on a surface of a semiconductor substrate, a capacitance film is formed on the diffusion layer, and a capacitance film is formed on the diffusion layer. Forming an impurity-doped polysilicon film on the capacitance film to form a source region and a connection conductor of a MOS transistor described below; and crystallizing polysilicon on the polysilicon film. Forming a crystallized silicon film, forming a drain diffusion layer and a channel portion of a MOS transistor on the upper surface and side surfaces of the crystallized silicon film, and simultaneously forming a drain electrode and a gate electrode of the MOS transistor. And the step of performing

(Operation)

In the present invention, a capacitance film is formed on the entire surface of an element region separated by a field oxide film on the surface of a semiconductor substrate, and a conductor made of an impurity-doped polysilicon film is formed thereon. Next, polysilicon is deposited on the polysilicon film and then crystallized, thereby selectively forming a crystallized silicon film. Then, a MOS transistor (the source region is already formed of an impurity-doped polysilicon film) is formed on the side surface of the crystallized silicon film as a substrate of the transistor. At this time, the conductor made of the impurity-doped polysilicon film serves as a source and a wiring for the capacitor of the MOS transistor. Next, a gate electrode and a drain electrode are simultaneously formed to complete the process. As described above, in the present invention, the capacitor portion and the transistor of the memory cell are formed not on the same substrate surface but in a stack structure.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of one embodiment formed according to the present invention. The method of manufacturing the memory cell will be described step by step. According to the present invention, the capacitor portion of the memory cell is formed over the entire surface of the element region formed separately as shown in FIG. For this purpose, first, an N-type impurity diffusion layer 2 is selectively formed on a P-type semiconductor substrate 1 by ion implantation. Furthermore, on top of it, dry oxidation at 900 ° C, 40-70
After forming the capacitance oxide film 3 of {circle around (1)} and the capacitance nitride film 4 of 100 to 200 μm by the vapor phase growth method, the nitride film 4 is selectively etched with hot phosphoric acid using a photoresist as a mask. Then, oxidize for about 30 minutes by steam oxidation at 980 ℃,
An isolation film 5 of about 0.2 μm is formed on the silicon substrate 1, and an oxide film 6 is formed on the nitride film 4 by about 60 °. A polysilicon film 8 is grown on the capacitance composite film 7 (capacitance oxide film 3 + capacitance nitride film 4 + oxide film 6) and the separation film 5 thus formed. Etching gives the structure of FIG.

Next, as shown in FIG. 3, a polysilicon film is formed on the polysilicon film 8 and the separation film 5 and crystallized (crystallized silicon film 9).

After selectively forming the diffusion layer 10 on a part of the upper surface of the crystallized silicon film 9 obtained by the above method by ion implantation, the crystallized silicon film 9 and the thermal oxide film formed on the diffusion layer 10 are formed. Then, when a P-type impurity is ion-implanted into the side surface for controlling the threshold value, a channel portion 11 is formed. The polysilicon film 8 containing phosphorus and the crystallized silicon film 9
In between, an N-type diffusion layer is formed by an intermediate heat treatment step. After removing the thermal oxide film with hydrofluoric acid, a gate oxide film 12 is formed again by steam oxidation to obtain the structure shown in FIG.

Next, a part of the gate oxide film 12 on the diffusion layer 10 is opened,
After growing a polysilicon film as an electrode, phosphorus diffusion and patterning are performed to obtain a drain electrode 13 and a gate electrode.
14 are formed at the same time, and the desired memory cell shown in FIG. 1 is obtained.

A second embodiment in which memory cells having different transistor structures are formed according to the present invention will be described with reference to FIG. FIG. 7 is a longitudinal sectional view showing the gate electrode 14 shown in FIG.
A structure similar to that described above is formed at left and right symmetric positions. By using the gate electrode 14 'as a back gate electrode, the threshold can be freely controlled.

In both the first and second embodiments, the capacitance portion is configured as a parallel plate type. However, the capacitance portion can be formed in another type, for example, a groove type or a V type, and the cell area can be further reduced. It becomes possible.

〔The invention's effect〕

In the present invention, since the capacitor composite film is formed over the entire width of the element formation region on the substrate, and the transistor is not on a plane,
The element formation region can be reduced accordingly. The transistor is formed on the crystallized silicon film on the capacitor composite film, and its channel is on the side wall of the crystallized silicon film and is formed separately for each element. Can be made thinner than the conventional example, so that Bird's beak can be reduced. This is also advantageous for high integration.

Further, since the transistor is formed on the side surface with the thickness of the crystallized silicon film as the gate length, the transistor can be managed by controlling the thickness of the polysilicon film during vapor phase growth. The variation in film thickness at this time is more stable than that obtained by conventional photolithography. Since the channel portion is formed after the gate dimensions are determined, the characteristic value can be further controlled by the injection amount.

Finally, since the drain and gate electrodes can be formed simultaneously, the number of steps can be reduced.

[Brief description of the drawings]

1 to 3 are sectional views showing an embodiment of the present invention in the order of steps, FIGS. 4 to 6 are sectional views showing a conventional example, and FIG.
FIG. 6 is a cross-sectional view formed in another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Diffusion layer, 3 ... Capacitance oxide film, 4 ... Capacitance nitride film, 5 ... Separation film, 6 ... Oxide film, 7 ... Capacitance composite film, 8 ... Poly Silicon film 9 Crystallized silicon film 10 Diffusion layer 11 Channel part 12 Gate oxide film 13 Drain electrode 14 Gate electrode 15 Field oxide film 16 ... interlayer isolation oxide film, 17 ... drain diffusion layer, 18 ... interlayer polysilicon film.

Claims (1)

(57) [Claims] A step of selectively forming an impurity diffusion layer on a surface of a semiconductor substrate, forming a capacitance film on the diffusion layer, and forming a capacitance film on the diffusion layer; An impurity-doped polysilicon film is formed on the capacitor film, and
A step of forming a source region of a MOS transistor and a connection conductor part; a step of forming a crystallized silicon film obtained by crystallizing polysilicon on the polysilicon film; and a step of forming a MOS on the upper surface and side surfaces of the crystallized silicon film. Forming a drain diffusion layer and a channel portion of the transistor, respectively;
Forming a drain electrode and a gate electrode of the MOS transistor at the same time.