JP3048517B2 - Reticles for semiconductor device manufacturing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reticle used in a manufacturing process of a semiconductor device, and more particularly, to a reticle used in a first step of a photolithography process for forming an element on a semiconductor wafer, and an alignment error between the reticle. The present invention relates to a reticle for manufacturing a semiconductor device, on which an alignment mark is formed so that the inspection can be performed.

[0002]

2. Description of the Related Art In a semiconductor manufacturing process, a mask or a reticle is used as a pattern transfer mechanism. In general,
The mask is a pattern transfer mechanism that includes a pattern image that can be transferred onto the entire surface of the wafer or onto another mask in a single exposure, and the reticle is a pattern image that is step-and-repeat to expose the entire substrate. Can be said to be a pattern transfer mechanism including Such a reticle is used for printing an image of a pattern on a mask, and is used for transferring an image directly onto a wafer with a step-and-repeat aligner (stepper).

When a pattern image is directly transferred onto a semiconductor wafer using a reticle in a step-and-repeat manner as described above, in the first exposure step (hereinafter, referred to as a first step), a pattern serving as a reference for pattern alignment is used. Since they do not exist, the problem of pattern reduction and rotation arises.

FIG. 7 is a diagram showing a problem occurrence pattern in the first step.

FIG. 7A shows a case where an exposure pattern 1 actually exposed on a wafer shown by a solid line is reduced compared to a predetermined actual pattern 2 designed in advance by a broken line (−). reduction). FIG. 7B shows, on the contrary, a case where the exposure pattern 1 exposed on the wafer is enlarged from the actual pattern 2 (+ reduction). FIG. 7C shows a case where the exposure pattern 1 is rotated by a predetermined angle with respect to the actual pattern 2 with reference to the center of the reticle pattern. Although not shown, the pattern may be reduced and rotated at the same time.

In order to solve the problem occurring in the first step exposure process in the semiconductor manufacturing process, a reticle used in the first step is provided with an alignment mark (or key) serving as a reference for pattern alignment in a subsequent exposure process. Is formed on a scribe line around an element formation region where a semiconductor element is usually formed.

FIG. 8 is a schematic diagram showing a conventional first-step reticle having an alignment mark formed on a scribe line. An element forming region 12 serving as an effective chip pattern is formed at the center of the reticle 10, and a scribe line cut along a periphery of the element forming region 12 in a cutting step for forming a chip is formed. On the other hand, X1 and Y1 which are alignment marks formed on the scribe line in the Y direction in FIG.
Acts as a vernier, and X2 and Y2 formed on the scribe line in the X direction act as a vernier. That is, the reticle 10 for the first step
When a scribe line is overlapped and exposed on a wafer by a step-and-repeat method using X1, X1 and X2,
Y1 and Y2 overlap to form a pattern. The rotation of the reticle is confirmed by inspecting the pattern on which the main scale and the vernier scale pattern are superimposed with a microscope.

[0008]

However, according to the conventional reticle, it is possible to confirm only when the degree of rotation of the reticle is severe, and almost no reduction or enlargement of the pattern can be detected. On the other hand, as the degree of integration of a semiconductor element increases, even if a slight pattern error occurs due to miniaturization of design rules, the number of defective elements increases significantly.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to form an alignment mark so that a pattern error in the first step can be more accurately inspected. An object of the present invention is to provide a reticle for manufacturing a semiconductor device.

[0010]

According to the present invention, there is provided a reticle for manufacturing a semiconductor according to the present invention, wherein an alignment mark for detecting misalignment between reticles is formed in a scribe line. The main scale pattern and the vernier scale pattern are formed adjacent to each other in pairs, and the main scale pattern is formed separately along each side of the square plate pattern and the square plate pattern. It consists of a rod-shaped pattern,
When the vernier pattern overlaps with the main scale pattern, the vernier pattern is included in the square plate pattern of the main scale pattern, and is configured to be able to inspect a relative positional relationship with the main scale pattern.

At least two pairs of the alignment marks are formed in each scribe line in the X direction and the Y direction of the reticle, and are formed in the vicinity of each quadrangular vertex forming an element forming region in the reticle. Is desirable for accurate inspection of pattern errors.

[0012]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a diagram schematically illustrating a reticle 20 for a first step according to an embodiment of the present invention. The reticle 20 has a square element forming region 22 in which a pattern image of an effective chip portion is formed in the center thereof.
Are formed, and a scribe line 24 to be discarded in the cutting step is formed outside the element formation region 22. Within each scribe line 24 in the X direction (horizontal direction in the drawing) and the Y direction (vertical direction in the drawing) of the reticle 20, an alignment mark in which the main scale pattern 28 and the sub scale pattern 26 are paired is formed by the square Element forming region 22
In the vicinity of each vertex, a pair in the X direction and a pair in the Y direction are formed. That is, two pairs are formed in each scribe line in the X direction and the Y direction of the reticle.

FIG. 2 is an enlarged view of the portion "A" in FIG.

Referring to FIG. 2, the scribe line 24
The main scale pattern 28 formed therein has a quadrangular plate-shaped quadrangular pattern 30 formed therein, and first bar-shaped patterns 29 corresponding to the respective sides are formed around the quadrangular pattern 30.
In addition, the bar-shaped pattern 29 can also be formed integrally.

On the other hand, the sub-scale pattern 26 adjacent to and paired with the main scale pattern 28 is composed of a second bar pattern 27 having the same shape as the first bar pattern 29 of the main scale pattern 28,
However, only the size of the pattern is reduced. Second
When the bar-shaped pattern 27 is exposed so as to overlap with an adjacent reticle in the exposure process of the step-and-repeat method, the size is determined so as to be located within the square plate pattern 30 of the main scale pattern 28, and the vernier pattern 26 is square. It is desirable that the area is about 1/4 of the area of the plate pattern 30 for the accuracy of the pattern error.

As shown in FIG. 2, the main scale pattern 28 and the sub scale pattern 26 are formed of a photoresist layer, and the hatched portions in the drawing indicate the photoresist layer.
Further, the shape of the vernier scale pattern 26 does not necessarily have to be a bar shape, and may be any shape as long as it can show a relative positional relationship with the main scale pattern 28.

FIG. 3 is a view showing the arrangement of the alignment marks after the first step process is performed on the semiconductor wafer using the reticle of FIG. The main scale pattern 28 and the sub-scale pattern 26 of each reticle 20 are overlapped so that the main scale pattern 28 and the sub-scale pattern 26 of the adjacent reticle 20 cross each other.

FIG. 4 is a diagram showing a case where there are various pattern mistakes seen at the position "B" in FIG. The center point O (X, Y) of the reticle element formation region 22 located on the upper left side of FIG. 3 was set as a reference point (0, 0).

FIGS. 4 (a) and 4 (b) show that the vernier pattern is shifted upward or downward in the main scale pattern and rotated in opposite directions, and FIGS. 4 (c) and 4 (c). FIG.
(D) shows that the vernier pattern shifts to the left or right in the main scale pattern and is reduced in opposite directions.
FIG. 4E shows that reduction and rotation occur at the same time, and FIG. 4F shows a case where no pattern error occurs, in which the second bar-shaped pattern 27 of the sub-scale pattern is the main scale pattern. It is located in the middle of the first rod-shaped pattern 29.

FIGS. 5 and 6 show that the reduction and rotation are 5P, respectively.
5 shows an example in which a pattern error is inspected by an overlay device when PM is present. FIG. 5 shows a case in which inspection is performed using an X-direction alignment mark, and FIG. 6 shows a case in which inspection is performed using a Y-direction alignment mark.

In FIG. 5, the reduction in the X direction is 10 PPM, the reduction in the Y direction is 0 PPM, the rotation in the X direction is 0 PPM, and the rotation in the Y direction is 10 PPM. In FIG. 6, the reduction in the X direction is 0 PPM, The reduction is tested as 10 PPM, the rotation in the X direction as 10 PPM, and the rotation in the Y direction as 0 PPM.

From the monitored data, it can be seen that the value of reduction and rotation can be determined by checking either the X direction or the Y direction. On the other hand, the monitoring value becomes 10 PPM even though the reduction or rotation value is 5 PPM, because the pattern error between reticle shots in the first step process changes in both directions at the same time. The sum of the monitoring value in the X direction and the monitoring value in the Y direction is １ ／
It should be divided into The correction value is input to a stepper to reset a set value to minimize a pattern error.

[0024]

As described above in detail, according to the present invention, a pattern error can be accurately inspected by forming an alignment mark on a reticle used in the first step of the exposure step more accurately and rationally. Therefore, pattern errors of semiconductor devices are reduced, and the quality and yield of products are improved.

[Brief description of the drawings]

FIG. 1 is a view showing an arrangement of alignment marks of a reticle used in a first step for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is an enlarged view of a portion “A” in FIG. 1;

FIG. 3 is a diagram showing an alignment state of alignment marks when the reticle of FIG. 1 is exposed on a wafer.

FIG. 4 is a diagram schematically illustrating examples of various pattern mistakes seen in a “B” part of FIG. 3;

FIG. 5 is a diagram showing an example in which a specific pattern error is inspected with an alignment mark in the X direction.

FIG. 6 is a diagram showing an example in which a specific pattern error is inspected with an alignment mark in the Y direction.

FIG. 7 is a diagram illustrating problems that may occur during a first step of forming a pattern on a semiconductor wafer for the first time;

FIG. 8 is a view showing an arrangement of alignment marks of a reticle used in a first step process for manufacturing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Exposure pattern 2 Actual pattern 10, 20 Reticle 12, 22 Element formation area 24 Scribe line 26 Vernier pattern 27, 29 Bar-shaped pattern 28 Main scale pattern 30 Square plate pattern

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kim Jong-hee Apartment 201-1410, Dongshin-dong, Cheonan-gu, Suwon-si, Gyeonggi-do, Republic of Korea (56) References JP-A-4-61111 (JP, A) JP-A-60- 148117 (JP, A) JP-A-2-174110 (JP, A) JP-A-57-166034 (JP, A) JP-A-59-155734 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/027 G03F 9/00

Claims (4)

(57) [Claims] 1. A reticle for manufacturing a semiconductor device in which an alignment mark capable of inspecting a misalignment between reticles is formed in a scribe line, wherein the alignment marks are formed as a pair adjacent to each other and stepped. Sometimes consisting of a main scale pattern and a vernier pattern that are superimposed on each other, the main scale pattern is formed of a square plate-shaped square plate pattern and a bar-shaped pattern formed separately along each side of the square plate pattern, When the vernier pattern is overlapped with the main scale pattern, the vernier pattern is included in the square plate pattern of the main scale pattern and is configured to be able to inspect a relative positional relationship with the main scale pattern. A reticle for manufacturing a semiconductor device, comprising: 2. The reticle for manufacturing a semiconductor device according to claim 1, wherein at least two pairs of the alignment marks are formed in each scribe line in the X and Y directions of the reticle. 3. The reticle for manufacturing a semiconductor device according to claim 1, wherein the alignment mark is formed in the vicinity of each apex of a quadrangular shape forming an element forming region in the reticle. 4. The reticle for manufacturing a semiconductor device according to claim 1, wherein the vernier pattern has a reduced shape of a bar-shaped pattern of the main scale pattern.