JP3039502B2 - Superconducting high-frequency clock operation evaluation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a superconducting high-frequency clock operation evaluation circuit, and more particularly to a superconducting high-frequency clock operation evaluation circuit for evaluating the operation of a superconducting integrated circuit with a high-frequency clock of a GHz band or more.

[0002]

2. Description of the Related Art In measurement and evaluation of superconducting integrated circuits,
An AC bias current and some input signal pulses are required. Conventionally, in order to generate such a pulse signal,
Uses a pulse generator placed at room temperature. FIG. 6 is a schematic diagram of a circuit for measuring and evaluating a superconducting integrated circuit according to such a conventional technique.

In FIG. 6, one low-frequency AC bias signal (AC) and four input pulse signals IN1 to IN4 are provided.
Is required. These signals are supplied from, for example, five pulse generators (not shown) to the corresponding input terminals of the Josephson integrated circuit 10 under a low environment via the coaxial cable 2 and the resistors R1 to R4, respectively. Have been.

[0004] Outputs OUT1 to OUT3 of the Josephson integrated circuit 10 are led out through resistors R11 to R13, respectively. Note that this Josephson integrated circuit 10
Are arranged on the same chip together with the resistors R1 to R4 and R11 to R13.

[0005]

In the prior art shown in FIG. 6 described above, there is no problem when the clock signal frequency is low, but as the clock signal frequency increases,
The delay time difference between the signals caused by the jitter between the signals generated from the pulse generator and the slight difference in the length of the coaxial cable 2 becomes a serious problem. In particular, GH
In the case of a frequency in a band of z or higher, there is a disadvantage that the evaluation and measurement of the circuit operation become impossible.

Accordingly, the present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to make it possible to measure and evaluate a superconducting integrated circuit at a high frequency clock of several GHz or more. It is to provide a conduction high frequency clock operation evaluation circuit.

[0007]

According to the present invention, there is provided a superconducting high-frequency clock operation evaluation circuit for evaluating the operation of a superconducting integrated circuit with a high-frequency clock of a GHz band or more, wherein the superconducting integrated circuit is on the same chip as the superconducting integrated circuit. A plurality of superconducting quantum interference devices (SQUIDs) having a control signal input terminal and a bias input terminal, wherein an external DC power supply or a low frequency signal source is connected to each of the control signal input terminals;
A high-frequency signal source in the GHz band is connected to each of the bias input terminals, and each output terminal of the superconducting quantum interference device is connected to an input terminal of the superconducting integrated circuit. A circuit is obtained.

The signal from the high-frequency signal source is common to the bias signal of the superconducting integrated circuit, and the high-frequency signal source, the DC power supply or the low-frequency signal source is connected to the low-temperature signal of the chip. It is characterized by being arranged in a room temperature environment different from the environment.

Further, the DC power source or the low frequency signal source is connected to each of the control input terminals via a switch, and the switch is arranged in a room temperature environment. And

The operation of the present invention will be described. In the present invention, a well-known superconducting quantum interference device (SQUID: Superconducting
Quantum Interference Device) are arranged on the same chip as the superconducting integrated circuits, a DC power supply or a low-frequency signal source is connected to the control signal input terminal of each of these SQUIDs, and a high-frequency band over the GHz band is connected to the bias input terminal. A signal is supplied, and a signal pulse having a large cycle from a low-frequency signal source or a signal pulse having a large cycle due to ON / OFF of a DC power supply is supplied to a control signal input terminal. An output obtained by modulating a high-frequency signal in the GHz band using the pulse as a baseband signal is obtained and supplied to a necessary input terminal of the superconducting integrated circuit.

With this configuration, a plurality of input patterns of the superconducting integrated circuit can be supplied in synchronism with the bias current using a high-frequency clock in the GHz band, and the clock operation test of the superconducting integrated circuit in the GHz band can be performed. Becomes possible. GH to be supplied to the bias input terminal of each SQUID
As the z-band high-frequency signal, a high-frequency signal in the GHz band, which is a bias signal to be supplied to the superconducting integrated circuit, can be used in common, and the bias signal is distributed to the bias input terminal of each SQUID in the chip. As a result, there is no variation in the delay time due to the coaxial cable.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an SKU used in an embodiment of the present invention.
FIG. 3 is a diagram showing an equivalent circuit of a specific example of ID,
The D circuit itself is not new and has a known configuration. In the present invention, G is connected to the bias input terminal of this circuit.
A high frequency AC power supply in a Hz band is connected, and a DC power supply or a low frequency pulse signal source is connected to a control signal input terminal. Then, an output signal is derived from the output terminal.

Incidentally, J1 and J2 are Josephson junctions, Rb
, Rd, Ri, and RL indicate resistors, and L1 to L4 indicate inductors.

FIG. 2 shows an example of input / output waveforms of this circuit. A signal obtained by taking an AND logic of a sine wave high frequency signal (GHz) and a low frequency pulse (or direct current on / off) signal is provided at an output terminal. Is output. In other words, a signal obtained by modulating a high-frequency signal in the GHz band using the low-frequency pulse signal as the baseband signal is obtained at the output terminal.

The low-frequency signal pattern shown in FIG. 2 is usually generated by a low-frequency pulse signal generator. If the period is very long, the DC power supply is turned on and off by manual operation or the like. May occur.

As described above, by supplying a low-frequency signal pulse from the outside or by turning on and off a DC power supply externally, a high-frequency pulse signal modulated into a low-frequency signal pulse is generated in the chip. This enables a clock operation test in the GHz band. In this case, the SQUI
By disposing the required number of ID circuits on the same chip as the superconducting integrated circuit to be measured, and supplying the same high-frequency AC signal to the bias input terminal of each SQUID circuit, the phase inside the chip is substantially reduced. Can be supplied to the superconducting integrated circuit.

As described above, by applying a low-frequency pulse signal from the outside or turning on / off the DC power supply,
Inside the chip, it is possible to generate a plurality of high-frequency pulse signals having the same phase according to these external signals.
Therefore, a plurality of arbitrary input patterns can be input in synchronization with the high-bias current by using a high-frequency clock in the GHz band, and a clock operation test of the superconducting integrated circuit in the GHz band becomes possible.

In FIG. 1, a two-junction SQUID is used. However, a similar function can be realized by using another electromagnetic coupling type gate, for example, a three-junction SQUID.

FIG. 3 is a diagram showing the configuration of one embodiment of the present invention, and the same parts as those in FIG. 6 are denoted by the same reference numerals. In this example, a Josephson integrated circuit as the circuit under test 10 and necessary input terminals IN1 to IN1 of the circuit under test 10 are provided.
Plural SQUIS that supply high frequency signals to
D circuits 21 to 24 are arranged on the same chip 1. This chip 1 is placed in a low-temperature environment (for example, liquid helium temperature 4.2 K).

In a room temperature environment, a high frequency power supply AC, DC power supplies DC1 to DC4, and switches SW1 to SW4 for controlling ON / OFF of the DC power supply are provided. And
A plurality of coaxial cables 2 connect the chip 1 in a low-temperature environment and these power supplies in a room-temperature environment. Although not shown here, the output terminals OUT1 to OUT3 are connected to an observation device such as a high-bandwidth sampling oscilloscope.

Each SQUID circuit 21 to 24 in the chip 1
A high frequency power supply AC in the GHz band is connected to the bias input terminal of this embodiment, and this high frequency power supply AC is also used as a bias power supply for the Josephson integrated circuit 10, and is thus distributed within the chip. Since this distribution is laid out with wiring of approximately equal length in the chip, each SQ
High-frequency currents reaching the UID circuit and the Josephson integrated circuit are distributed in substantially the same phase.

DC power supplies DC1 to DC4 are connected to the control signal wiring of each SQUID circuit, and the current flowing through the control signal wiring can be turned on and off by switches SW1 to SW4 arranged at room temperature. Here, for example, the switch S
W1 and SW3 are turned on in advance, SQUIDs 21 and 23 are operable, and a high-frequency current in the GHz band is supplied to the chip, so that a pulse signal in the GHz range synchronized with the bias current of the Josephson integrated circuit 10 is supplied. (IN1 and IN3) can be generated.

According to this embodiment, the operation of the Josephson integrated circuit 10 can be measured and evaluated with a high frequency clock in the GHz range for all input signal patterns by a combination of DC on / off.

FIG. 4 is a diagram showing the configuration of another embodiment of the present invention, and the same parts as in FIG. 3 are denoted by the same reference numerals. In this example, a Josephson RAM is used as the circuit under test 10, and the high-frequency clock operation of the RAM is evaluated. Only parts different from FIG. 3 will be described.

When evaluating the operation of the RAM, many input signals such as an address signal, a data signal, and a read / write signal are required. Here, for simplicity, assuming a 64-bit RAM, a 6-bit address signal (Ax, B
x, Cx, Ay, By, Cy), a 1-bit data signal (Data), and a 1-bit read / write signal (R / W)
8 shows a case where a total of eight input signals are required.

Therefore, the eight SQUID circuits 21 to 28
Are provided on the same chip 1 in correspondence with these eight input signals. These eight SQUID circuits 21 to 28
Is connected to one high-frequency signal power supply (bias) line (AC) which also serves as a power supply line of the Josephson RAM. SQUID circuits 21 to 28
Here, the control signal wirings are two DC power supplies DC1 and D
Connected to C2.

The switches SW1 to SW8 respectively corresponding to the control signal wirings of the SQUID circuits 21 to 28 can be turned on and off individually. For example, by turning on only the switches SW1 and SW5 and inputting a high frequency signal in the GHz band, two high frequency signals of Data and R / W can be input to the bias of the RAM in synchronization with the signal.

As a result, writing of data "1" into the memory cell of the Josephson RAM having all addresses "0" can be repeatedly performed by the high frequency clock in the GHz range. Alternatively, for example, by turning on only the switches SW1, SW3 and SW8 and inputting a high frequency in the GHz range, the address of the Josephson RAM becomes (<110>).
x, <001> y), the data can be repeatedly read out by the high frequency clock in the GHz range.

By turning on and off the eight switches according to the present embodiment, operations such as writing and reading of data with a high-frequency clock to and from a memory cell at an arbitrary address are performed by G.
Measurement and evaluation can be performed using a high-frequency clock in the Hz range.

FIG. 5 is a diagram showing the configuration of another embodiment of the present invention, and the same parts as those in FIGS. Also in this example, the circuit under test 10 is a Josephson RAM, and therefore, a 6-bit address signal (Ax, Bx,
Cx, Ay, By, Cy), a 1-bit data signal (Data), and a 1-bit read / write signal (R / W) are required for a total of eight input signals.

Low frequency signal sources (pulse generators) P1 to P8 are provided corresponding to the control signal wirings of the eight SQUID circuits 21 to 28, respectively, and switches SW1 to SW8 are turned on and off in the circuit of FIG. Instead of this, in this example, it can be performed automatically with a low-frequency pulse pattern. Therefore, it is possible to generate an arbitrary input signal pattern by combining these pulse patterns.

According to this embodiment, only by adding a low-frequency input signal pattern, a high-frequency input pulse synchronized with a high-frequency bias current is generated in the chip in accordance with the low-frequency input signal pattern. Operations such as writing and reading of data with respect to a memory cell of an address with a high-frequency clock can be measured and evaluated with a high-frequency clock in the GHz range.

[0034]

As described above, according to the present invention, the jitter between input signals and the delay between signals caused by a slight difference in the length of a coaxial cable when evaluating the high-frequency clock operation of a superconducting integrated circuit. There is an effect that a large problem such as a time difference can be eliminated. Thus, the measurement and evaluation of the superconducting integrated circuit can be performed using the high-frequency clock in the region of GHz or more.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing an example of a SQUID circuit used in the present invention.

FIG. 2 is a waveform chart showing the operation of the circuit of FIG.

FIG. 3 is a diagram showing one embodiment of the present invention.

FIG. 4 is a diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing another embodiment of the present invention.

FIG. 6 is a diagram illustrating a conventional technique.

[Explanation of symbols]

 1 chip 2 coaxial cable 10 circuit under test 21-28 SQUID circuit AC high frequency power supply DC1-DC4 DC power supply SW1-SW4 switch P1-P8 low frequency power supply

Claims (6)

(57) [Claims] 1. A superconducting high-frequency clock operation evaluation circuit for evaluating the operation of a superconducting integrated circuit with a high-frequency clock of a GHz band or more, comprising a control signal input terminal and a bias input disposed on the same chip as the superconducting integrated circuit. And a plurality of superconducting quantum interference devices (SQUIDs) having an input terminal, an external DC power supply or a low-frequency signal source connected to each of the control signal input terminals, and a G input to each of the bias input terminals.
A superconducting high-frequency clock operation evaluation circuit, wherein a high-frequency signal source in a Hz band is connected, and each output terminal of the superconducting quantum interference device is connected to an input terminal of the superconducting integrated circuit. 2. The superconducting high-frequency clock operation evaluation circuit according to claim 1, wherein a signal from said high-frequency signal source is common to a bias signal of said superconducting integrated circuit. 3. The super-high-frequency signal source according to claim 1, wherein the high-frequency signal source, the DC power source, or the low-frequency signal source is arranged in a room temperature environment different from a low-temperature environment of the chip. Conducted high frequency clock operation evaluation circuit. 4. The superconducting high-frequency clock according to claim 1, wherein the DC power supply or the low-frequency signal source is connected to each of the control input terminals via a switch. Operation evaluation circuit. 5. The superconducting high-frequency clock operation evaluation circuit according to claim 4, wherein said switch is arranged in a room temperature environment. 6. The superconducting high-frequency clock operation evaluation circuit according to claim 1, wherein said superconducting integrated circuit is a Josephson integrated circuit.