JPS61117472A - Test system - Google Patents

Abstract

PURPOSE:To reduce the influence of a noise from a digital test module to an analog system in a test system which tests the digital and analog systems simultaneously by passing a digital system test signal through an optical transmitting means. CONSTITUTION:A digital system test signal and an analog system test signal are applied simultaneously to the digital system test module TML1 and analog system test module TML2 for objects to be tested and the both are tested simultaneously. In this case, the digital system test signal is a relatively fast pulse signal and the analog system test signal is a wide-range low-level signal. Therefore, when a test module TMLi is connected to a test head THD through an electric signal line Lbi, the digital system TML1 becomes a high-level noise source and affects the analog system TML2, which is not tested stably. For the purpose, the digital system test signal is transmitted through optical interfaces OIFa and OIFb and an optical fiber OF to reduce the influence of a noise, thereby testing the analog system and digital system simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a test system, and more specifically, it connects a digital test module and an analog test module to a test object, and The present invention relates to an improvement of a test system configured to perform a digital test and an analog test in parallel while simultaneously applying a system test signal and an analog test signal.

(Prior Art) One type of test system is an analog LSI test system.

FIG. 4 is a block diagram showing an example of such a conventional system. In FIG. 4, TRM is an operation terminal, TSM is a test system manager, TSC is a test system controller, MDC is a module controller, TML is a test module, and THD is a test head. For example, the TRM is equipped with a CRT,
It has functions to create programs necessary to execute test operations in each TML, and to monitor and record test results in each TML. Programs created in TRM are managed as files in TSM, compiled, and sent to TSC. TSC memorizes the test contents added by TSM and writes them to each MD.
Sends information for each test to C. The MDC creates setting information for tests to be performed by each TML when loading a program before a test, and sends the created setting information to each TML for each test. The TML has at least one function as a measuring device or a generator, such as a voltmeter, a 1M current meter, a voltage generator, or a waveform generator. THD includes test objects (analog and digital in the case of this system).

A hybrid LSI (LSI such as a hybrid) is arranged, and signal lines from each TML are connected. Here, TRM.

The SM and TSC are each connected by a serial bus 8B, the TSC and each MDC are connected in parallel by a data bus DB, and the MDC and TML and TML and THD are connected by electric signal lines 1a and lb, respectively.

In such a configuration, various unique data of each TML turtle is sent from the TSC to each MOC via the O8.

TSC also assigns sequence numbers to each MD for each test.
Send it to C. On the other hand, each MDC selects configuration data for configuring the operation of each TML based on the sequence number added from the TSG. And each block M L G
, tT according to the synchronization signal sent from TSC
A predetermined test operation is performed on the LSI placed in the HD, and the test results are read by each MDC.

(Problems to be Solved by the Invention) By the way, in such a test system, digital TML (for example,
A digital test signal is added from an analog TML (for example, ML).

An analog test signal is added from TML2>, and digital tests and analog tests may be performed simultaneously in parallel. In this case, a relatively high-speed pulse signal (for example, several tens of MHz) is used as the digital test signal,
As an analog test signal, a wide band (DC to several hundred
MHz), low level < OC, several μV, several nA, i frequency r G, t -100 dBIll or less, but 50 Ω
It often handles signals with an impedance of 111W and a power level of Od 81.

However, according to such conventional NIT, each TML
Since the THD and THD are connected by the electric signal line 1b, the digital TML+ becomes a high-level noise source and has a negative effect on the analog TML2, making it difficult to stably perform low-level analog tests. Sometimes there isn't. Further, in the conventional system, a series control type power supply device is used to prevent radiation from the power supply unit, which results in an increase in size, weight, and cost of the power supply unit.

The present invention has been made with attention to such points, and its purpose is to reduce the influence of noise from a digital test module to an analog test module,
The purpose of the present invention is to provide a test system that can perform high-precision, high-sensitivity analog tests in parallel with digital tests.

(Means for Solving the Problems) The present invention achieves the above object by connecting a digital test module and an analog test module to a test object, and transmitting a digital test signal and an analog test signal. The test system is configured to perform a digital test and an analog test in parallel while simultaneously applying a digital test signal, and is characterized in that the digital test signal is transmitted via an optical transmission means.

(Example) Hereinafter, it will be explained in detail using the drawings.

FIG. 1 is a block diagram not showing one embodiment of the present invention,
Parts equivalent to those in FIG. 4 are given the same reference numerals. In FIG. 1, 0(Fa is an opto-interface connected to the TMLr side of the digital system, 0IFb is an opto-interface connected to the THD side, and OF is an optical fiber that transmits the digital system test signal.

FIG. 2 is a block diagram showing an example of a main part of the digital test block in FIG. 1. In FIG. 2, CTL is a control unit that controls the test operation of the digital system, and the pattern generator PTG on the TMLr side
, comparison memory CM and comparison voltage generator RVG on the THD side
, the set voltage generator SVG, etc., respectively, and the comparison result data [)C+++ is added from the CM. PTG is opto-interface 01Fa + ~0IFa 3 and optical fiber OF1~.

F3 and opto-interface 0rFl)+~0IF
A clock C is sent to the THD via an optical transmission means consisting of t13.
L, transmits the pattern data Sod and the try date signal Sts, and also transmits the reference pattern R.
1) Send d. Note that the CM is provided with a delay means for arranging the reference patterns R1) d added from P T G h' in a vibratory manner.

The clock OL and pattern data Sod transmitted to the THD are added to a pulse processing circuit PM that has the function of latching pattern data 3pcl and converting it into a predetermined pattern signal.6PM adds an output pulse Sop via an optical transmission means. A tri-state driver DRV is controlled by a tri-state signal StS to put the output in a high-impedance state. The returned clock RCL is connected to the optical interface 0IFb4,
Optical fiber OF a and opto interface 0IF
It is sent to the CM via an optical transmission means consisting of a4. Here, when the tri-state signal 3ts is on, the output impedance of the DRV becomes high and it is virtually disconnected from the LSI, and when the tri-state signal 3ts is off, the DRV is tested according to the output pulse Sop of the PM. The pattern signal Stp will be applied to the LSI. By connecting two sets of RVs in parallel and controlling each DRV with a tri-state signal Sts, it is possible to apply a ternary test pattern signal Stp to the LSI, but in Fig. 1, only one DRV is connected. It shows.

Note that the output voltage of DRV can be set by the output voltage VdV of SVG. CMP is a comparator that compares the LSI output voltage 0 with comparison voltages vh and vl output from RVG, and its output signal sh is an opto interface 0IFtls.

Optical fiber OF5# and opto interface 0IFa
It is sent to the CM via an optical transmission means consisting of 5, and Sl is an opto interface OIFj1g.

Optical fiber 0F6J5 and opto interface 0jF
The signal is sent to the CM via an optical transmission means consisting of aG. Then, CM is li1 pattern R added from PTG.
The pd is compared with the measurement signal 31+ applied from the CMP and the pattern of Sl according to the RCL applied from the PM. Note that the control signal S for controlling RVG and SVG
C' 3 is opto-interface ○IFay, optical fiber OFv and opto-interface OIF b
The signal is sent to the THD via an optical transmission means consisting of 7.

FIG. 3 is a time chart showing an example of signal transmission in such a configuration, where (a) shows the clock signal CL transmitted from the PTG to the PM, and (b) shows the pulse signal transmitted from the PTG to the PM. Data 3pcl is shown, (C
) shows the output pulse Sop applied from the PM to the DRV, (d) shows the test pattern signal Stp applied from the DRV to the LSI, and (e) shows the return clock RCL transmitted from the PM to the CM. Here, the frequency fc of the clock signal CL is set to, for example, 10 times the frequency "d" of the data rate.
By transmitting the pulse data Sod in synchronization with the clock signal CL, the gap between multiple channels can be corrected in units of cycles of the clock signal CL, and from the PM, the output pulse Sod without deviation inherent to optical fibers can be corrected. can be obtained. Note that with this, only the transmission line for the clock CL needs to be made compatible with high speed, and the other transmission lines may not be capable of high-speed response like the clock transmission line. On the other hand, RCL is given a delay time td that is approximately equal to the delay time caused by DRV and CMP with respect to the output pulse Sop applied from PM to DRV.

As a result, the CM is able to control the reference pattern Rpd added from the PTG and the CM corresponding to the reference pattern R1)d.
The patterns of the measurement signals sh and sl applied from P can be sequentially compared in a synchronized state.

With this configuration, digital T M
between L + and T l-11) OF + ~ OF 7
Because there is no interference between the analog test signal line and the analog test signal line due to radiation from the electric signal line as in the past (
As a result, it is possible to conduct analog system tests in parallel with digital tests in ultra-low noise and conditions.
Since M L + and T l-I D can be maintained at different ground potentials, the LSI to be tested can be installed at an optimal location.

In addition, since the effects of radiation can be reduced, a small, time-saving and low-cost switching power supply can be used as a power supply, and the space factor of the entire device can be improved, and it can also be made lighter and lower in cost. Furthermore, the limit value of the test object can be measured without creating a special measurement environment, and the test throughput can be increased.

Note that in the above embodiment, the test object is an analog LSI.
This example is applicable to test systems for various objects.

Further, in the above embodiment, an example was shown in which the ORV and CMP of the TML are connected to the LSI in common to control the DRV, thereby effectively turning on or turning off the DRV.
Connect RV to the designated input bin of LS and connect CMP to LS
It may be connected to a predetermined output bin of I.

Further, a comparison memory may be provided in T-ID.

Alternatively, light may be used in an analog manner, and the output signals of DRV, I, and CMP may be transmitted in analog form.・ (Effects of the invention!!) As explained above, according to the present invention, the influence of noise from the digital test module to the analog test module is reduced, and high-precision, high-sensitivity analog tests can be performed digitally. It is possible to realize a test system that can simultaneously perform system tests in parallel.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the main part of the digital test block in FIG. 1, and FIG. 3 is a block diagram showing an example of the main part of the digital test block in FIG. A time chart showing an example, and FIG. 4 is a 110 block diagram showing an example of a conventional device.
TL...Digital test control unit, PTG...Pattern generator, CM...Comparison memory, THD...
・Test head, PM...Pulse processing circuit RVG...
・Comparison voltage generator, SVG...setting voltage generator, CM
P...Comparator, OIF...Opto interface, OF...Optical fiber. LSI...Test object. Figure 1

Claims (1)

[Claims] A digital test module and an analog test module are connected to the test object, and the digital test and analog test are performed in parallel while applying the digital test signal and the analog test signal simultaneously. A test system characterized in that a digital test signal is transmitted via an optical transmission means.