JP3029253U - Monitor identification information control device - Google Patents

Abstract

(57) [Abstract] [Issue] DDC1 / DDC2B / DDC2A required by VESA Federation
Provide a monitor identification information control device conforming to B. A monitor identification information control device 213 is provided in a monitor 2 having a microprocessor 21 and a storage device 22 and reads monitor identification device information from the storage device 22.
, A data buffer device 2131 for receiving monitor identification information stored in the storage device 22 by the microprocessor 21, and a multiplex control determination for outputting a first or second input signal used as a shift clock pulse. A monitor identification information control device comprising a device 2132 and a data shift comparison device 2133.

Description

[Detailed description of the device]

[0001]

[Technical field to which the device belongs]

 The present invention relates to a control device, and more particularly to a monitor identification information control device applied between a monitor and a computer body.

[0002]

[Prior art]

 At present, the communication method between the computer body and the monitor is moving toward the trend of digital control. In other words, it is essential for the monitor to carry out signal judgment, read the related data again, convert it into a voltage, and transmit it to the device in the subsequent stage of each related control to control it. In the technology of reading and identifying monitor identification information (Extended Display Indentification, EDID), it is not necessary for the user to easily use the peripheral devices of the computer and to know the operating environment of software and hardware standards inside the monitor It has already become the mainstream of development by monitor manufacturers that they can be plugged in and used.

Regarding the access of this EDID, in order to promote the unification and standardization of each monitor maker, the VESA Federation, in particular, has a vertical synchronization signal (Vertical SYNC, Vertical Sync Signal) transmitted by the VGA card included in each computer main body. VSYNC or VCLK) and IIC bus developed by Philips (including 2 signal terminals of SCL and SDA) are used to meet various EDID access requirements. A standard has been set to meet the requirements.

DDC1: VDI is used as a clock pulse, and EDID data stored in the monitor is transmitted to the computer main body through the SDA signal terminal (one-way transmission) DDC2B: IIC bus is transmitted in two directions between the computer main body and the monitor The channel.

DDC2AB: An access bus with an IIC bus as a framework is used as a two-way transmission channel between a computer main body and a monitor.

However, all monitor manufacturers employ the following two types of conventional methods to access EDID.

(A) An EEPROM that uses the EEPROM as a storage medium for storing EDID data is added, and the EDID data is read via the IIC bus.

This type of system includes two types of standards, DDC1 and DDC2B, but has the following drawbacks.

(1) This type of method increases the circuit board space.

(2) The manufacturing cost is increased.

(B) D DC1 is simulated by the input / output pin (I / O pin) of the microprocessor and the vertical synchronizing signal. If the microprocessor has an IIC bus, the DDC2B is simulated by using the IIC bus under software control. However, the following deficiencies existed.

(1) The transmission effect of DDC1 / DDC2B does not reach the standard established by VESA. This method uses the VSYNC signal to generate an interrupt, reads the EDID data within the execution period of the interrupt service routine, and once a bit is judged to be "HI" or "LOW", it is reset again. In the method of outputting one set of E DID data with the I / O port set or reset, the execution time of the software interrupt service routine is limited, and the transmission speed of DDC1 (25 Kbits) required by VESA is limited. / sec) cannot be satisfied.

(2) The VESA Federation requires any monitor to meet at least one of the standards DDC1 / DDC2B or DDE1 / DDC2B / DDC2AB. However, it is clear that this method cannot satisfy this.

(3) Since this method adopts firmware as a control, the coding of the firmware becomes long and more complicated.

[0015]

[Problems to be solved by the device]

 The main object of the present invention is to provide a monitor identification information control device that conforms to DDC1 / DDC2B / DDC2AB required by the VESA Federation.

Another object of the present invention is to provide a monitor identification information control device having a structure capable of reducing the capacity of SRAM in the microprocessor required for storing EDID, and to reduce the manufacturing cost of the monitor.

Yet another object of the present invention is to provide a monitor identification information control device that shortens the EDID processing time of a microprocessor.

[0018]

[Means for Solving the Problems]

 In order to achieve the above object, the monitor identification information control device according to the present invention is provided in a monitor having a microprocessor and a storage device, and is input to a computer main body through first to third signal terminals. A monitor identification information control device for reading monitor identification device information from the storage device by applying first to third input signals, wherein the monitor identification information control device stores the monitor identification information stored in the storage device by the microprocessor. A data buffer device for receiving and a first or second input signal connected to the first to third signal terminals and used as shift clock pulses, respectively, corresponding to the signal state of the first input signal. Connected to the multiplex control discriminating device for outputting the data buffer device, the multiplex control discriminating device and the third signal terminal. When the multiplex control discriminating apparatus outputs the first input signal used as the shift clock pulse signal, the microprocessor is responsive to the address state in the third input signal to cause the microprocessor to store the storage device. Output of the monitor identification information from the storage device is stopped, or the computer main body can sequentially read the monitor identification information through the third input terminal, or the computer main body can read the external data. When the multiplex control discriminating device outputs the second input signal, the data shift comparing device is made to directly receive the monitor identification information from the data buffer device. Equipped with a data shift comparison device for sequentially shifting output from the third signal terminal to the computer body To have.

In a preferred embodiment of the monitor identification information control device, the first, second and third signal terminals are an SCL signal terminal, a VSYNC (vertical synchronization signal) and an SDA signal terminal, respectively, The monitor identification information is a set of EDID (Extended Display Identification), the multiplex control discriminating device is connected to the first and third signal terminals, and corresponds to a signal state of a first input signal. A control discriminating device for generating and outputting a multiplex selection signal and selectively deciding whether to start or stop the transmission operation of the monitor identification information according to the third input signal, and the first and second signal terminals. Connected to a control discriminating device and a data shift comparing device, the first input signal and the second input signal are input in accordance with the first and second selection states of the multiplex selection signal, respectively. It has a multiplex selection device that outputs to the data shift comparison device.

Further preferably, the control determination device transmits the monitor identification information by detecting a signal state of the third input signal in response to a start (START) signal and a stop (STOP) signal. The start or stop of the operation should be selectively determined.

In a preferred embodiment of the monitor identification information control apparatus, when the first input signal is in a high level state, the multiplex selection signal is in the second selection state. When the second input signal is output from the selection device or when the first input signal changes from the high level signal state to the low level signal state, the multiplex selection signal becomes the first selection state. , The first input signal is output from the multiplex selection device.

Further, when the first input signal is in the low level state, the multiplex selection signal is in the second selection state, and the second input signal is output from the multiplex selection device. , Or when the first input signal changes from the low-level signal state to the high-level signal state, the multiplex selection signal becomes the first selection state, and the multiplex selection device outputs the first input signal. You may make it output a signal.

The first and second selected states can be a high level state or a low level state, respectively.

Further, the first and second selected states may be a low level state or a high level state, respectively.

The multiplex selection device may be a 2: 1 multiplexer.

Further, in a preferred embodiment of the monitor identification information control device, the data shift comparison device is connected to the third signal terminal, the data buffer device and the multiplex control device, and outputs the shift clock pulse signal as the shift clock pulse signal. According to the first or second input signal used, the third input signal or the monitor identification information stored in the data buffer device is read and the monitor identification information is sequentially output to the third signal terminal. A shift register for sequentially storing the external data in the data buffer device, an address storage device for storing at least two sets of fixed addresses, and a third input connected to the shift register and the address storage device. The address state of the signal is the same as one of the at least two fixed addresses If the comparison result is the same, the shift register executes the shift-in or shift-out operation of the monitor identification information or the external data. An address comparator that stops the microprocessor from outputting the monitor identification information from the storage device.

Further, the data shift comparator preferably comprises an input / output buffer device connected between the third signal terminal and the shift register and providing a signal buffer function.

The storage device may be an electronic erasable program ROM (EEPROM).

The storage device may include a static storage device (SRAM) and a read-only storage device (ROM).

The variable and fixed parts of the monitor identification information are stored in the EEPROM and the ROM, respectively, and the monitor identification information can be directly accessed.

Further, both unique data of the monitor identification information and direct related data are stored in the EEPROM, and the ROM stores a memory of the unique data and the direct related data. A pointer address may be stored so that the monitor identification information is indirectly accessed.

[0032]

[Action]

 When the user complies with the DDC1 standard defined by the VESA Federation and the user reads EDID data from the storage device and outputs it to the computer main body, the SCL signal input to the control discrimination device from the SCL signal terminal goes to a high level state. Yes, the mode flag register DDC is in the “LOW” state. Therefore, if the multiplex selection device 21322 outputs the VSYNC signal to the shift register, the EDID data input by the data buffer and stored in the shift register can be directly output to the computer main body. it can.

When the user complies with the DDC2B or DDC2AB standard defined by the VESA Federation and the user reads the EDID data from the storage device and outputs it to the computer main body, the SCL signal changes from the high level state to the low level state. Then, the 1-series clock pulse signal is output, and at the same time, the mode flag register DDC becomes the “HI” state via the control determination device in response to the signal change edge changing from the high level state to the low level state.

[0034]

[Embodiment of device]

 Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is an exemplary view of a preferred embodiment of the present invention, which comprises a computer main body 1 and a monitor 2. The computer main body 1 has an SDA signal terminal, an SCL signal terminal, and a VSYNC signal terminal from a VGA card (not shown), and the SDA and SCL signal terminals form an IIC bus. Needless to say, the VSYNC signal terminal is for inputting the VSYNC signal, and the SCL signal terminal is for inputting the SCL signal.

The monitor 2 includes a microprocessor 21 and a storage device 22 (for example, EEPROM), and the microprocessor 21 has a static storage device (SRAM) 211, a read-only storage device (ROM) 212, and a monitor identification. An information controller 213 and a data bus 214 are provided. The monitor identification information control device 213 includes a data buffer device 2131, a multiplex control determination device 2132, and a data shift comparison device 2133. The multiplex control determination device 2132 includes a control determination device 21321 and a multiplex selection device. 21322, and the data shift comparison device 2133 includes a shift register 21331, an address storage device 21332, an address comparator 21333, and an input / output buffer device 21334.

Further, R / W, ADDR, DDC, START, and STOP in FIG. 1 are a read / write flag register, an address comparison result flag register, a mode flag register, a signal start flag register, and a signal stop flag register, respectively. .

Next, the principle of operation of the block shown in FIG. 1 will be described so that the technical idea of the present invention may be better understood.

First, the DDC1 standard defined by the VESA Federation is applied, and when ED ID data is read from the storage device 22 and output to the computer main body 1, it is input from the SCL signal terminal into the control determination device 21321. The SCL signal is in the high level state and the mode flag register DDC is in the “LOW” state. Therefore, when the multiplex selection device 21322 outputs the VSYNC signal to the shift register 21331, the EDID data input from the data buffer device 2131 and stored in the shift register 21331 is directly input to the computer main unit 1. Can be output to.

When the DDC2B or DDC2AB standard defined by the VESA Federation is applied and the EDID data is read from the storage device 22 and output to the computer body 1, the SCL signal changes from the high level state to the low level state. Then, a 1-series clock pulse signal is output. At the same time, in response to the signal change edge from the high level state to the low level state, the mode flag register DDC becomes the “HI” state via the control determination device 21321.

Furthermore, when the control determination device 21321 receives an input signal (including an address state) from the SDA signal terminal and an appropriate flag corresponding to each of the signal start flag register START and the signal stop flag register STOP is generated, The plex selector 21322 outputs the SCL signal. Therefore, the input signals input from the SDA signal terminal via the input / output buffer device 21334 are sequentially stored in the shift register 21331.

An address comparator 21333 compares the address state of the third signal with a set of addresses (for example, 1010000) in the address storage device 21332. The comparison result being “HI” (stored in the address comparison register ADDR) indicates that the addresses are the same, and in this case, the DDC2B mode is entered. Otherwise, if the previous address state and another set of addresses in the address storage device 21332 (the value of which can be set by the user) are the same, the DDC2AB mode or the mode set by the user himself. to go into. Needless to say, when the address state is different from either of the two sets of addresses stored in the address storage device 21332, it means that it is error information, and the monitor identification information control device 213 does not store any EDID. No access operation is performed.

If this is the DDC2B mode and the flag state in the read / write flag register is “HI” (indicating the READ state), the shift register 2 1331 corresponds to the SCL signal as the shift clock signal. Then, the EDID data input by the data buffer device 2131 is sequentially shifted and output to the computer main body 1.

Similarly, if the read / write flag register is “LOW” (that is, the WRITE state), the computer main body 1 shifts the external data via the input / output buffer device 21334 corresponding to the SDA signal and the SCL signal. Write on 21331. After that, when the external data is completely shifted into the shift register 21331, the external data is automatically output to the data buffer device 2131, and the microprocessor 1 reads the external data.

By the way, the data buffer device 2131 has a function of taking out in advance. The reason is as follows.

For example, every 9 VSYNC signals, the EDID data in the shift register 21331 is completely shifted out, the EDID data in the data buffer device 2131 is loaded into the shift register 21 331, and the next VSYNC signal comes. Sometimes EDID data can be transmitted. Therefore, when the EDID data in the data buffer device 2131 is output to the shift register 21331, the discrimination control device 21321 automatically generates an interrupt signal (see the symbol INTO in FIGS. 2 to 4). , And notifies the microprocessor 21. At this time, the interrupt service routine of the microprocessor 21 shifts in the next set of EDID data to the data buffer 2131 for transmission. By doing so, the transmission speed of EDID data is accelerated.

FIGS. 2 to 4 are timing charts in the case of reading EDID using the preferred embodiment of the present invention, taking DDC1 and DDC2B as examples. FIG. 2 is a timing chart of a state in which EDID data is output from the data buffer device 2131 to the computer main body 1 in the DDC1 mode, and FIG. 3 is a timing chart of a state in which the computer main body 1 reads the data in the DDC2B mode. FIG. 4 is a timing chart of a state in which the computer main body 1 executes data writing in the DDC2B mode. 2 to 4, S is a start status bit, P is a stop status bit, A is a confirmation signal bit, and N is a non-confirmation signal bit. Further, the signal state diagrams disclosed in FIGS. 2 and 3 are well known to those skilled in the art and will not be described.

Furthermore, the EDID data stored in the microprocessor 21 and the storage device is divided into the following two types according to the data structure.

1. Data that does not change regardless of monitor type.

2. Data that changes depending on the type of monitor.

Therefore, if the structure of the entire data of the EDID is understood, the usage amount of the static memory 211 in the macro processor 21 can be reduced by the storage structure and access method enumerated below of the present invention.

(A) When EDID data is directly read (a1) Hardware storage structure part EDID data is divided into two parts. One is a variable part (FE in FIG. 5) stored in the ROM 212 in the microprocessor 21, and the other is a variable part (VE in FIG. 5) stored in the storage device 22. . When the microprocessor 21 is activated, first of all, the EDID data stored in the storage device 22 is shifted into the SRAM 211, and then the EDID data is sequentially transmitted to the computer main body 1 under the control of software.

(A2) Software Read / Write Method After the microprocessor is activated, two parts of the EDID data are stored in the SRAM 211 and the ROM 212, respectively. Then, the software determines the start address, the threshold address, and the final address of the EDID data, and transmits the EDID data byte by byte to the data buffer device 2131.

(B) When the EDID data is read indirectly (b1) The hardware storage structure part EDID data is rearranged and only n bytes are left as “directly related data” and the remaining data is duplicated. Delete the deleted data and leave only the uniqueness data (the one with no duplicate data). The "uniqueness data" and the "directly related data" (code EDID 'in FIG. 6) are stored in the storage device 22. The ROM 212 in the microprocessor 21 has a space of 128 bytes, and each byte serves as a pointer (address) for indexing the address of the SRAM 211 that stores EDID 'data. When the microprocessor 21 is activated, the EDID 'data is transmitted from the storage device 22 to the SRAM 211 in the microprocessor 21, and the EDID' data is finally transmitted to the computer main body 1 by software program control.

(B2) Software read / write method After reading data indirectly and reading 128 bytes from the start point of the index storage area, the EDID 'data is output to the computer main body 1. This state is shown in FIG.

[0055]

[Effect of device]

 According to the method of the present invention, not only the manufacturing cost of the monitor is reduced, but also the monitor identification information control device which is suitable for any of DDC1 / DDC2B / DDC2AB defined by the VESA Federation can be provided. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a preferred embodiment of the present invention.

FIG. 2 is a timing chart in the example of FIG. 1 in a state where EDID data is output from the data buffer device 2131 to the computer main body in the DDC1 mode.

FIG. 3 is a timing chart in the example of FIG. 1 in a state where the computer main body 1 reads data in the DDC2B mode.

FIG. 4 is a timing chart in the example of FIG. 1 in a state where the computer main body 1 executes data writing in the DDC2B mode.

FIG. 5 is an explanatory diagram showing an example of a storage structure for storing an EDID by a direct storage method in the device of the present invention.

FIG. 6 is an explanatory diagram showing an example of a storage structure for storing EDID by an indirect storage method in the device of the present invention.

[Explanation of symbols]

 1 Computer Main Body 2 Monitor 21 Microprocessor 22 Storage Device 211 SRAM 212 ROM 213 Monitor Identification Information Control Device 214 Data Bus 2131 Data Buffer Device 2132 Multiplex Control Discrimination Device 2133 Data Shift Comparison Device 21331 Shift Register 21332 Address Storage Device 21333 Address Comparator 21334 Input / output buffer device

Claims (8)

[Scope of utility model registration request] 1. A monitor provided with a microprocessor and a storage device, wherein the first to third input signals are input to the computer main body through the first to third signal terminals, thereby A monitor identification information control device for reading monitor identification device information from a storage device, wherein the microprocessor is connected to a data buffer device for receiving monitor identification information stored in the storage device, and the first to third signal terminals. And a multiplex control discriminating device which outputs a first or second input signal used as a shift clock pulse in accordance with the signal state of the first input signal, the data buffer device, and multiplex control. A discriminating device and a third signal terminal are connected, and the multiplex control discriminating device is connected to the shift clock. When the first input signal used as a pulse signal is output, the microprocessor stops the output of the monitor identification information from the storage device in accordance with the address state in the third input signal, or The computer main body can sequentially read the monitor identification information through the third input terminal, or the computer main body can sequentially write the external data to the data buffer device, and the multiplex control discriminating device is the second one. And a data shift comparing device for allowing the data shift comparing device to directly receive the monitor identification information from the data buffer and output the input signal to the computer main body in sequence from the third signal terminal. Monitor identification information control device. 2. The first, second and third signal terminals are an SCL signal terminal, a VSYNC signal (vertical synchronization signal) terminal and an SDA signal terminal, respectively, and the monitor identification information is a set of EDID (Extended Displ).
ay Identification), wherein the multiplex control determination device is connected to the first and third signal terminals, generates and outputs a multiplex selection signal according to a signal state of a first input signal, and outputs the multiplex selection signal. Connected to the control determination device that selectively determines the start or stop of the transmission operation of the monitor identification information according to the input signal of, and the first and second signal terminals, the control determination device, and the data shift comparison device, 2. A multiplex selection device that outputs one of the first and second input signals to the data shift comparison device according to the selection state of the multiplex selection signal. The monitor identification information control device described. 3. The control determination device starts or stops the operation of transmitting the monitor identification information by detecting the signal state of the third input signal in response to a start (START) signal and a stop (STOP) signal. 3. The monitor identification information control device according to claim 2, wherein the multiplex selection device is a 2: 1 multiplexer. 4. The selection state of the multiplex selection signal comprises a first selection state and a second selection state, and the first selection state
When the input signal is in the high level state, the multiplex selection signal is in the second selection state and outputs the second input signal from the multiplex selection device, or the first input When the signal changes from a high level signal state to a low level signal state, the multiplex selection signal is in a first selection state and outputs a first input signal from the multiplex selection device, or When the input signal is in the low level state, the multiplex selection signal is in the second selection state and outputs the second input signal from the multiplex selection device, or the first input signal is When the low level signal state changes to the high level signal state, the multiplex selection signal becomes the first selection state, and the multiplex selection device Output the first input signal from the first selected state is a high level state and the second selected state is a low level state, or
3. The selected state of is a low level state and the second selected state is a high level state.
The monitor identification information control device described. 5. The data shift comparison device is connected to the third signal terminal, a data buffer device, and a multiplex control device, and receives the first or second input signal used as the shift clock pulse signal. Accordingly, the third input signal or the monitor identification information stored in the data buffer device is read, the monitor identification information is sequentially output to the third signal terminal, and the external data is sequentially shifted to the data buffer device. A shift register for storing, an address storage device for storing at least two sets of fixed addresses, connected to the shift register and the address storage device,
It is compared whether the address state of the third input signal is the same as one of the at least two sets of fixed addresses, and if the comparison result is the same, the monitor identification information or the external And an address comparator that executes a data shift-in or shift-out operation, and conversely stops the microprocessor from outputting the monitor identification information when the comparison results are not the same. The monitor identification information control device according to claim 1. 6. The data shift comparison device comprises:
And an input / output buffer device that provides a signal buffer function, the memory device being an electronic erasable program ROM (EEPROM), and the memory device is a static memory. 6. The monitor identification information control device according to claim 5, further comprising a storage device (SRAM) and a read-only storage device (ROM). 7. In the monitor identification information, the variable and fixed portions of the monitor identification information are the EEPROM and ROM, respectively.
7. The monitor identification information control device according to claim 5, wherein the monitor identification information is stored in the monitor identification information and is directly accessed. 8. In the monitor identification information, both uniqueness data and direct related data of the monitor identification information are stored in the EEPROM, and the ROM stores the uniqueness data and direct related data. 6. The monitor identification information control device according to claim 5, wherein the monitor identification information is indirectly accessed, and the monitor identification information is indirectly accessed.