CN117931404A - Multi-application switching method, device, equipment and medium based on FPGA - Google Patents
Multi-application switching method, device, equipment and medium based on FPGA Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F9/48—Program initiating; Program switching, e.g. by interrupt
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Abstract
The application relates to the technical field of network function test, and discloses a multi-application switching method, device, equipment and medium based on FPGA. The target start address and enable signal are resolved from the switch image instruction. When the enabling signal is the switching image enabling signal, according to the data format requirement of the drive processor of the FPGA, the instruction information of the switching image instruction is written into the drive processor, and the target starting address is written into the first-in first-out queue, so that the switching of the application program is realized based on the drive processor and the safety equipment manager. When the initial address of the application program carried in the read response data is matched with the target initial address, loading a burning file matched with the target initial address in the memory chip to execute the testing function corresponding to the application program. Reducing hardware cost and circuit design complexity.
Description
Technical Field
The application relates to the technical field of network function testing, in particular to a multi-application switching method, device, equipment and medium based on an FPGA.
Background
The Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) is widely applied to various industries according to the characteristic of reconfigurability of circuit design, and a.rpd or. jic file generated by compiling engineering is generally programmed into a nonvolatile memory (FLASH) externally connected with the FPGA, and the file in the FLASH is loaded into the FPGA after power-on so as to realize certain specific functions. Aiming at some high-end instruments and meters, the device has a plurality of complex functions, a specific function is burnt in each FLASH file, a plurality of FLASH chips are connected outside an FPGA, and the functions in different FLASH are realized through the chip selection circuits by combining with specific chip selection circuits.
At present, although a plurality of FLASH chips can be connected through an external chip selection circuit of the FPGA, the method increases the quantity of the FLASH chips. When the specific functions to be realized are more, a larger number of FLASH chips are required to be added, so that the cost is high, the circuit design is relatively complex, the functions can not be completely realized at one time in the circuit design, and the circuit can be frequently debugged repeatedly.
It can be seen how to reduce the hardware cost and the complexity of the circuit design is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the application aims to provide a multi-application switching method, device, equipment and medium based on FPGA, which can reduce hardware cost and circuit design complexity.
In order to solve the above technical problems, an embodiment of the present application provides a multi-application switching method based on FPGA, including:
Combining compiled files corresponding to a plurality of application programs to generate a burning file, and storing the burning file into a unified memory chip; the burning file records a starting address and a memory use page corresponding to each application program;
Under the condition that a switching image instruction is received, analyzing a target starting address and an enabling signal from the switching image instruction;
Under the condition that the enabling signal is switching image enabling, writing instruction information of the switching image instruction into the driving processor according to the data format requirement of a driving processor carried by the FPGA, and writing the target starting address into a first-in first-out queue of the driving processor so as to realize switching of application programs based on the driving processor and a safety device manager connected with the driving processor;
Reading response data according to the acquired starting address reading instruction;
and under the condition that the initial address of the application program carried in the response data is matched with the target initial address, loading a burning file matched with the target initial address in the memory chip to execute the test function corresponding to the application program.
In one aspect, when the enable signal is a switch image enable signal, writing instruction information of the switch image instruction into the drive processor according to a data format requirement of the drive processor of the FPGA, where the instruction information includes:
Judging whether the format of the enabling signal is the same as the format of the set switching image enabling signal;
And under the condition that the format of the enabling signal is the same as that of the set switching image enabling signal, filling the instruction length and the instruction type of the switching image instruction into the corresponding position of the writing naming header according to the format of the writing command header of the driving processor.
In one aspect, the writing the target start address to the first-in-first-out queue of the drive processor comprises:
writing a low 32-bit data packet containing the target start address into a first-in-first-out queue of the drive processor;
Judging whether the length of the target initial address is higher than 32 bits;
Writing a data packet containing the upper 32 bits of the target start address into a first-in-first-out queue of the drive processor if the length of the target start address is higher than 32 bits;
in the case where the length of the target start address is not higher than 32 bits, the high 32 bits of the target start address are set to 0 to be written into the first-in-first-out queue of the driving processor.
In one aspect, before the reading instruction according to the acquired start address reads the response data, the method further includes:
After the image switching is executed, starting timing;
And under the condition that the timing time reaches the set time threshold, executing the step of reading the response data according to the acquired starting address reading instruction.
In one aspect, the reading the response data according to the acquired start address reading instruction includes:
And writing instruction information of the starting address reading instruction into the driving processor according to the data format requirement of the driving processor so as to facilitate the driving processor to read response data, and storing the starting address of the application program carried in the response data into a set register.
In one aspect, the method further comprises:
And displaying prompt information of application program switching failure under the condition that the starting address of the application program carried in the response data is not matched with the target starting address.
In one aspect, the method further comprises:
And under the condition that a new application program adding instruction is acquired, merging the compiling file corresponding to the new application program with the compiling file corresponding to the historical application program to generate a new burning file, and replacing the original burning file with the new burning file.
The embodiment of the application also provides a multi-application switching device based on the FPGA, which comprises a generating unit, a storage unit, an analyzing unit, an instruction information writing unit, an address writing unit, a reading unit and a loading unit;
the generating unit is used for merging compiled files corresponding to a plurality of application programs to generate a burning file;
The storage unit is used for storing the burning file into a unified memory chip; the burning file records a starting address and a memory use page corresponding to each application program;
the resolving unit is used for resolving a target starting address and an enabling signal from the switching image instruction under the condition that the switching image instruction is received;
The instruction information writing unit is used for writing the instruction information of the image switching instruction into the driving processor according to the data format requirement of the driving processor of the FPGA when the enabling signal is the image switching enabling signal;
The address writing unit is used for writing the target initial address into a first-in first-out queue of the driving processor so as to realize switching of application programs based on the driving processor and a safety device manager connected with the driving processor;
the reading unit is used for reading the response data according to the acquired starting address reading instruction;
The loading unit is configured to load a burn-in file in the memory chip that matches the target start address, so as to execute a test function corresponding to the application program, where the start address of the application program carried in the response data matches the target start address.
In one aspect, the instruction information writing unit includes a judging subunit and a filling subunit;
The judging subunit is configured to judge whether the format of the enable signal is the same as the format of the set switch image enable signal;
and the filling subunit is used for filling the instruction length and the instruction type of the switching mapping instruction to the corresponding position of the writing naming header according to the format of the writing command header of the driving processor under the condition that the format of the enabling signal is the same as the format of the set switching mapping enabling signal.
In one aspect, the address writing unit is configured to write a data packet including a low-order 32 bits of the target start address into a first-in-first-out queue of the driving processor; judging whether the length of the target initial address is higher than 32 bits; writing a data packet containing the upper 32 bits of the target start address into a first-in-first-out queue of the drive processor if the length of the target start address is higher than 32 bits; in the case where the length of the target start address is not higher than 32 bits, the high 32 bits of the target start address are set to 0 to be written into the first-in-first-out queue of the driving processor.
In one aspect, the device further comprises a timing unit;
the timing unit is used for starting timing after image switching is executed; and triggering the reading unit to execute the step of reading the response data according to the acquired starting address reading instruction under the condition that the timing time reaches the set time threshold.
In one aspect, the reading unit is configured to write the instruction information of the start address reading instruction into the driving processor according to a data format requirement of the driving processor, so that the driving processor reads the response data, and stores the start address of the application program carried in the response data into a set register.
In one aspect, the display device further comprises a display unit;
the display unit is configured to display a prompt message indicating that the application program fails to switch when the start address of the application program carried in the response data does not match the target start address.
In one aspect, the device further comprises a replacement unit;
And the replacing unit is used for merging the compiling file corresponding to the new application program with the compiling file corresponding to the historical application program to generate a new burning file under the condition that a new application program adding instruction is acquired, and replacing the original burning file with the new burning file.
The embodiment of the application also provides multi-application switching equipment based on the FPGA, which comprises the following components:
a memory for storing a computer program;
And a processor for executing the computer program to implement the steps of the FPGA-based multi-application switching method as described above.
The embodiment of the application also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program realizes the steps of the multi-application switching method based on the FPGA when being executed by a processor.
According to the technical scheme, compiling files corresponding to a plurality of application programs are combined to generate a burning file, and the burning file is stored in a unified memory chip. The starting address and the memory use page corresponding to each application program are recorded in the burning file. When the switch image instruction is received, the target start address and the enable signal are resolved from the switch image instruction. Under the condition that the enabling signal is the switching image enabling, according to the data format requirement of a drive processor carried by the FPGA, writing instruction information of a switching image instruction into the drive processor, and writing a target starting address into a first-in first-out queue of the drive processor, so that switching of application programs is realized based on the drive processor and a safety device manager connected with the drive processor. In order to ensure that the application program has successfully completed switching, the instruction can be read according to the acquired starting address, and response data can be read; under the condition that the initial address of the application program carried in the response data is matched with the target initial address, the switching of the application program is successfully completed, and at the moment, a burning file matched with the target initial address in the memory chip can be loaded to execute the testing function corresponding to the application program. In the technical scheme, the FPGA is externally connected with only one memory chip, and the automatic switching of different application programs can be completed based on the software programs deployed in the FPGA, so that the FPGA is prevented from being externally connected with a plurality of FLASH chips and chip selection circuits thereof, and the hardware cost and the circuit design complexity are reduced. The FPGA has a plurality of complex functions, the cost performance is obviously improved, the image switching time is short, and the stability is strong.
Drawings
For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flowchart of a multi-application switching method based on an FPGA according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a multi-application switching device based on FPGA according to an embodiment of the present application;
fig. 3 is a block diagram of a multi-application switching device based on FPGA according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.
The terms "comprising" and "having" in the description of the application and the claims and in the above-mentioned figures, as well as any variations thereof that relate to "comprising" and "having", are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed.
In order to better understand the aspects of the present application, the present application will be described in further detail with reference to the accompanying drawings and detailed description.
Next, a multi-application switching method based on FPGA provided by the embodiment of the present application is described in detail. Fig. 1 is a flowchart of a multi-application switching method based on FPGA according to an embodiment of the present application, where the method includes:
S101: and merging the compiled files corresponding to the plurality of application programs to generate a burning file, and storing the burning file into a unified memory chip.
The starting address and the memory use page corresponding to each application program are recorded in the burning file. The compiled file of each application has a corresponding start address. The memory chip comprises a plurality of memory use pages, and different memory use pages of the memory chip can be allocated for each compiled file.
Each application program has a corresponding function, and in order to ensure the implementation of the function, a compiled file can be compiled based on the function required to be implemented by the application program. Each application program has a corresponding compiled file, which may be a sof file.
In the embodiment of the application, the memory chip can adopt a FLASH chip. In the traditional mode, a FLASH chip is required to be connected externally for each function, when a plurality of complex functions are required to be realized, the cost is increased, and the difficulty of circuit design is increased.
In order to reduce hardware cost and circuit design complexity, in the embodiment of the application, a mode of connecting only one FLASH chip with larger capacity outside the FPGA is provided, and in order to ensure smooth switching among different application programs, corresponding software programs can be deployed in the FPGA, and the software programs can be divided into different functional modules according to functions required to be realized, including an instruction analysis module, an image switching module and a switching verification module.
In order to enable one memory chip to manage all application programs, compiled files corresponding to all application programs can be combined to generate a burning file, and the burning file is stored in a memory unit. In practical applications, the burned file may be an rpd file.
S102: when the switch image instruction is received, the target start address and the enable signal are resolved from the switch image instruction.
Each application has its corresponding image, and the switching of the application is actually the switching of the images. Each image has its corresponding one of the functions.
After the default system is started, a certain image is obtained, and when the image is started, if the functions of other images need to be switched, the image can be switched in a mode of issuing instructions.
In actual application, the user may input a switch image instruction through a graphical user interface (GRAPHICAL USER INTERFACE, GUI). The GUI is connected with the FPGA, and can transmit the switching image instruction to the FPGA, so that an instruction analysis module deployed in the FPGA can analyze a target starting address and an enabling signal from the switching image instruction.
The compiled file of each application program has a corresponding start address, and for convenience of distinction, in the embodiment of the present application, the start address parsed in the switch image instruction may be referred to as a target start address.
S103: under the condition that the enabling signal is the switching image enabling, according to the data format requirement of a drive processor carried by the FPGA, writing instruction information of a switching image instruction into the drive processor, and writing a target starting address into a first-in first-out queue of the drive processor, so that switching of application programs is realized based on the drive processor and a safety device manager connected with the drive processor.
The types of the enabling signals are various, and after the enabling signals are analyzed, an image switching module deployed in the FPGA can judge whether the format of the enabling signals is the same as the format of the set switching image enabling signals.
And under the condition that the format of the enabling signal is the same as that of the set switching image enabling signal, the current received switching image instruction is truly used for realizing the switching of the image, and the instruction length and the instruction type of the switching image instruction can be filled into the corresponding position of the writing naming header according to the format of the writing command header of the driving processor.
The structure of the command header (header) is composed as follows:
{4'h0,4'h0,1'b0,command_length-1'b1,1'b0,command}；
Wherein command_length represents the instruction length, and command_length is 0x03 when updating the command; command indicates the instruction type, which is 0x5C (indicating a switch) when the command is updated.
In practice, the image switching module may be connected to a self-contained driver processor (MC) of the FPGA through a memory mapped interface (Avalon MM), and the driver of the MC is finally connected to a Security Device Manager (SDM) of the FPGA.
When the format of the enable signal is determined to be the same as the format of the set switch image enable signal, the command header may be written to the drive processor and the target start address may be written to a first-in-first-out queue (First Input First Output, FIFO) of the drive processor according to the process requirement of the drive processor to write the command.
Considering that the length of the start address is generally not more than 64 bits, the FIFO can only write 32 bits at a time, so that when writing the target start address is performed, the data packet containing the lower 32 bits of the target start address can be written into the FIFO queue of the driving processor. It is determined whether the length of the target start address is greater than 32 bits.
And under the condition that the length of the target initial address is higher than 32 bits, writing the data packet containing the high 32 bits of the target initial address into a first-in first-out queue of the driving processor. In the case where the length of the target start address is not higher than 32 bits, the high 32 bits of the target start address are set to 0 to write to the first-in-first-out queue of the driving processor.
After the writing of the target start address is completed, the driving processor may pull the feedback signal (command_done) high so that the FPGA may know that the driving processor has performed the image switching.
S104: and reading the response data according to the acquired starting address reading instruction.
In the embodiment of the application, in order to verify whether the FPGA has completed the mapping switching, the switching verification module can be utilized to verify the application program which is currently executing.
In practical application, the instruction information of the start address reading instruction can be written into the driving processor according to the data format requirement of the driving processor, so that the driving processor can read the response data, and the start address of the application program carried in the response data is stored in the set register.
The response data includes the following:
word 0-1 represents the starting address of the application currently executing;
word [2-3] represents the offset address in Flash of the application with the highest priority failure;
word [4] represents error coding of the application program which fails to update;
word [5] represents a version of RSU software;
word [6] stores the location of the failed application, if there is no error, return 0;
word [7] stores detailed information of the application program failed to update;
word [8] records the number of retries performed by the current program.
After the response data is acquired, the start address of the application currently being executed in the response data may be stored in a set register.
S105: and under the condition that the initial address of the application program carried in the response data is matched with the target initial address, loading a burning file matched with the target initial address in the memory chip to execute the testing function corresponding to the application program.
In practical application, after the upper computer reads the data of the register through the serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI) bus, the read starting address can be compared with the target starting address.
Under the condition that the read starting address is equal to the target starting address, the switching is successful, and a signal of successful switching can be output, so that the FPGA can acquire that the starting address of the application program carried in the response data is matched with the target starting address, and the FPGA can load a burning file matched with the target starting address in the memory chip at the moment so as to execute the test function corresponding to the application program.
Under the condition that the starting address of the application program carried in the response data is not matched with the target starting address, the prompt information of the switching failure of the application program can be displayed.
For the situation of failure of switching the application program, the switching can be performed after the switching is turned off.
According to the technical scheme, compiling files corresponding to a plurality of application programs are combined to generate a burning file, and the burning file is stored in a unified memory chip. The starting address and the memory use page corresponding to each application program are recorded in the burning file. When the switch image instruction is received, the target start address and the enable signal are resolved from the switch image instruction. Under the condition that the enabling signal is the switching image enabling, according to the data format requirement of a drive processor carried by the FPGA, writing instruction information of a switching image instruction into the drive processor, and writing a target starting address into a first-in first-out queue of the drive processor, so that switching of application programs is realized based on the drive processor and a safety device manager connected with the drive processor. In order to ensure that the application program has successfully completed switching, the instruction can be read according to the acquired starting address, and response data can be read; under the condition that the initial address of the application program carried in the response data is matched with the target initial address, the switching of the application program is successfully completed, and at the moment, a burning file matched with the target initial address in the memory chip can be loaded to execute the testing function corresponding to the application program. In the technical scheme, the FPGA is externally connected with only one memory chip, and the automatic switching of different application programs can be completed based on the software programs deployed in the FPGA, so that the FPGA is prevented from being externally connected with a plurality of FLASH chips and chip selection circuits thereof, and the hardware cost and the circuit design complexity are reduced. The FPGA has a plurality of complex functions, the cost performance is obviously improved, the image switching time is short, and the stability is strong.
In consideration of the fact that the image switching is unstable in the early stage, the acquired response data is easy to be inaccurate, and therefore timing can be started after the image switching is performed. And executing the step of reading the response data according to the acquired starting address reading instruction under the condition that the timing time reaches the set time threshold.
The value of the time threshold can be flexibly set according to actual requirements, for example, can be set to be 2 seconds.
By setting the time threshold, the response data can be read again when the image switching is in a stable state, and the accuracy of the read response data is ensured.
In practical application, the burning file can be dynamically adjusted according to different functions required by the FPGA.
Taking adding a new application as an example, in practical application, a user can input a new application adding instruction through a GUI. Under the condition that the FPGA acquires a new application program adding instruction, combining the compiling file corresponding to the new application program with the compiling file corresponding to the historical application program to generate a new burning file, and replacing the original burning file with the new burning file.
In the embodiment of the application, the requirements of different functions can be met by updating the burning file, so that the FPGA can meet the complex function realization.
By adopting the multi-application switching mode provided by the application, switching and testing of various network functions such as 400G, 200G, 100G, 50G and the like can be realized on the network analyzer, and the testing requirements of manufacturers on different modules at different rates can be met.
Fig. 2 is a schematic structural diagram of an FPGA-based multi-application switching device according to an embodiment of the present application, which includes a generating unit 21, a storing unit 22, an analyzing unit 23, an instruction information writing unit 34, an address writing unit 25, a reading unit 26, and a loading unit 27;
A generating unit 21, configured to combine compiled files corresponding to a plurality of application programs to generate a burned file;
A storage unit 22, configured to store the burned file into a unified memory chip; the burning file records a starting address and a memory use page corresponding to each application program;
A parsing unit 23, configured to parse the target start address and the enable signal from the switch image instruction when the switch image instruction is received;
An instruction information writing unit 24, configured to write instruction information of the switching image instruction into the driving processor according to a data format requirement of the driving processor of the FPGA when the enabling signal is switching image enabling;
An address writing unit 25, configured to write a target start address into a first-in first-out queue of the driving processor, so as to implement switching of the application program based on the driving processor and a security device manager connected to the driving processor;
a reading unit 26 for reading the response data according to the acquired start address reading instruction;
and the loading unit 27 is configured to load the burn-in file in the memory chip that matches the target start address, so as to execute the test function corresponding to the application program, when the start address of the application program carried in the response data matches the target start address.
In some embodiments, the instruction information writing unit includes a judging subunit and a padding subunit;
a judging subunit, configured to judge whether the format of the enable signal is the same as the format of the set switch image enable signal;
And the filling subunit is used for filling the instruction length and the instruction type of the switching mapping instruction to the corresponding position of the writing naming header according to the format of the writing command header of the driving processor under the condition that the format of the enabling signal is the same as the format of the set switching mapping enabling signal.
In some embodiments, the address writing unit is configured to write a low-order 32-bit data packet including the target start address to a first-in-first-out queue of the driving processor; judging whether the length of the target initial address is higher than 32 bits; writing a data packet containing the high 32 bits of the target start address into a first-in first-out queue of the driving processor under the condition that the length of the target start address is higher than 32 bits; in the case where the length of the target start address is not higher than 32 bits, the high 32 bits of the target start address are set to 0 to write to the first-in-first-out queue of the driving processor.
In some embodiments, a timing unit is also included;
The timing unit is used for starting timing after image switching is executed; and triggering the reading unit to execute the step of reading the response data according to the acquired starting address reading instruction under the condition that the timing time reaches the set time threshold.
In some embodiments, the reading unit is configured to write instruction information of the start address reading instruction into the driving processor according to a data format requirement of the driving processor, so that the driving processor reads the response data, and stores a start address of an application program carried in the response data into a set register.
In some embodiments, further comprising a display unit;
The display unit is used for displaying the prompt information of the switching failure of the application program under the condition that the starting address of the application program carried in the response data is not matched with the target starting address.
In some embodiments, a replacement unit is also included;
And the replacing unit is used for merging the compiling file corresponding to the new application program with the compiling file corresponding to the historical application program to generate a new burning file under the condition that a new application program adding instruction is acquired, and replacing the original burning file with the new burning file.
The description of the features in the embodiment corresponding to fig. 2 may be referred to the related description of the embodiment corresponding to fig. 1, and will not be repeated here.
According to the technical scheme, compiling files corresponding to a plurality of application programs are combined to generate a burning file, and the burning file is stored in a unified memory chip. The starting address and the memory use page corresponding to each application program are recorded in the burning file. When the switch image instruction is received, the target start address and the enable signal are resolved from the switch image instruction. Under the condition that the enabling signal is the switching image enabling, according to the data format requirement of a drive processor carried by the FPGA, writing instruction information of a switching image instruction into the drive processor, and writing a target starting address into a first-in first-out queue of the drive processor, so that switching of application programs is realized based on the drive processor and a safety device manager connected with the drive processor. In order to ensure that the application program has successfully completed switching, the instruction can be read according to the acquired starting address, and response data can be read; under the condition that the initial address of the application program carried in the response data is matched with the target initial address, the switching of the application program is successfully completed, and at the moment, a burning file matched with the target initial address in the memory chip can be loaded to execute the testing function corresponding to the application program. In the technical scheme, the FPGA is externally connected with only one memory chip, and the automatic switching of different application programs can be completed based on the software programs deployed in the FPGA, so that the FPGA is prevented from being externally connected with a plurality of FLASH chips and chip selection circuits thereof, and the hardware cost and the circuit design complexity are reduced. The FPGA has a plurality of complex functions, the cost performance is obviously improved, the image switching time is short, and the stability is strong.
Fig. 3 is a structural diagram of an FPGA-based multi-application switching device according to an embodiment of the present application, where, as shown in fig. 3, the FPGA-based multi-application switching device includes: a memory 30 for storing a computer program;
A processor 31 for implementing the steps of the FPGA-based multi-application switching method of the above-described embodiments when executing a computer program.
The multi-application switching device based on the FPGA provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 31 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 31 may be implemented in at least one hardware form of DSP (DIGITAL SIGNAL Processing), FPGA (Field-Programmable gate array), PLA (Programmable Logic Array ). The processor 31 may also include a main processor, which is a processor for processing data in an awake state, also called a CPU (Central Processing Unit ), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 31 may integrate a GPU (Graphics Processing Unit, image processor) for rendering and drawing of content required to be displayed by the display screen. In some embodiments, the processor 31 may also include an AI (ARTIFICIAL INTELLIGENCE ) processor for processing computing operations related to machine learning.
Memory 30 may include one or more computer-readable storage media, which may be non-transitory. Memory 30 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 30 is at least used for storing a computer program 301, where the computer program, after being loaded and executed by the processor 31, can implement the relevant steps of the FPGA-based multi-application switching method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 30 may further include an operating system 302, data 303, and the like, where the storage manner may be transient storage or permanent storage. Operating system 302 may include Windows, unix, linux, among other things. The data 303 may include, but is not limited to, burn files, response data, and the like.
In some embodiments, the FPGA-based multi-application switching device may further include a display screen 32, an input-output interface 33, a communication interface 34, a power supply 35, and a communication bus 36.
Those skilled in the art will appreciate that the architecture shown in fig. 3 is not limiting of FPGA-based multi-application switching devices and may include more or fewer components than shown.
It will be appreciated that if the FPGA-based multi-application switching method in the above embodiments is implemented in the form of a software functional unit and sold or used as a separate product, it may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in part or in whole or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), an electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, a magnetic disk, or an optical disk, etc., which can store program codes.
Based on this, the embodiment of the application further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the FPGA-based multi-application switching method described above.
The method, the device, the equipment and the computer readable storage medium for switching the multiple applications based on the FPGA provided by the embodiment of the application are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The method, the device, the equipment and the computer readable storage medium for switching the multiple applications based on the FPGA provided by the application are described in detail. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
Claims (10)
1. The multi-application switching method based on the FPGA is characterized by comprising the following steps of:
Combining compiled files corresponding to a plurality of application programs to generate a burning file, and storing the burning file into a unified memory chip; the burning file records a starting address and a memory use page corresponding to each application program;
Under the condition that a switching image instruction is received, analyzing a target starting address and an enabling signal from the switching image instruction;
Under the condition that the enabling signal is switching image enabling, writing instruction information of the switching image instruction into the driving processor according to the data format requirement of a driving processor carried by the FPGA, and writing the target starting address into a first-in first-out queue of the driving processor so as to realize switching of application programs based on the driving processor and a safety device manager connected with the driving processor;
Reading response data according to the acquired starting address reading instruction;
and under the condition that the initial address of the application program carried in the response data is matched with the target initial address, loading a burning file matched with the target initial address in the memory chip to execute the test function corresponding to the application program.
2. The FPGA-based multi-application switching method according to claim 1, wherein, in the case where the enable signal is a switch image enable, writing instruction information of the switch image instruction into the drive processor according to a data format requirement of the drive processor of the FPGA comprises:
Judging whether the format of the enabling signal is the same as the format of the set switching image enabling signal;
And under the condition that the format of the enabling signal is the same as that of the set switching image enabling signal, filling the instruction length and the instruction type of the switching image instruction into the corresponding position of the writing naming header according to the format of the writing command header of the driving processor.
3. The FPGA-based multi-application switching method of claim 2, wherein the writing the target start address to the first-in-first-out queue of the driving processor comprises:
writing a low 32-bit data packet containing the target start address into a first-in-first-out queue of the drive processor;
Judging whether the length of the target initial address is higher than 32 bits;
Writing a data packet containing the upper 32 bits of the target start address into a first-in-first-out queue of the drive processor if the length of the target start address is higher than 32 bits;
in the case where the length of the target start address is not higher than 32 bits, the high 32 bits of the target start address are set to 0 to be written into the first-in-first-out queue of the driving processor.
4. The FPGA-based multi-application switching method according to claim 1, further comprising, before the reading of the response data according to the acquired start address read instruction:
After the image switching is executed, starting timing;
And under the condition that the timing time reaches the set time threshold, executing the step of reading the response data according to the acquired starting address reading instruction.
5. The FPGA-based multi-application switching method according to claim 1, wherein the reading response data according to the acquired start address reading instruction includes:
And writing instruction information of the starting address reading instruction into the driving processor according to the data format requirement of the driving processor so as to facilitate the driving processor to read response data, and storing the starting address of the application program carried in the response data into a set register.
6. The FPGA-based multi-application switching method of claim 1, further comprising:
And displaying prompt information of application program switching failure under the condition that the starting address of the application program carried in the response data is not matched with the target starting address.
7. The FPGA-based multi-application switching method of claim 1, further comprising:
And under the condition that a new application program adding instruction is acquired, merging the compiling file corresponding to the new application program with the compiling file corresponding to the historical application program to generate a new burning file, and replacing the original burning file with the new burning file.
8. The multi-application switching device based on the FPGA is characterized by comprising a generating unit, a storage unit, an analysis unit, an instruction information writing unit, an address writing unit, a reading unit and a loading unit;
the generating unit is used for merging compiled files corresponding to a plurality of application programs to generate a burning file;
The storage unit is used for storing the burning file into a unified memory chip; the burning file records a starting address and a memory use page corresponding to each application program;
the resolving unit is used for resolving a target starting address and an enabling signal from the switching image instruction under the condition that the switching image instruction is received;
The instruction information writing unit is used for writing the instruction information of the image switching instruction into the driving processor according to the data format requirement of the driving processor of the FPGA when the enabling signal is the image switching enabling signal;
The address writing unit is used for writing the target initial address into a first-in first-out queue of the driving processor so as to realize switching of application programs based on the driving processor and a safety device manager connected with the driving processor;
the reading unit is used for reading the response data according to the acquired starting address reading instruction;
The loading unit is configured to load a burn-in file in the memory chip that matches the target start address, so as to execute a test function corresponding to the application program, where the start address of the application program carried in the response data matches the target start address.
9. An FPGA-based multi-application switching device, comprising:
a memory for storing a computer program;
A processor for executing the computer program to implement the steps of the FPGA-based multi-application switching method according to any of claims 1 to 7.
10. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the FPGA-based multi-application switching method according to any of claims 1 to 7.
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