KR0132343Y1 - Monitor information control apparatus - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a control device, and more particularly, to a monitor identification information control device applied between a monitor and a computer main body.

2. The technical problem the invention is trying to solve:

A monitor identification information control device for reducing the manufacturing cost of a monitor that reduces the storage structure of an EDID occupying a static access storage space of a microprocessor is provided.

3. Summary of solution of design:

Monitor identification provided in a monitor having a microprocessor and a storage device, the monitor identification information being read out from the storage device in response to the first to third input signals input to the computer body via the first to third signal terminals. An information control apparatus, comprising: a data buffer for pre-transmitting monitor identification information stored in the storage device by the microprocessor; and electrically connected to the first to third signal terminals, and the signal of the first input signal. A multiplexed control panel-specific device for outputting a first or second input signal respectively used as a shift clock pulse according to a state, and electrically connected to the data buffer, the multiplexed control panel-specific device, and a third signal terminal; When the control panel specific device outputs the first input signal used as the shift clock pulse signal, Stops the output of the monitor identification information from the storage device by the microprocessor in accordance with the address state of the third input signal, or shifts the monitor identification information sequentially through the third input terminal by the computer main body. The third signal is directly released by the data shift comparison device when the external data is sequentially shifted into the data buffer by the computer main body, or when the multiplex control panel-specific device outputs a second input signal. And a data shift comparison device which sequentially shifts out the monitor identification information from the terminal to the computer main body.

4. Important uses of the devise:

The manufacturing cost of the monitor is reduced, and a monitor identification information control device conforming to any one of the EDID transmission access methods of DDC 1 / DDC 2B / DDC 2AB defined by the VESA Alliance can be obtained.

Description

Monitor Identification Information Control Device

1 is an exemplary view showing a preferred embodiment of the present invention.

2 (a) to 2 (c) are molding schematics for reading out the EDID showing DDC 1 and DDC 2B as an example.

3 (a) and 3 (b) are schematic diagrams of a memory structure for storing EDIDs in a direct memory method and an indirect memory method, respectively.

The present invention relates to a control device, and more particularly to a monitor identification information control device applied between the monitor and the computer main body.

At present, the connection method between the computer body and the monitor is moving toward the trend of digital control. That is, a monitor requires a microprocessor that performs signal determination and then reads out related data, converts it to voltage at the same time, and transmits it to each related subsequent element to control it. Among them, an extended display identification (hereinafter referred to as EDID) In the reading and operating technology, it is possible for the user to easily use the peripheral device of the computer, and it is not necessary to know the operating environment of the software and hardware standard inside the monitor. Therefore, what can be used by mechanically operating the plug has already become the mainstream of monitor manufacturers.

In order to facilitate the unification and standardization of each monitor maker with respect to the access of this EDID, the VESA Alliance, in particular, is provided with a vertical synchronization signal (Vertical SYNC; VSYNC or VCLK) transmitted by a VGA card provided by all of the computer bodies. IIC bus (including two signal terminals of SCL and SDA) developed by Philips, and also meets the requirements of the following three types of VESA federation to meet various EDID access needs Set.

DDC 1; With VCLK as the clock pulse, EDID data stored in the monitor is transferred to the computer main body by the SDA signal terminal (unidirectional transmission).

DDC 2B; The IIC bus is a two-way transmission channel between the computer body and the monitor.

DDC 2AB; The access bus framed by the IIC bus is a two-way transmission channel between the computer body and the monitor.

By the way, all the said general monitor manufacturers employ | adopt two types of conventional methods, and access EDID.

(a) The added EEPROM is used as a storage medium for storing EDID data, and the EDID data is read through the IIC bus.

However, this method includes two types of standards, DDC 1 and DDC 2B, which are defined by the VESA Federation, but have the following drawbacks.

(1) Increase the space of such a circuit board.

(2) Increase manufacturing costs.

(b) Simulate DDCI with the general input / output pins (I / O pins) of the microprocessor and the vertical synchronization signal, and if the microprocessor has an IIC bus, use the IIC bus in cooperation with software control to It simulates and has the following drawbacks.

(1) The transmission effect of DDC 1 / DDC 2B does not reach the standard established by the VESA Federation. It generates an interrupt using the VSYNC signal, reads EDID data within the execution period of the interrupt service routine, determines that any bit is high or low, and then again returns any I / O. Setting or resetting the O port and outputting one set of data of any EDID results in a time limit for execution in the interrupt service routine of the software, which is equivalent to the transmission rate (25K bits / sec) for DDC 1 by the VESA federation. Because you can't.

(2) Any monitor specified by the VESA Federation shall not meet the requirement to meet at least the specifications of either DDC 1 / DDC 2B or DDC 1 / DDC 2B / DDC 2AB.

(3) By this method being controlled by firmware, the coded firmware becomes relatively long and easy to increase the coding firmware complexity.

Therefore, the main object of the present invention is to provide a monitor identification information control device that conforms to any type of EDID transmission access method of DDC 1 / DDC 2B / DDC 2AB as defined by the VESA Alliance.

It is also a main object of the present invention to provide a monitor identification information control device which reduces the manufacturing cost of the monitor by reducing the memory structure of the EDID occupying the static access storage space of the microprocessor.

Another object of the present invention is to provide a monitor identification information control apparatus that can reduce the processing time of the EDID of the microprocessor.

The monitor identification information control apparatus of the present invention for achieving the above object is provided in a monitor having a microprocessor and a storage device, and the first to third input signals input to the computer body through the first to third signal terminals. A monitor identification information control device which reads monitor identification information from the storage device in response to the data storage device, comprising: a data buffer configured to previously receive the identification information stored in the storage device to the microprocessor, and the first to third signal terminals. A multiplex control panel device, electrically connected to the output device, and outputting a first or second input signal used as a shift clock pulse, respectively, in accordance with the signal state of the first input signal; Electrically connected to a second signal terminal, wherein the multiplexed control panel When outputting the first input signal used as the third input signal, the microprocessor stops outputting the monitor identification information from the storage device according to the address state in the third input signal, or outputs the third data by the computer main body. The monitor identification information is sequentially read out through a signal terminal, or the external data is sequentially written into the data release device by the computer main body, and the multiplex control panel-specific device outputs a second input signal. And a data shift comparison device which shifts the monitor identification information to the computer main body sequentially from the third signal terminal by a data shift comparison device.

Among them, the first, second and third signal terminals are SCL signal terminals, VSYNC (vertical synchronization signal) and SDA signal terminals, respectively, and the monitor identification information is a set of EDID (Extended Display Identification).

The multiplex control panel device is electrically connected to the first and third signal terminals, generates and outputs a multiplex selection signal in accordance with the signal state of the first input signal, and also the mode in the third input signal. A control panel-specific device for determining to start or stop the transmission operation of the monitor identification information according to a state, and electrically connected to the first and second signal terminals, a control panel-specific device, and a data shift comparator, and selecting the multiplex And a multiplex selection device for outputting first and second input signals to the data shift comparator, respectively, as the signals are in the first and second selection states.

Among them, the control panel-specific apparatus determines the start or stop of the transmission operation of the monitor identification information by detecting the mode state in the third input signal in accordance with the signal open and stop states.

Wherein, when the first input signal is in a high level signal state, the multiplex select signal is in the second select state to output the second input signal from the multiplex selector, or the first input. When the signal is converted from a high level signal state to a low level signal state, the multiplex selection signal is converted to a first selection state to output the first input signal from the multiplex selection device.

Among these, when the first input signal is in a low level signal state, the multiplex select signal is in a second select state to output the second input signal from the multiplex selector, or the first input signal. When is converted from the low level signal state to the high level signal state, the multiplex select signal is converted to the first select state to output the first input signal from the multiplex selector.

Among them, the first and second selection states are high level or low level states, respectively, or the first and second selection states are low level or high level states, respectively.

Among them, the multiplex selector is a two-to-one multiplexer.

Among them, the data shift comparison device is electrically connected to the third signal terminal, the data buffer and the multiplex control panel-specific device, and the third shift signal is output in accordance with the first or second input signal used as the shift clock pulse signal. A shift register which reads in an input signal or monitor identification information stored in the data buffer and sequentially outputs the monitor identification information to a third signal terminal, and shifts and memorizes the external data in the data buffer sequentially; An address storage device for storing a set of fixed addresses, and electrically connected to the shift register and the address storage device, wherein the at least two sets of fixed addresses and the address state are compared for equality, and the comparison result is the same. Shift-in or shift of monitor identification information or the external data When running-out operation, and the other hand the comparison result is not the same is achieved by having an address comparator for outputting the display identification information from the storage device by stopping the microprocessor.

The data shift comparator further includes an input / output buffer electrically connected between the third signal terminal and the shift register and providing a signal buffer function.

Among them, the storage device is an electronic erasing program ROM (EEPROM).

Among them, the memory device includes a static memory device (SRAM) and a read-only memory device (ROM).

Among these, in the monitor identification information, the variable and fixed portions of the monitor identification information are stored in the EEPROM and the ROM, respectively, in a direct reading method.

In addition, in the monitor identification information indirectly in a read memory manner, both uniqueness data and direct related data in the monitor identification information are stored in the EEPROM, and the ROM is a memory index address value of the uniqueness data and direct related data. Remember.

When the user performs the DDCI standard defined by the VESA federation, and the user reads the EDID data from the storage device and outputs it to the main body of the computer, the SCL signal input from the SCL signal terminal to the control panel device is in a high level state. Since the mode flag register DDC is set low, the EDID data input by the data buffer and stored in the shift register directly to the computer main body by outputting a VSYNC signal to the shift register by the multiplex selector. Can be printed.

At this time, if the user performs the standard of DDC 2B or DDC 2AB defined by the VESA federation, and the user reads EDID data from the storage device and outputs it to the computer body, the SCL signal is converted from the high level state to the low level state. At the same time, the mode flag register DDC is set high through the control panel device in accordance with the signal conversion edge which outputs a 1-series clock pulse signal and simultaneously converts the signal from the high level state to the low level state.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing a preferred embodiment of the present invention, consisting of a computer body 1 and a monitor 2. Among them, the computer main body 1 includes VSYNC signal terminals from SDA, SCL, and VGA cards (not shown), and these SDA and SCL signal terminals constitute an IIC bus. Of course, the VSYNC signal terminal is for inputting the VSYNC signal, and the SCL signal terminal is for inputting the SCL signal.

Monitor 2 comprises a microprocessor 21 and a memory 22 (e.g., EEPROM), of which microprocessor 21 includes static memory (SRAM) 211, read-only memory (ROM) 212, and monitor identification. An information control device 213 and a data bus 214 are provided. The monitor identification information control device 213 includes a data buffer 2131, a multiplexer control panel device 2132, and a data shift comparator 2133. The multiplex control panel device 2132 includes a control panel device 21321 and a multiplex selector 21322. The data shift comparator 2133 includes a shift register 21331, an address memory device 21332, an address comparator 21333, and an input / output buffer 21334. Is done.

R / W, ADDR, DDC, START, and STOP in FIG. 1 are read / write flag registers, address comparison result flag registers, mode flag registers, signal start flag registers, and signal stop flag registers, respectively. to be.

Next, the operation of the block shown in FIG. 1 will be described to better understand the technical spirit of the present invention.

First, when the user performs the standard of DDC 1 defined by the VESA federation, and the user reads the EDID data from the storage device 22 and outputs it to the computer main body 1, the SCL signal input from the SCL signal terminal to the control panel-specific device 21321 is high. Since it is in the level state and puts the mode flag register DDC in the low state, it is input from the data buffer 2131 and stored in the shift register 21331 by outputting a VSYNC signal to the shift register 21331 by the multiplex selector 21322. The generated EDID data can be directly output to the computer main body 1.

If the DDC 2B or DDC 2AB specified by the VESA Alliance is followed and the user reads the EDID data from the storage device 22 and outputs it to the computer main body 1, the SCL signal is converted from the high level state to the low level state. At the same time, the mode flag register DDC is made high through the control panel-specific device 21321 according to the signal conversion edge which outputs a 1-series clock pulse signal and simultaneously converts the signal from the high level state to the low level state.

In addition, when the control panel-specific device 21321 inputs an input signal (including an address state) from the SDA signal terminal and an appropriate flag corresponding to the signal start flag register START and the signal stop flag register STOP appears, respectively, through the input / output buffer 21334. The multiplex selector 21322 stores the SCL signal in the shift register 21331 so that the input signal input from the SDA signal terminal is sequentially stored in the shift register 21331.

First, the address state and one set of addresses (e.g., 1010000) in the address storage device 21332 are compared by the address comparator 21333. When the comparison result is high, it indicates that the addresses are the same and enters the DDC 2B mode. Enter Otherwise, when the address state and the other one set of addresses (the value can be set by the user) in the address storage device 213321 are the same, they are switched to the DDC 2AB mode or the mode set by the user. Of course, if the address state and the two sets of addresses stored in the address storage device 21332 are different from each other, this indicates error information, and the monitor identification information control device 213 does not perform any EDID access operation.

If this is the DDC 2B mode and the flag state in the read / write flag register is high (indicating that it is a read state), the shift register 21331 is used as a shift clock pulse signal in cooperation with the high flag state of the read / write flag register. The EDID data input by the data buffer 2131 is sequentially shifted out to the computer main body 1 in accordance with the SCL signal.

Similarly, if the read / write flag register is low (ie, in a write state), the computer main body 1 writes external data to the shift register 21331 by means of the SDA signal and the SCL signal through the input / output buffer 21334. Thereafter, once the external data is completely shifted in the shift register 21331, the external data is automatically output to the data buffer 2131, and the external processor reads out the external data.

However, the data buffer 2131 has a function of pre-fetching. The reason for this is as follows.

For example, the EDID data in the shift register 21331 has already completed the shift output every time the nine VSYNC signals have passed, so that the EDID data in the data buffer 2131 is loaded into the shift register 21331 and the EDID data when the next VSYNC signal is received. To be transmitted. Therefore, after the EDID data in the data buffer 2131 is shifted to the shift register 21331, the control panel-specific apparatus 21321 automatically interrupts the interrupt signal (the sign of FIG. 2). To be noticed) to notify the microprocessor 21. At this time, the interrupt service program in the microprocessor 21 shifts the next set of EDID data into the data buffer 2131 for transfer. In this way, the transmission speed of the EDID data is accelerated.

2 (a) to 2 (c) are schematic diagrams of reading EDID using the preferred embodiments of the present invention, taking DDC 1 and DDC 2B as an example. 2 (a) is a state diagram in which EDID data is output from the data buffer 2131 to the computer main body 1 by using DDC 1 as an example, and FIG. 2 (b) is a state diagram in which the computer main body 1 uses the DDC 2B mode as an example. Fig. 2 (c) is a schematic diagram of a signal state for writing data by the computer main body 1 by taking the DDC 2B mode as an example. In Figs. 2 (a) to 2 (c), a symbol S denotes a start state bit, a symbol P denotes a stop state bit, a symbol A denotes a confirmation signal bit, and a symbol N denotes an unconfirmed signal bit, respectively. The schematic diagrams of the signal states disclosed in FIGS. 2 (a) and 2 (c) are well known to those skilled in the art and will not be described.

Further, EDID data stored in the ordinary microprocessor 21 and the storage device 22 are classified into the following two types by the data structure.

1. Data that does not change regardless of the type of monitor, and

2. Data changed by monitor type.

Therefore, by understanding the structure of the entire data of the EDID, the amount of SRAM 211 used in the microprocessor 21 can be reduced by the storage structure and access method listed below.

(a) providing for direct reading of EDID data;

(a1) Hardware Memory Structure

The EDID is separated into both parts of the invariant portion (FE in FIG. 3 (a)) stored in the ROM 212 in the microprocessor 21 and the variable portion (VE in FIG. 3 (a)) stored in the storage device 22. When the microprocessor 21 starts up, first, the partial EDID data located in the storage device 22 is shifted in to the SRAM 211, and then the EDID data is sequentially sent to the computer main body 1 through software control.

(a2) Software reading / writing method

After the microprocessor is started, the EDID data divided into two parts is stored in the SRAM 211 and the ROM 212, respectively. Then, the start address, the threshold address, and the last address of the EDID data section are software by one EDID. The data is read into the data buffer 2131.

(b) Indirectly provides for reading EDID data.

(b1) Hardware storage structure

All of the EDID data is rearranged, leaving only a few n bytes to be directly related data, and at the same time deleting duplicates from the remaining data, leaving only unique data (no duplicate data). Thereafter, the unique data and the directly related data (code EDID 'in FIG. 3 (b)) are stored in the storage device 22. As shown in FIG. The ROM 212 in the microprocessor 21 has a space of 128 bytes, and each byte has one index (address), and the address location of the SRAM 211 storing EDID 'data is used as an index. When the microprocessor 21 starts up, the EDID 'data is shifted from the storage 22 to the SRAM 211 in the microprocessor 21, and the EDID' data is transferred to the computer main body 1 by software program control.

(b2) Software reading / writing method

The indirect data reading method starts at the point of the index memory section, and after 128 bits are read, the EDID 'data is output to the computer main body 1. See Figure 3 (b).

As described above, according to the method of the present invention, not only the manufacturing cost of the monitor is reduced, but also the monitor identification information conforming to the EDID transmission access method of any one of the DDC 1 / DDC 2B / DDC 2AB defined by the VESA Alliance. It is possible to obtain a control device and to have an industrial useful value.

Claims (8)

Monitor identification provided in a monitor having a microprocessor and a storage device, the monitor identification information being read out from the storage device in response to the first to third input signals input to the computer body via the first to third signal terminals. An information control apparatus, comprising: a data buffer for pre-transmitting monitor identification information stored in the storage device by the microprocessor; and electrically connected to the first to third signal terminals, and the signal of the first input signal. A multiplexed control panel-specific device for outputting a first or second input signal respectively used as a shift clock pulse according to a state, and electrically connected to the data buffer, the multiplexed control panel-specific device, and a third signal terminal; When the control panel specific device outputs the first input signal used as the shift clock pulse signal, Stops output of the monitor identification information from the storage device by the microprocessor or shifts the monitor identification information sequentially through the third input terminal by the computer main body in accordance with the address state of the third input signal. The third signal is directly released by the data shift comparison device when the external data is sequentially shifted into the data buffer by the computer main body, or when the multiplex control panel-specific device outputs a second input signal. And a data shift comparison device for shift-outputting the monitor identification information to a computer main body sequentially from a terminal. 2. The apparatus of claim 1, wherein the second and third signal terminals are respectively an SCL signal terminal, a VSYNC (vertical synchronization signal), and an SDA signal terminal, wherein the monitor identification information is a set of EDID, Electrically connected to the first and third signal terminals, generating and outputting a multiplex selection signal in accordance with the signal state of the first input signal, and transmitting the monitor identification information in accordance with the mode state of the third input signal; A control panel specific device for determining to start or stop an operation, the first and second signal terminals, a control panel specific device, and a data shift comparator electrically connected to each other, wherein the multiplex selection signal is in a first and second selection state; And a multiplex selector for outputting first and second input signals to the data shift comparator, respectively, in response to being present. . The apparatus according to claim 2, wherein the control panel-specific apparatus determines the start or stop of the transmission operation of the monitor identification information by detecting the mode state in the third input signal in accordance with the signal start and stop states. The flex selector is a monitor identification information control device, characterized in that it is a two-to-one multiplexer. 3. The method of claim 2, wherein when the first input signal is in a high level state, the multiplex select signal is in the second select state, and outputs the second input signal from the multiplex selector. When the input signal is converted from the high level signal state to the low level signal state, the multiplex select signal is converted to a first select state to output a first input signal from the multiplex selector, or the first input signal Is in a low level state, the multiplex select signal is in a second select state to output the second input signal from the multiplex selector, and the first input signal is a high level signal from the low level signal state. The multiplex selection signal is converted into the first selection state when the signal is converted to the state, and the first input signal is transmitted from the multiplex selection device. And the first and second selection states are a high level state or a low level state, respectively, or the first and second selection states are a low level state or a high level state, respectively. Device. The data shift comparator according to claim 1, wherein the data shift comparator is electrically connected to the third signal terminal, the data buffer, and the multiplex control device, and is used in accordance with the first or second input signal used as the shift clock pulse signal. A shift for reading out the monitor identification information stored in the third input signal or the data buffer and sequentially outputting the monitor identification information to the third signal terminal and shifting and storing the external data in the data buffer sequentially. A register, an address storage device for storing at least two sets of fixed addresses, and an electrically connected device to the shift register and the address storage device, and comparing the at least two sets of fixed addresses with the state of the addresses and comparing them If the result is the same, the monitor identification information or the shift of the external data When running-in or shift-out operation, and conversely the comparison is not equal to the monitored identification information control apparatus characterized in that it comprises an address comparator for outputting the display identification information from the storage device by stopping the microprocessor. 6. The data shift comparator according to claim 5, wherein said data shift comparator comprises an input / output buffer electrically connected between said third signal terminal and said shift register and providing a signal buffer function, said storage device being electronically erased. A program ROM (EEPROM), wherein the memory device includes a static memory device (SRAM) and a read-only memory device (ROM). 6. The monitor identification information control apparatus according to claim 5, wherein the monitor identification information is stored directly in the EEPROM and the ROM, respectively, in the EEPROM and the ROM. The method according to claim 5, wherein in the monitor identification information, both uniqueness data and direct related data in the monitor identification information are stored in the EEPROM in an indirectly read storage manner, and the ROM is configured to directly identify the uniqueness data and the direct data. And a memory index address value of the associated data.