KR100425692B1 - External memory access apparatus for processor - Google Patents

Abstract

The present invention relates to an external memory access device of a processor, and an external memory access device of a conventional processor is not easy to debug because it is impossible for the processor to read or write data by designating a specific address of the external memory in a debugging mode. There is a problem in that the use efficiency is lowered because other additional equipment is required. In view of the above problems, the present invention determines a debugging mode, and outputs a register accessible by designating a specific address of the external memory in the debugging mode, and extracts and displays the state of the external memory to the user. ; A processor which sets an internal register in a debugging mode under the control of the host computer, and accesses a specific address of the external memory using the set register; It is composed of an external memory that outputs the data of the corresponding address or stores the recording data in the corresponding address according to the register set in the processor in the debugging mode, and the user uses a host computer to designate a specific address of the external memory in the debugging mode. By designating the data at the address or reading the recorded data, the debugging can be performed more easily, which increases the efficiency of the device. Debugging without connecting a separate device is possible. This can be done in-house, which speeds up debugging and improves reliability.

Description

EXTERNAL MEMORY ACCESS APPARATUS FOR PROCESSOR}

The present invention relates to an external memory access device of a processor, and more particularly, to an external memory access device of a processor capable of performing debugging by accessing an external memory by switching to a debugging mode while the processor is performing normal operation.

In general, the processor has an external memory in addition to the internal memory, and the processor accesses necessary data from the external memory to perform a data patch (FETCH).

However, since the processor itself cannot designate a specific address when storing or reading data in the external memory, debugging of the processor is not easy, and the external memory access device of the conventional processor is described in detail with reference to the accompanying drawings. The explanation is as follows.

FIG. 1 is a block diagram illustrating a connection relationship between a conventional processor and an external memory. As shown in FIG. 1, the processor 1 may include a read / write signal EXTRWB for determining reading or writing of data and an external memory 2. The chip enable signal EXTDSB, the strobe signal EXTMSTRB, and the address signal EXTA which are enabled are transmitted to the external memory 2 in the normal operation mode, and thus data is written to or written to the external memory 2. The read data (D) can be read.

When the processor 1 operates in the normal mode, the read / write signal EXTRWB, the chip enable signal EXTDSB, the strobe signal EXTMSTRB, and the address signal EXTA of the processor 1 are generated. ) To decide whether to record or read the data.

However, during debugging of the processor 1, the user goes through a process of reading and verifying data stored in the external memory 2 by using additional equipment in order to know a value stored in the external memory 2.

At this time, since the processor 1 cannot designate a specific address of the external memory 2, only the data of the specific address of the external memory 2 cannot be read or written to the address.

That is, while the processor 1 is performing a normal operation, it stops the operation, checks the error of the processor 1 on hardware, and if there is an error, during a debugging operation to correct the error, a specific address of the external memory 2 is provided. Since it is impossible to read and write the data, it is impossible to perform a smooth debugging operation. Accordingly, the external memory 2 is controlled using a separate means capable of controlling the external memory.

As described above, the external memory access device of the conventional processor is not easy to debug because the processor is unable to read or write data by designating a specific address of the external memory in the debugging mode, and also requires other additional equipment. There was a problem that the efficiency is lowered.

It is an object of the present invention to provide an external memory access device of a processor which enables a processor to write and read data by designating a specific address of the external memory when debugging itself.

1 is a block diagram of an external memory access device of a conventional processor.

Figure 2 is a block diagram of an external memory access device of the processor of the present invention.

3 is a detailed block diagram of the processor of FIG.

Figure 4 is a main signal waveform diagram in normal mode operation of the external memory access device of the processor of the present invention.

FIG. 5 is a detailed circuit diagram of scan cells CELL2 to CELL7 in FIG.

FIG. 6 is a detailed circuit diagram of the scan cell CELL1 in FIG.

Fig. 7 is a diagram of the major partial signal waveforms in the debugging mode of the present invention.

Figure 8 is an embodiment of a shift-in signal of the host computer to which the present invention is applied.

Figure 9 is a waveform diagram of a signal for controlling the external memory in the debugging read mode of the external memory access device of the processor of the present invention.

Figure 10 is a waveform diagram of a signal for controlling the external memory in the debug write mode of the external memory access device of the processor of the present invention.

* Description of the symbols for the main parts of the drawings *

1: processor 2: external memory

3: Host computer 4: Core part

5: Clock control section 6: External memory interface section

The above object includes a host computer including an address for accessing a specific address of an external memory according to a user's setting, and outputting a control signal necessary for the operation of the external memory; In the debugging mode, the register of the host computer is received and only the set register among the registers is selected and stored, and the stored register is temporarily transferred to the external memory to write data to a specific address of the external memory or read the recorded data. It is achieved by having a plurality of scan cells provided in the processor, which will be described in detail with reference to the accompanying drawings, the present invention as follows.

FIG. 2 is a block diagram of an external memory access device of a processor of the present invention. As shown therein, an operation mode of the processor 1 is determined and an address and an external memory 2 of the external memory 2 to be accessed in the debugging mode. A host computer 3 outputting a control signal for controlling the operation and displaying data of the external memory 2 accessed in the debugging mode; The processor 1 is configured to access a specific address of the external memory 2 in a debugging mode under the control of the host computer 3 to read or write data, and output the information to the host computer 3.

3 is a configuration diagram of an external memory access device provided in the processor 1 according to the present invention. As shown in FIG. 3, the processor 1 receives data from the external memory 2 by internal processing, Outputs data to be stored in the external memory 2 and generates a write data enable signal DOUTEN, a read / write signal EXTRWB, a chip enable signal EXTDSB, a strobe signal EXTMSTRB, and an address signal EXTA. A core portion 4 for outputting a); A clock control unit (5) for supplying a debug clock to the core unit (4) in a debugging mode; In the normal mode, the data DOUT, the write data enable signal DOUTEN, the read / write signal EXTRWB, the chip enable signal EXTDSB, the strobe signal EXTMSRTB, and the address signal Scan cells CELL2 to CELL7 that apply EXTA to the external memory 2 and extract the data in the debugging mode and transmit the data to the host computer 3; Scan cell CELL1 that applies data read from the external memory 2 to the core unit 4 and transmits the data of the extracted external memory 2 to the host computer 3 in the debugging mode. and; The data of the scan cell CELL2 is output to the external memory 2 or the data of the external memory 2 is applied to the scan cell CELL1 according to the write enable signal EXTDOUTEN output from the scan cell CELL3. It consists of an external memory interface unit (6).

Hereinafter, the configuration of the present invention configured as described above and the operation and action of the configuration in more detail.

First, in the normal mode of operation, the debugging mode signal DEBUG_MODE applied from the host computer 3 is applied at a low potential.

As described above, when the debugging mode signal DEBUG_MODE is low, the scan cells CELL2 to CELL7 of the processor 1 transmit the read / write signal EXTRWB applied from the core unit 4 as it is.

In addition, the chip enable signal EXTDSB and the address signal EXTA are transmitted as they are.

In the read mode, the low-potential write enable signal EXTDOUTEN is output from the scan cell CELL3 to which the low potential write enable signal DOUTEN is applied to block the operation of the buffer BUFF. Data read from a specific address of the external memory 2 operated in accordance with the application is applied to the core unit 4 through the scan cell CELL1.

At this time, in the write mode, the write data EXTDOUT of the core unit 4 is buffered through the buffer BUFF of the external memory interface unit 6 and applied to the external memory 2 as the data D to desired data. Is written to a specific address of the external memory 2.

The waveform diagram of each signal at this time is shown in FIG.

That is, when the debugging mode signal DEBUG_MODE transmitted from the host computer 3 is at low potential, each scan cell CELL2 to CELL7 retains the output of the core unit 4 as it is through the external memory interface unit 6. Applied to (2), the external memory 2 is accessed, and a read or write operation is performed. In addition, the scan cell CELL1 applies the data read from the external memory 2 to the core unit 4 as it is.

In FIG. 4, the operation of the debugging mode is performed from the section where the debugging mode signal DEBUG_MODE transitions to the high potential, which will be described later.

The scan cells CELL1 to CELL7 have two forms, which will be described in more detail.

FIG. 5 is an internal circuit diagram of the scan cells CELL2 to CELL7 according to the present invention, and includes a plurality of multiplexers MUX1 to MUX4 as shown in the figure, with debug clock signals DEBUGCLK interposed therebetween. With the flip-flops FF1 and FF2 operating, in the debugging mode, the signal output from the core unit 4 is blocked, and the registers set by shifting the registers output from the host computer 3 are located. Holding the shifting operation to store each set register, and transfer each register to the external memory 2 at a given moment to access a specific address of the external memory 2, and access of the external memory 2 at that time It is configured to record data at the designated address.

FIG. 6 is an internal configuration diagram of the scan cell CELL1. As shown in FIG. 6, the scan cell CELL1 transferring data from the external memory 2 to the core unit 4 has two multiplexers MUX5. , MUX6) and a flip-flop (FF3) to transmit the data (DIN) of the external memory (2) read during debugging to the host computer (3) to check the data stored in a specific address of the external memory It is configured to be.

At this time, the multiplexer MUX4 operates by the debugging mode signal DEBUG_MODE to output the output signal of the core unit 4 to the external memory 2 or to access an address designated by the host computer 3. The output signal can be selectively outputted, and the clock signal CLOCKDR, the update signal UPDATEDR, and the shift signal SHIFTDR, which are the control signals of the remaining host computer 3, control the external memory 2 in the debugging mode. The selection point of the signal for applying each signal to the host computer 3 is determined.

Hereinafter, the debugging mode operation of the present invention by applying the above signals will be described in more detail.

First, a waveform diagram of a signal transmitted between the host computer 3 and the processor 1 and an external signal transmitted between the host computer 1 and the external memory 2 in the debugging mode is shown in FIG. 7. .

In the debugging mode, the clock control unit 5 outputs the debug clock signal DEBUG_CLK as the debugging mode signal DEBUG_MODE is applied at a high potential.

In this state, the clock signal CLOCKDR is applied at high potential.

At this point, each signal output from the core unit 4 is blocked by the operation of the multiplexer MUX4 included in each of the scan cells CELL2 to CELL7. 0 and 1 displayed at the input terminals of the multiplexers MUX1 to MUX4 indicate that the selection signal is selected when the low potential and the high potential are respectively.

In addition, while the debug_clock signal DEBUG_CLK is generated, the main clock signal input to the core of the processor 1 is not applied, and the processor 1 stops its operation.

In such a state, the clock signal CLOCKDR is applied at high potential, and the shift signal SHIFTDR is applied at high potential in the period of the next debug clock signal DEBUG_CLK, and the multiplexes included in each of the scan cells CELL2 to CELL7 are provided. The registers MUX1 and MUX2 select and output the registers input to the input terminal SI, thereby storing them in the flip-flop FF1.

The register is a shift in signal (SHIFTIN) applied from the host computer (3).

FIG. 8 is an exemplary diagram of a shift-in signal SHIFTIN input from the host computer 3, and includes each signal required for operation control of an external memory as shown.

That is, writing data for writing data to the address signal A, the strobe signal MSTRB, the chip enable signal DSB, the read / write signal RWB, and the external memory 2 to be accessed in the external memory 2. A space corresponding to the corresponding bit is inputted into the enable signal DOUTEN, the read data DIN area in which the data DOUT to be written and the data read from the external memory 2 are stored.

As such, when the shift-in signal SHIFTIN having the above configuration is applied to the multiplexers MUX1 and MUX2 of the scan cells CELL2 to CELL7, the information is flip-flop ( FF1) is sequentially output through the register output stage SO.

In this state, the data to be written DOUT included in the shift-in signal SHIFTIN transmitted from the host computer 3 is located in the scan cell CELL2, and the write enable signal is written in the scan cell CELL3. (DOUTEN), read / write signal RWB to scan cell CELL4, chip enable signal DSB to scan cell CELL5, strobe signal MSTRB to scan cell CELL6, address to scan cell CELL7 Let signals A be located respectively.

In this case, the read data DIN area, which is a storage space for the shift-in signal SHIFTIN, is located in the scan cell CELL1, and the clock signal CLOCKDR and the clock signal are set after setting the registers of the scan cells CELL1 to CELL7 as described above. The shift signal SHIFTDR is applied at a low potential to change the selection state of the multiplexers MUX1 and MUX2 included in the scan cells CELL2 to CELL7 to hold the registers stored in the flip-flop FF1.

In addition, the multiplexers MUX5 and MUX6 of the scan cell CELL1 are prepared to accept the data DIN output from the external memory 2.

In this state, when the update signal UPDATEDR is applied at high potential, the multiplexer MUX3 of each of the scan cells CELL2 to CELL7 stores the registers stored in the flip-flop FF1, respectively. Transfer to the external memory (2) through.

At this time, in the read mode, the operation of the buffer BUFF of the external memory interface unit 6 is interrupted, the read / write signal RWB is applied to the external memory 2, the chip enable signal DSB, and the strobe. A signal MSTRB and an address signal A are applied.

Accordingly, the data DIN of the address corresponding to the address signal A of the external memory 2 is accessed and applied to the host computer 3 through the flip-flop FF3 of the scan cell CELL1.

The memory access state at this time is shown in FIG.

That is, since the write enable signal DOUTEN is in the read mode, the write enable signal DOUTEN is output at a low potential to stop the operation of the buffer BUFF of the external memory interface unit 6 so that the data DIN of the external memory 2 is scanned. It can be introduced into the cell (CELL1).

In addition, the read / write signal RWB is applied to the external memory 2 at a high potential which is a signal for operating in a read mode.

In addition, the chip enable signal DSB and the strobe signal MSTRB are applied at low potential to enable the external memory 2, and access the address corresponding to the address signal A to read the data DIN.

Through this process, by accessing a specific address of the external memory 2 in the debugging mode and reading the data, it is possible to determine whether there is an abnormality of data stored at a specific address of the external memory 2.

In the write mode, the data to be debugged may be stored in the write data area DOUT of the shift-in signal SHIFTIN and written to a specific address of the external memory 2.

That is, after setting the registers to the scan cells CELL1 to CELL7 through the operation described above, the registers set to the scan cells CELL2 to CELL7 are applied to the external memory by applying the update signal UPDATEDR at high potential. (2).

As such, an operation waveform diagram of a process of performing a write operation in the debugging mode is illustrated in FIG. 10.

The write enable signal DOUTEN is applied at a high potential to operate the buffer BUFF of the external memory interface 6 so that the data DOUT to be written is applied to the external memory 2, and the read at this time. The write signal RWB is applied to the external memory 2 at a low potential indicating the write mode so that the external memory 2 can operate in the write mode.

The chip enable signal DSB and the strobe signal MSTRB are applied at a low potential to enable the external memory 2 to write the data DOUT at the corresponding address A. FIG.

As described above, the present invention can read or write data of a specific address of the external memory 2 in the debugging mode under the control of the external host computer 3 inside the processor 1, thereby improving the efficiency of debugging. Therefore, debugging can be easily performed without connecting other external devices.

As described above, in the external memory access device of the microprocessor of the present invention, a user may designate a specific address of the external memory in the debugging mode and write data to or read data from the address in the debugging mode. It is effective to increase the use efficiency of the device by making debugging easier, and debugging can be done within itself without connecting a separate device, so that debugging speed can be improved and reliability thereof can be improved. It works.

Claims (6)

A host computer for determining a debugging mode, outputting a register accessible by designating a specific address of the external memory in the debugging mode, and extracting and displaying a state of the external memory to a user; Core unit for reading data of external memory or outputting data to write to external memory in normal operation mode and outputting write / read control signal, chip enable signal, strobe signal and address signal of external memory, and In operation mode, signals or data input and output to and from the core unit are transmitted as they are, and in debugging mode, each signal included in a register of the host computer is selectively stored and simultaneously applied to an external memory to transmit data to a specific address of the external memory. A plurality of scan cells for writing or reading the data and control signals outputted through the plurality of scan cells are applied to an external memory, and data from the scan cells is applied to the external memory, or data from the external memory is applied. Processor composed of an external memory interface to apply to a specific scan cell .; And an external memory for outputting data of a corresponding address or storing write data at a corresponding address according to a register set in the processor in the debugging mode. The register of claim 1, wherein the register output by the host computer stores an area storing data read from an external memory, a data area to be written, a write enable signal, a read / write control signal, a chip enable signal, a strobe signal, and an external device. An external memory access device of a processor comprising an address signal for designating a specific address of a memory. delete The register of claim 1, wherein the plurality of scan cells receive a register applied from the host computer on one side and sequentially shift a register to receive a corresponding signal, and store a register for controlling an external memory, respectively. And accessing the external memory by applying the stored register to the external memory, and shifting the data read from the external memory to the host computer. The method according to claim 1 or 4, wherein each of the plurality of scan cells, each of which stores a register of the host computer, uses a plurality of multiplexers to select a register applied by the control of the host computer, and by a debugging clock signal. An external memory access device of a processor, characterized by shifting the register using an operating flip-flop and storing only the register corresponding to the scan cell. The scan cell of claim 1 or 4, wherein the scan cell that receives and stores data of the external memory and outputs the data to the host computer stores and transmits the data of the external memory using a flip-flop operated by a debugging clock signal. External memory access device of the processor, characterized in that.