JP3022685B2 - Static bus driver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static bus driver, and more particularly to a static bus driver formed by a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional static bus driver includes NAND circuits 2 and 2, respectively.
Including an inverter 3, a NOR circuit, a PMOS transistor 5 and an NMOS transistor 6, the data signal D ₁ ,
D ₂ , D ₃ ,..., D _n and control signals CT ₁ , CT ₂ ,
CT _3, ......, _3-state buffer 1-1, 1-2, 1-3 to enter the CT _n, ......, the output of 1-n is 0
When the output of any one of these three-state buffers becomes "1" level, the data signal is amplified, and the data signal is amplified. Drives the bus 201.

FIGS. 6 (a), 6 (b), 6 (c) and 6 (d)
Are timing charts of respective signals showing the operation in the conventional example, and show a clock signal φ, a data signal D ₁ , a control signal CT _1, and a potential V _B31 of a 31-bit bus line 203, respectively. .

[0004]

In the above-mentioned conventional static bus driver, since the load capacity of the bus is large, it is required to provide a buffer having a large driving capability at the last stage. The number of the last stage is plural (l) for one bus wiring, the bus width is plural (m), and some have plural (n) types of buses. Therefore, the total number of buffers is 1 × mx
n, which is an enormous number. Accordingly, there is a disadvantage that the layout area of the semiconductor integrated circuit forming the static bus driver becomes large.

[0005]

SUMMARY OF THE INVENTION According to the present invention, a static
The bus driver is formed by a semiconductor integrated circuit,
In a static bus driver for driving and controlling a potential level of a predetermined bus line, a predetermined low-level reference voltage and a potential level of the bus line are input, compared and collated, and a predetermined level signal is output. A first voltage level comparison circuit, a second reference voltage of a predetermined high level, and a potential level of the bus wiring, which are compared and collated, and a second voltage level comparison circuit for outputting a predetermined level signal; A latch circuit that holds a potential of a wiring for a period of one clock, a first NAND circuit that performs an AND operation on an output of the latch circuit and an output of the first voltage level comparison circuit; A second NAND circuit for performing an AND operation between an output of the circuit and an output of the second voltage level comparison circuit; a source connected to a predetermined power supply;
, A drain connected to the bus wiring, a drain connected to the drain of the PMOS transistor, and an inverted output of the second NAND circuit input to the gate. And an NMOS transistor having a source connected to the ground potential. The latch circuit may be a rising edge static data flip-flop.

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The present embodiment is an example of a static bus driver using a two-phase clock system formed by a semiconductor integrated circuit, and as shown in FIG. Bus wiring 202
Corresponding to the NAND circuit 2, the inverter 3,
NOR circuit 4, PMOS transistor 5, and NMOS
3-state buffer 1-1 including transistor 6
n, voltage level comparison circuits 7 and 8, NAND circuits 9 and 10, inverter 11, PMOS transistor 12, NMOS transistor 13, latch circuit 14-1 including inverters 15, 16 and 17, and latch circuit Latch circuit 1 having the same configuration as 14-1
4-2 and an input circuit 18.

In FIG. 1, 0-bit bus wiring 202
In the potential V _B0 is 0V (volts), when you attempt to pulling through any one of the 3-state buffers of the potential of the 3-state buffers 1-1 to 1-n is the potential V _B0 is Is pulled up, and its potential becomes low reference voltage V _RL (≒
0.5V), the output 102 of the potential level comparator 7 goes to the "1" level.
The PMOS transistor 12 is driven via the circuit 9, and raises the potential V _B0 of the bus wiring 202. At this time,
When the potential V _B0 of the bus wiring 202 is higher than ₀ V, the reference voltage V
_While the output 103 changes to _RH (≒ 4.5 V), the output 103 of the potential level comparator 8 is also at the “1” level. In this case, one of the bus lines 202 is controlled so that the NMOS transistor 13 is not driven. By the latch circuits 14-1 and 14-2 for remembering the state before the clock,
If the potential V _B0 of the bus wiring 202 one clock before is 0 V, the NAND circuit 10 and the inverter 11 are provided as a circuit for changing the output level 103 of the potential level comparator 8 from the active state to the inactive state. I have.

Next, the potential V _B0 of the bus wiring 202 is 5 V
In order to reduce this potential via any one of the three-state buffers 1-1 to 1-n, the potential is set to the high reference voltage V _RH (≒ 4.
5V) or less, the output 103 of the potential level comparator 8 becomes "1" level, thereby
NMOS through a D circuit 10 and an inverter 11
The transistor 13 is driven, and the potential V
_B0 is reduced to 0V. At this time, while the potential V _B0 of the bus wiring 202 changes from 5 V to the low reference voltage V _RL (≒ 0.5 V), the output 102 of the potential level comparator 7
Is also at the "1" level. In this case, the bus wiring 202 is controlled so that the PMOS transistor 12 is not driven.
Latch circuit 1 for remembering the state one clock before
According to 4-1 and 14-2, if the potential V _B0 of the bus wiring 202 one clock before is 5 V, the potential level comparator 7
The NAND circuit 9 is provided as a circuit for changing the output 102 from the active state to the inactive state.

Next, when the potential V _B0 of the bus line 202 remains at 0 V and does not change, the output 101 of the latch circuit 14-2 is at the “0” level, and the output 102 of the voltage level comparison circuit 7 is also at the “0” level. At the “0” level, the output 103 of the voltage level comparison circuit 8 goes to the “1” level, so that the buffer composed of the PMOS transistor 12 and the NMOS transistor 13 is not driven, and therefore, the bus wiring 20
The potential V _B0 of 2 is output as 0 V only by the 3-state buffers 1-1 to 1-n. In this case, since there is no change in voltage, there is no problem in terms of operation speed. Finally, when the potential V _B0 of the bus wiring 202 remains at 5 V and does not change, the output 101 of the latch circuit 14-2 becomes the “1” level, and the output 102 of the voltage level comparison circuit 7 becomes the “1” level. Since the output 103 of the voltage level comparison circuit 8 becomes "0" level, the buffer composed of the PMOS transistor 12 and the NMOS transistor 13 is not driven, whereby the potential V _B0 of the bus wiring 202 becomes three-state buffer 1− 5V is output only by 1 to 1-n. In this case, no problem occurs in the operation speed because the voltage does not fluctuate.

2 (a), 2 (b), 2 (c), 2 (d),
(E), (f), (g) and (h) are timing diagrams of the respective signals during the above operation. In FIG.
Data signal D ₁ input to 3-state buffer 1-1
, The PMOS transistor 5 having a small gate width included in the three-state buffer 1-1 is driven, and the potential V _{B0 of} the 0-bit bus line 202 starts to rise. When the potential V _B0 of the bus line 202 exceeds the low reference voltage V _RL , the PMOS transistor 12 having a large gate width is driven, and the potential V _B0 of the bus line 202 is raised to 5 V by the PMOS transistors 5 and 12. The fall of the data signal D ₁ then 3
N with small gate width included in state buffer 1-1
MOS transistor 6 is driven, and potential V _{B0 of} 0-bit bus line 202 starts to fall. Then, when the potential V _B0 of the bus wiring 202 falls below the high reference voltage V _RH ,
The NMOS transistor 13 having a large gate width is driven, and the potential V _B0 of the bus line 202 is reduced to 0 V by the NMOS transistors 6 and 13.

[0012] Incidentally, Shown in FIG. 3 (a) and 3 (b), in the timing diagram shown in FIG. 2, the clock signal phi _1, at the time and falling the rising of the data signal D _1, the bus lines FIG. 4 is an enlarged timing chart showing a potential V _{B0 of} 202 and outputs 102 and 103 of voltage level comparison circuits 7 and 8; The dotted lines in FIGS. 3A and 3B show the rising and falling states of the potential V _B0 of the bus wiring 202 in the conventional example.

FIG. 4 is a block diagram showing a second embodiment of the present invention. This embodiment is an example of a static bus driver using a single-phase clock system formed by a semiconductor integrated circuit. As shown in FIG.
A three-state buffer 1 including a NAND circuit 2, an inverter 3, a NOR circuit 4, a PMOS transistor 5 and an NMOS transistor 6, corresponding to the bus wiring 201 of the 31st bit and the bus wiring 202 of the 0th bit, respectively.
-1 to 1-n, voltage level comparison circuits 7 and 8, N
AND circuits 9 and 10, inverter 11, PMO
S transistor 12 and NMOS transistor 13
And a latch circuit 19 including OR circuits 20 and 22, NAND circuits 21 and 23, AND circuits 24 and 25, and NOR circuits 26 and 27. As is apparent from FIG. 4, the present embodiment differs from the first embodiment in the configuration of the latch circuit 19, and the other components are exactly the same as those in the first embodiment. . The reason why the configuration of the latch circuit in this embodiment is different from that of the first embodiment is that, when a single-phase clock is used, when the latch circuit used in the first embodiment is used, the data signal This is because punch-through occurs and an expected signal cannot be obtained. Therefore, as a latch circuit, FIG.
As shown in (1), the use of the rising edge static data flip-flop realizes a smaller circuit scale. Of course, even in the case of the two-phase clock system, there is no problem even if the rising edge static data flip-flop is used, but the circuit configuration shown in FIG. It has the advantage of ending.

[0014]

As described above, the present invention provides a method for comparing two voltage levels with a small number of transistor components in a static bus without delaying the operating speed of the rise and fall of the potential of the bus wiring. By adding a circuit, a latch circuit, and one buffer having the same dimensions as the conventional one, the dimensions of the three-state buffers themselves are significantly reduced as compared with the conventional example driven by only the three-state buffers. This makes it possible to realize a static bus driver in which the layout area of the semiconductor integrated circuit is significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation in the first embodiment.

FIG. 3 is an enlarged timing chart showing an operation in the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a timing chart showing an operation in the second embodiment.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a timing chart showing an operation in a conventional example.

[Explanation of symbols]

 1-1 to 1-n 3-state buffer 2, 9, 10, 21, 23 NAND circuit 3, 11, 15 to 17 inverter 4, 26, 27 NOR circuit 5, 12 PMOS transistor 6, 13 NMOS transistor 7, 8 Voltage Level comparison circuit 14-1, 14-2, 19 Latch circuit 20, 22 OR circuit 24, 25 AND circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 3/00 H03K 19/0175

Claims (2)

(57) [Claims] 1. A static integrated circuit formed by a semiconductor integrated circuit for driving and controlling a potential level of a predetermined bus line.
In the bus driver, a first voltage level comparison circuit that inputs and compares a predetermined low-level reference voltage and the potential level of the bus wiring and outputs a predetermined level signal; A second voltage level comparison circuit that inputs and compares a reference voltage and a potential level of the bus line and outputs a predetermined level signal; and a latch circuit that holds the potential of the bus line one clock before. A first NAND circuit that performs an AND operation on an output of the latch circuit and an output of the first voltage level comparison circuit; an output of the latch circuit; and an output of the second voltage level comparison circuit. A second NAND circuit for performing a logical AND operation of the first NAND circuit; a source connected to a predetermined power supply;
An output of an AND circuit is input, a PMOS transistor having a drain connected to the bus wiring; a drain connected to the drain of the PMOS transistor; an inverted output of the second NAND circuit input to a gate; And a NMOS transistor connected to a ground potential. 2. The static bus driver according to claim 1, wherein a rising edge static data flip-flop is used as said latch circuit.